CN105871730A - Novel compact, efficient and fast on-chip network router based on network coding - Google Patents
Novel compact, efficient and fast on-chip network router based on network coding Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/60—Router architectures
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0076—Distributed coding, e.g. network coding, involving channel coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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Abstract
The invention discloses a novel compact, efficient and fast on-chip network router based on network coding. The router comprises P ways of input and output channels, wherein each input channel is provided with v virtual channels; each input channel is provided with one routing logic and a virtual channel allocator which are respectively responsible for a routing direction of data transmission and allocation of the virtual channels; the virtual channel allocator is also connected to a switch allocator; the switch allocator is responsible for allocating crossbars to the P ways of input channels, so that arbitration of one output channel is simultaneously requested by multiple input channels; network coding modules NCU are also arranged between the P ways of input channels and the cross switches; the output of flits of the virtual channel passes through a simple coding selection circuit, the NCU carries out coding operations on the input which conforms to the conditions, after the coded flits are arbitrated by the switch allocator, the flits are sent to the crossbars. The on-chip network router supports a transmission mode with the flits as a unit, the real-time coding is realized and the additional hardware and power consumption can be effectively reduced.
Description
Technical field
The present invention relates to the research field of network router, particularly to a kind of Novel compact based on network code, height
Effect, quick network-on-chip router.
Background technology
Along with the sustainable development of semiconductor technology, one chip accommodates the quantity of transistor and is continuously increased, and integrated circuit steps
Multinuclear (multiple-core) or many-core (many-core) epoch are entered.Core relies on network-on-chip (Network-on-
Chip or NoC) link together, the overall performance of chip is improved by concurrent operation.At present, many-core chip has been carried out
The application of substantial amounts of business.Such as: cloud computer single-chip cloud computer " the single-chip cloud of Intel 48 core
Computer " and the TILE-Gx72 single-chip of Tilera 72 core.These chips be widely used in supercomputing, cloud computing,
In the systems such as big data.
Scale and the degree of parallelism of many-core chip constantly increase, and the reliable interconnection between core becomes increasingly to be stranded with communicating
Difficulty, bus and point-to-point interconnection mode gradually can not meet the performance of interconnection on sheet and extendible needs, there has been proposed
Network-on-chip mode based on packet switch.The application of many-core chip is continuously increased, and in chip, the concurrent cooperation between core is day by day
Closely, the data volume transmitted each other continues to increase, and needs to support increasingly complex network behavior.Additionally, complicated many multicasts
(multi-session multicast) communication is applied the most frequent, such as: Cache concordance and biography in many-core chip
Defeated shared data etc..These factors add the traffic of network-on-chip, cause network congestion, reduce the property of network-on-chip
Can, add the power consumption of whole chip.People are badly in need of new network-on-chip design to improve performance and energy consumption efficiency.
The proposition of network-on-chip concept is at about 2000, uses for reference the data transmission shape of macroscopic view computer network packet switch
Formula and the frame mode of shared physical channel, support with " microplate (flit) " transmission mode as unit.1999, masschusetts, U.S.A
Static and dynamic two set communication networks are combined by the Raw microprocessor of Polytechnics, jointly realize multiple processor core
Work in coordination with and communicate；Guerrier and Greiner proposed based on fat tree (fat-tree) structure and packet switch SPIN in 2000
On-chip network structure.Calendar year 2001, Dally and Towles analyzes the feature of SOC(system on a chip) hardware resource, it is proposed that one general
NoC model, thus demonstrate network-on-chip in the feasibility solving SoC interconnection；In the same year, Benini and Micheli proposes NoC's
Stratification tectonic model.Subsequently, researchers expand widely studied in network-on-chip field, it is proposed that a series of online
Network structure, more influential have: CHAIN and SpiNNaker of Univ Manchester UK, Bologna university of Italy and U.S.
The XPIPES of Stanford University of state, PHILIPS Co.The NOSTRUM of KTH of Sweden, France UPMC
The SPIN of university, and the MANGO etc. of Denmark Polytechnic University.
Along with polycaryon processor and the development of shared market demand, increasingly complex network behavior, such as multicast
(multicast) significant consideration of network-on-chip design, is become.The data transmission of network-on-chip mainly has clean culture
(unicast) transmission and multicast transmission.Multicast can realize by multiple unicast operation, but efficiency is the lowest.Researchers
Numerous studies have been done, it is proposed that the NoC framework of multiple support multicast and multicast optimization algorithm in terms of multicast network-on-chip.
Merolla et al. proposes a kind of tree routing device supporting multicast, can be by broadcast (sites) in turn in subtree (subtree)
Mode realizes multicast.Stefan et al. proposes the on-chip network structure of a kind of time-sharing multiplex, supports QoS, multicast and efficient
Connection establishment mechanism.Abad et al. proposes a kind of new routing mechanism supporting multicast, utilizes the method for multicasting of self adaptation tree to protect
Demonstrate,prove correctly transmitting and without the restriction routeing, therefore improve the performance of CMP multicast of multicast.Samman et al. proposes one
Just can realize deadlock-free multicast without tunnel, the router of NoC supports following functions: if some packet is hindered
Fill in, before the microplate of other packet is inserted into them, thus avoid deadlock.You Zhiqiang et al. proposes based on BFT
The network-on-chip of type proposes a kind of multicast routing protocol and nodes encoding design, has been used for the multicast to identical core and has surveyed
Examination, reduces test application time.
The concept of network code is put forward in 2000 by Ahlswede et al. for the first time.It is a kind of network data
Transmission means, extends concept and the function of traditional routing.In traditional network based on route, network node (router,
Switch etc.) only carry out the forwarding of data and replicate two operations；And after employing network code, network node can be right
The data received carry out arbitrary encoding operation (such as linear transformation etc.), then coding result is replicated or forwarded.With tradition net
Network is compared, and the advantage of network code is mainly reflected in multicast application, can promote throughput, it is achieved directed networks
The multicast capacity (multicast capacity) of (directed networks).Network code just causes state once proposition
The extensive concern of border academia, it is theoretical and application has become network and the new focus of communications field research.
Introducing of network code brings certain extra consumption to network, as extra encoding operation, complicated router,
Bigger caching.In network code, needing on the premise of meeting throughput, use simple calculations as far as possible, less has
Confinement, and reduce the quantity of coding nodes.For given network topology structure, find minimum finite field and reach network
Capacity has NP difficulty.C.Fragouli and E.Soljanin is at " Information flow decomposition
For network coding " in prove that the size of finite field is closely related with the number of destination node, and give one
The upper bound of minimum finite field.Similar, finding minimum coding nodes number also has NP difficulty.M.Langberg,
First A.Sprintson, and J.Bruck will in " The encoding complexity of network coding "
General network is converted to so-called simple network.The method using simple network, obtains under network that is acyclic and that have ring respectively
Go out the Lower and upper bounds of coding nodes number.C.Fragouli and E.Soljanin utilizes greedy algorithm, it is proposed that one new
Network information flow model studies coding nodes and the optimization of coding limit number.Coding nodes, coding limit optimize and can also apply
Genetic algorithm (genetic algorithm).M.Kim, C.W.Ahn, M.M é dard, and M.Effros is at " On
Minimizing network coding resources:An evolutionary approach " in first be considered as lose
Propagation algorithm Optimized Coding Based limit number.For the coding of chromosome, first network G is converted to the line chart G ' of correspondence.For each
Encoding scheme, using the bit vectors of code coefficient composition on the corresponding all limits of line chart G ' as chromosome coding.With coding limit
Quantity as the adaptive value of chromosome.Preliminary simulation result shows, the result of application genetic algorithm is better than greedy algorithm.
The research team of Texas A&M University proposes to be applied to network code integrated electricity for 2006 for the first time
Interconnection field, road.Jayakumar, Khatri and Gulati et al. be application network coding techniques in ASIC bus, reduces energy consumption
7%～8.5%, reduce interconnection bus length and area 6%～10%.Subsequently, the application extension of network code is arrived by they
FPGA interconnects field, achieves good effect.This research team have also been devised a kind of bidirectional bus supporting network code, net
Network coding techniques can utilize a bidirectional bus to realize the bandwidth of two one-way bus, saves the bus resource and 11% of 49%
Bus energy consumption.
2011, the concept of network code was applied in network-on-chip by Indrusiak for the first time, inquires into it in NoC group
Broadcast the potential advantages in communication.The angle of the jumping figure (hops) that article transmits from packet, compares network coding and XY
The sum of the required hop of routing transmission, tentatively demonstrates the advantage being applied in NoC by network coding.Analytical table
Bright, network code can reduce the transmission jump number of 10%～22%.Thuan et al., should by network code in terms of hardware realizes
In CMP, devise the router supporting network code, it was demonstrated that in the CMP of 9 cores, network code can drop significantly
Low network delay, and improve the handling capacity 1.48 times of network.Shalaby et al. mainly considers that butterfly network is under 2D-mesh
Optimization problem, it is proposed that 5 algorithms selecting intermediate source node is and middle destination node i d, it was demonstrated that network code is permissible
Reduce transmission jump number 12%～35%.The optimization problem of network code is expanded to general group from butterfly network by Vonbun et al.
Broadcast topological structure, demonstrate network code theoretically and can reduce the bag transmission range of network-on-chip.A.Shalaby,
V.Goulart, and M.-S.Ragab is at " Study of application of network coding on NoCs for
Multicast communications " in document [33], it was demonstrated that use the network code can also in multicast application effectively
Reduce transmission delay.Hu et al. is it is also proposed that with the on-chip network structure of network coding technique, achieve Preliminary Results, but circuit sets
Meter and experimental result describe and unintelligible.
From above document analysis it can be seen that the research work in terms of network coding technique is applied to network-on-chip is firm
Ground zero, relevant achievement in research is the most comprehensive.These preliminary explorations demonstrate network-on-chip and can effectively utilize network to compile
Code technology improves network throughput, reduces transmission delay, saving transmission energy consumption.But, major part technology is all confined to butterfly net
The structure of network, and butterfly network is a special case of network code application.Although butterfly network is expanded to one by some technology
As multicast topology structure and give theoretical performance, but literary composition is not mentioned concrete networking code construction to realize this
A little theoretical performances.But (Intra-session) coding in being still confined to multicast.Compiled by (Inter-session) between multicast
Code, we should realize bigger performance gain.Additionally, the rough theory that these documents are mostly based on network code is commented
Estimating, lack accurate time delay and power consumption experimental data under side circuit environment, optimized algorithm is also based on existing network coding reason
Opinion, not structure and performance characteristics for network-on-chip are not improved targetedly, it is difficult to realize to network code for
The facilitation of network-on-chip carries out comprehensive, comprehensive research and evaluation.
Summary of the invention
Present invention is primarily targeted at the shortcoming overcoming prior art with not enough, it is provided that a kind of based on network code new
Type network-on-chip router compact, efficient, quick.
In order to achieve the above object, the present invention is by the following technical solutions:
The invention provides a kind of Novel compact based on network code, network-on-chip router efficient, quick, this road
Being included the input of P road, output channel by device, each input channel is provided with again v tunnel, and the input channel on each road all sets
There is a routing logic Routing Logic and virtual channel allotter VC allocator, be each responsible for data transmission
Route direction and distribution tunnel；Virtual channel allotter VC allocator is also associated with switch divider Switch
Allocator, described switch divider Switch allocator is overall parts, is responsible for P road input channel and divides
Joining cross bar switch crossbar, it is achieved multiple input channels ask the president of same output channel simultaneously, Crossbar is one
Individual cross bar switch, it is achieved the rapid data transmission of P road input channel to P road output channel, at P road input channel and cross bar switch
Being additionally provided with network code module NCU between Crossbar, the microplate of tunnel exports through simple codes selection circuit, nothing
The microplate that need to encode or do not encode herein is directly sent to cross bar switch Crossbar；Encode if in this router
Microplate, then deliver to network code module NCU, qualified input is performed the encoding operation by NCU, encoded microplate warp
After the arbitration of switch divider Switch allocator, it is sent to cross bar switch.
As preferred technical scheme, router is by revising the logic of routing logic Routing Logic parts
Circuit realiration multicast functionality.
As preferred technical scheme, described network code module NCU includes input buffer Input buffer and defeated
Going out buffer Output buffer, input allotter Input allocator is according to the sky of input buffer Input buffer
Not busy state is input distribution buffer queue, output moderator Output arbiter arbitration two-way coding output, it is ensured that intersect and open
The use closing Crossbar does not conflicts.
As preferred technical scheme, described network code module NCU scanning input buffer Input buffer, check
Whether there are effective data to be encoded, and check these data paired data with or without alignment, if two paths of data is the most here, net
Network coding module NCU just carries out data encoding, and revises packet header, forms the packet after new coding, delivers to the defeated of free time
Go out in buffer Output buffer.
As preferred technical scheme, the pack arrangement supporting network code is defined as follows:
One packet is made up of several microplates Flit, including a packet header Head, several load datas Payload
Comprising control information with bag tail Tail, Head and a Tail, put in Payload is valid data.
As preferred technical scheme, Head comprises the key control information supported network transmission and encode, by 9 parts
Constituting, definition and the function of each part are as shown in table 1:
Definition from above table is it can be seen that just may be used just with NC type, Dist to IS and Dist to ID
To determine which router is two data wrap in and perform the encoding operation, and which router to carry out multicast transmission at.
As preferred technical scheme, packet Dist to IS=2 at the beginning, often through a router Dist to
IS subtracts 1, until is router becomes 0, represents and does network code in is, and is is intermediate source node, and it is a router,
It is again an encoder, the raw data packets that two-way inputs is encoded according to the order of microplate；This packet is sent to
In NCU, after Dist to IS is less than 0, representing that network code completes, it is not necessary to change, now Dist to IS keeps-1 not again
Becoming, Dist to ID represents and also to arrive middle destination router through a how many router, needs packet is carried out two
Road multicast transmission.
The present invention compared with prior art, has the advantage that and beneficial effect:
1, network-on-chip based on network code is designed the comprehensive study carried out by the present invention, it is achieved to hardware, power consumption,
The accurately assessment of performance and modeling, it is proposed that a kind of novel compact network-on-chip data packet coding structure, with the least volume
Outer hardware, time delay and energy expenditure, design the efficient network-on-chip router supporting microplate transmission mode so that extra is hard
Part resource the most only accounts for 1/5th (routers for 5 ports of router.For the router of multiport, additionally
Consume less), solve alignment and the real-time coding problem of microplate in packet well.This design being network-on-chip provides
New method and thinking, have theory and practice for improving network-on-chip and the performance of many-core chip, reduction power consumption further
Novelty.
2, in terms of concrete implementation technological means, the present invention has gathered network code, network-on-chip, on-chip multi-processor
With the newest research results in terms of low-power consumption, merge the related discipline knowledge such as signal theory, integrated circuit and computer, theoretical with
Practice combines, and physical modeling and emulation experiment combine, and finally draws achievement in research.
3, the laboratory facilities of network-on-chip circuit design relate to IC design and Simulation Software Design, such as Fig. 3 institute
Show.NoC circuit design uses the method that IC design eda software instrument and FPGA combine with modeling, concrete such as institute on the left of Fig. 3
Show.The present invention utilizes FPGA to accelerate the efficiency of behavior simulation, the correctness of checking function, and utilizes eda tool emulation testing to go out
The time delay of each parts of new network-on-chip and power consumption, and carry out accurate time delay and power consumption modeling.
Accompanying drawing explanation
Fig. 1 (a)-Fig. 1 (b) is respectively network code in butterfly network coding structure figure and network-on-chip and processes figure；
Fig. 2 is the schematic diagram of the alignment problem that the network code in units of microplate brings；
Fig. 3 is the flow chart of the present embodiment experimental technique；
Fig. 4 is the structure chart of inventive network router；
Fig. 5 is the schematic diagram that the present invention supports network code pack arrangement.
Detailed description of the invention
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention do not limit
In this.
Embodiment
The proposition of network code be in traditional macro network environment (such as radio sensing network, computer network
Deng), the router of these networks has stronger process and storage function, and while supporting routing function, can be enough to should
Pay the extra work of network code.Further, for the time delay of Relative Network transmission and power consumption, the volume that network code is consumed
Outer time delay and power consumption are the least or be negligible.But, network-on-chip is a kind of for speed and hardware resource requirements pole
Its strict micronet, it processes and caching capabilities is the most weak, it is impossible to consume the most extra hardware and energy consumption resource is come
Support network code.
Fig. 1 (a) is a typical butterfly network coding structure: s1, s2 are two multicast source nodes；D1, d2 are two
Destination's node of multicast；Is is intermediate source node, and it is a router, is again an encoder, is inputted by two-way
Raw data packets encodes according to the order of flit, then forwards；Id is middle destination node, the coding received
After packet be transmitted to the destination direction of multicast respectively.Intermediate source node is need receive from s1, s2 packet A,
B, makees simple XOR and processes, and is then transferred to middle destination node i d.Packet delivery is given by middle destination node i d
d1、d2.D1, d2 carry out XOR with packet A or B after receiving packet A B, obtain B or A.
In macro network in (such as wireless network), time and energy consumption required for network transmission are far longer than nodes
According to the time processed, is and id is generally processor node, has stronger disposal ability and bigger caching.Packet A, B
XOR process is just carried out after completely arriving at is.
But, in the network-on-chip as shown in Fig. 1 (b), the speed of network transmission requirement is exceedingly fast, the process of network code and
Distribution otherwise can not will have a strong impact on the speed of network-on-chip through processor node (such as nis, nid).These operations must
(is, id) must be completed by network-on-chip router (router).But, the recovery operation (such as B=A A B) of network code
Can complete in destination's node (such as d1, d2).
It is known that the router of network-on-chip only supports that the circuit-level that speed is exceedingly fast exchanges and routing operations, and delay
Deposit the least, using microplate (flit) as the unit of transmission, it is impossible to accommodate a complete packet (package).Therefore, new
The network-encoding operation of network-on-chip also must be in units of flit, and can not be in units of package.Owing to network-on-chip is deposited
Blocking, the transmission of microplate is likely to occur discontinuously, brings huge difficulty to the network code of router, as shown in Figure 2.
The square (starting with c) that in Fig. 2, Lycoperdon polymorphum Vitt is filled represents the flit after XOR coding.Situation 1 is optimal situation,
I.e. packet A, B length is equal, and arrives a certain intermediate source node simultaneously.The microplate simultaneously arrived is entered by this intermediate source node
Row XOR processes, and forms new microplate (c0-c6) and sends.Situation 2 represents that packet A, B two clock cycle of difference arrive
Reach.A0, a1 and b5, b6 cannot be carried out network code and process.Situation 3 represents to be affected by network congestion, and packet A, B's is micro-
Sheet arrives intermediate source node intermittently, and the situation of network code becomes sufficiently complex so that the recovery of follow-up data is by pole
Big impact.
Additionally, as shown in Fig. 1 (b), after chip once completes, its multicast node position, network characteristic, link bandwidth etc. are all
Cannot change.And the optimisation technique of existing network code allows network structure and parameter to change according to the requirement optimized
Become.This generates the new problem of network code optimisation technique.
The technology path of two key cores is as follows:
1) the network-on-chip circuit design of network code is supported
The key issue of this respect is the design of NoC router.The present invention is on the NoC road of classical support tunnel
Improved by the basis of device, be allowed to both support traditional exchange route function, support again microplate encoding function, as shown in Figure 4.
This router has P I/O channel, each input channel to have v tunnel.The input channel on each road has one
Routing Logic and VC allocator, is each responsible for route direction and the distribution tunnel of data transmission.Switch
Allocator is overall parts, is responsible for P input channel distribution cross bar switch crossbar, it is achieved multiple inputs
Passage asks the president of same output channel simultaneously.Crossbar is a cross bar switch, it is achieved P road is input to the output of P road
Rapid data transmission.The network-on-chip router of 2D-mesh topological structure has 5 ports (P=5), be respectively east, south, west,
Northern and local.The NoC router of 3D-mesh topological structure has 7 ports (the most upper and lower).Router can be by amendment
The logic circuit of Routing Logic parts realizes multicast functionality.
New router adds network code module (Network Coding Unit or NCU).Tunnel micro-
Sheet exports through simple codes selection circuit (according to the definition of table 1 below, check Dist to IS=0, NC Type=1),
Microplate without encoding or do not encode herein is directly sent to cross bar switch Crossbar；Compile if in this router
The microplate of code, then deliver to network code parts (NCU).Qualified input is performed the encoding operation by NCU.Encoded is micro-
Sheet, after the arbitration of Switch allocator, is sent to cross bar switch.Therefore, a road input of cross bar switch is many NCU, become
Having become the cross bar switch of (P+1) xP, the cross bar switch of the PxP of classical router has increased, but ratio is the least.
The circuit structure design of NCU is as shown in Fig. 4 lower part, it is assumed that be the 2D-mesh router of 5 inputs.NCU has 5
Input, the most be up to 4 circuit-switched data bags need coding, weave into two-way coding output.Therefore, in figure, input is 5, input buffering
Device (Input buffer) is 4, and output buffer (Output buffer) is 2.Input allocator is according to Input
The idle condition of buffer is input distribution buffer queue.Output arbiter arbitration two-way coding output, it is ensured that
The use of Crossbar does not conflicts.
Network coding is the critical component of addressable part.It scans 4 Input buffer, and check whether there is has
The data to be encoded of effect, and check these data paired data with or without alignment.If two paths of data is the most here, Network
Coding just carries out data encoding, and revises packet header (package head), forms the packet after new coding, delivers to sky
In not busy Output buffer.
Input Buffer plays well effect for the microplate alignment solving network code, and we can compile at network
Code optimization algorithm increases the sequential calculating that bag sends so that packet arrives the time synchronized of coding nodes.Such as, Fig. 1 (b)
In, the packet of s2 sends early than 1 sequential of packet of s1, A and B can arrive is simultaneously.If there is slight obstruction,
Input Buffer can realize the caching of A and B so that they have alignd and have carried out coding transmission again.If the Input of a bag
Buffer is full, and another bag does not the most arrive, the most do not do encoding operation according to, the mode of routine transmits.It practice, also
Tunnel can be utilized to ensure the QoS of data to be encoded transmission, it is ensured that packet to be encoded does not blocks, so that
The phenomenon not lined up seldom occurs.
From fig. 4, it can be seen that the structure of NCU is like adding the circuit of a road tunnel, mainly by buffering FIFO, secondary
Cutting out device, cross bar switch is constituted.It can thus be appreciated that support the additional hardware needed for the NoC router of network code and few (for 5 tunnels
NoC router, extra consumption is 1/5th of router；For high base router, extra consumption is less).Due to raising property
Can and the additional hardware resources that introduces can accept.Additionally, the size of Input buffer is taken at the packet of network code
Size and our flit alignment strategy.Can utilize with accurate optimized algorithm, greater compactness of data micro sheet structure enter one
Step reduces the area of Input buffer.The existence of Output buffer can smooth the transmission speed of a lower network, but this
Function can also be completed by Input buffer.Output buffer sets or sets much, will be determined by emulation experiment.
And network code is simple xor operation, shared circuit resource is few.To sum up, the additional hardware resources needed for NCU is
Entirely acceptable.
2) compact data packet coding scheme
In order to realize network code in network-on-chip, need the bag form of data transmission is recompiled definition,
Support that network-on-chip is with the microplate (flit) transmission mode as ultimate unit.The present invention defines and supports the pack arrangement of network code such as
Shown in Fig. 5.One packet is made up of several microplates (Flit), including packet header (Head), several load datas
(Payload) and one bag tail (Tail).Head and Tail comprises control information, and put in Payload is valid data.
Head comprises the key control information supported network transmission and encode, and is made up of 9 parts.The definition of each part
As shown in table 1 with function.
The composition of table 1 Head and function
From defined above it can be seen that be assured that two just with NC type, Dist to IS and Dist to ID
Which router is individual data wrap in performs the encoding operation, and which router to carry out multicast transmission at.As shown in Fig. 1 (b), s2 to is
Packet Dist to IS=2 at the beginning, often subtract 1 through a router Dist toIS, arrived is router and become 0, table
Showing and do network code in is, this packet is sent in NCU.After Dist to IS is less than 0, represent that network code is complete
Becoming, it is not necessary to change, now Dist to IS holding-1 is constant again.Dist to ID represents and also to arrive through a how many router
Middle destination router, needs packet is carried out two-way multicast transmission.Its operating principle is identical with Dist to IS.
The laboratory facilities of network-on-chip circuit design relate to IC design and Simulation Software Design, as shown in Figure 3.
NoC circuit design uses the method that IC design eda software instrument and FPGA combine with modeling, the most as shown on the left side of figure 3.This
Invention utilizes FPGA to accelerate the efficiency of behavior simulation, the correctness of checking function, and utilizes the sheet that eda tool emulation testing makes new advances
The time delay of each parts of upper network and power consumption, and carry out accurate time delay and power consumption modeling.
Test assessment is carried out, as shown on the right side of Fig. 3 under simulation software environment.Time delay and power consumption model are input to sheet online
In network emulation software tool (according to experience before, secondary development NS2 network law carrys out design and simulation environment), in conjunction with net
The related optimization of network coding, uses a large amount of real case, is successfully authenticated the novelty of the present invention.
Above-described embodiment is the present invention preferably embodiment, but embodiments of the present invention are not by above-described embodiment
Limit, the change made under other any spirit without departing from the present invention and principle, modify, substitute, combine, simplify,
All should be the substitute mode of equivalence, within being included in protection scope of the present invention.
Claims (7)
1. Novel compact based on network code, network-on-chip router efficient, quick, it is characterised in that this router bag
Having included the input of P road, output channel, each input channel is provided with again v tunnel, and the input channel on each road is designed with one
Routing logic Routing Logic and virtual channel allotter VC allocator, is each responsible for the route side of data transmission
To with distribution tunnel；Virtual channel allotter VC allocator is also associated with switch divider Switch allocator,
Described switch divider Switch allocator is overall parts, is responsible for P road input channel distribution cross bar switch
Crossbar, it is achieved multiple input channels ask the president of same output channel simultaneously, Crossbar are cross bar switches,
Realize P road input channel to transmit to the rapid data of P road output channel, P road input channel and cross bar switch Crossbar it
Between be additionally provided with network code module NCU, the microplate of tunnel exports through simple codes selection circuit, it is not necessary to coding or
The microplate not encoded herein is directly sent to cross bar switch Crossbar；The microplate encoded is carried out, then if in this router
Delivering to network code module NCU, qualified input is performed the encoding operation by NCU, and encoded microplate is through switch distribution
After the arbitration of device Switch allocator, it is sent to cross bar switch.
Novel compact based on network code the most according to claim 1, network-on-chip router efficient, quick, its
Being characterised by, router realizes multicast functionality by the logic circuit of amendment routing logic Routing Logic parts.
Novel compact based on network code the most according to claim 1, network-on-chip router efficient, quick, its
Being characterised by, described network code module NCU includes input buffer Input buffer and output buffer Output
Buffer, input allotter Input allocator are input point according to the idle condition of input buffer Input buffer
Join buffer queue, output moderator Output arbiter arbitration two-way coding output, it is ensured that cross bar switch Crossbar makes
With not conflicting.
Novel compact based on network code the most according to claim 3, network-on-chip router efficient, quick, its
Being characterised by, described network code module NCU scanning input buffer Input buffer, check whether there is is the most to be encoded
Data, and check these data paired data with or without alignment, if two paths of data is the most here, network code module NCU is just entered
Row data encoding, and revise packet header, form the packet after new coding, deliver to the output buffer Output of free time
In buffer.
Novel compact based on network code the most according to claim 1, network-on-chip router efficient, quick, its
It is characterised by, the pack arrangement supporting network code is defined as follows:
One packet is made up of several microplates Flit, including a packet header Head, several load datas Payload and
Individual bag tail Tail, Head and Tail comprise control information, and put in Payload is valid data.
Novel compact based on network code the most according to claim 5, network-on-chip router efficient, quick, its
Being characterised by, Head comprises the key control information supported network transmission and encode, and is made up of 9 parts, determining of each part
Justice and function are as shown in table 1:
Definition from above table is it can be seen that just can be true just with NC type, Dist to IS and Dist to ID
Which router is fixed two data wrap in performs the encoding operation, and which router to carry out multicast transmission at.
Novel compact based on network code the most according to claim 6, network-on-chip router efficient, quick, its
It is characterised by, packet Dist to IS=2 at the beginning, often subtracts 1 through a router Dist to IS, until is router
Becoming 0, represent and do network code in is, is is intermediate source node, and it is a router, is again an encoder, will
The raw data packets of two-way input encodes according to the order of microplate；This packet is sent in NCU, as Dist to IS
After 0, representing that network code completes, it is not necessary to change, now Dist to IS holding-1 is constant, and Dist to ID represents also again
To arrive middle destination router through a how many router, to need packet is carried out two-way multicast transmission.
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| CN107894963A (en) * | 2017-11-27 | 2018-04-10 | 上海兆芯集成电路有限公司 | Communication controler and communication means for system single chip |
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