CN105870191A - Gate alignment contact part and manufacturing method thereof - Google Patents

Gate alignment contact part and manufacturing method thereof Download PDF

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Publication number
CN105870191A
CN105870191A CN201610305963.1A CN201610305963A CN105870191A CN 105870191 A CN105870191 A CN 105870191A CN 201610305963 A CN201610305963 A CN 201610305963A CN 105870191 A CN105870191 A CN 105870191A
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China
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grid
gate
dielectric
contact
structures
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CN201610305963.1A
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CN105870191B (en
Inventor
O·戈隆茨卡
S·希瓦库马
C·H·华莱士
T·加尼
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Intel Corp
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Intel Corp
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Priority to CN201610305963.1A priority Critical patent/CN105870191B/en
Priority claimed from CN201180075764.1A external-priority patent/CN104011835B/en
Publication of CN105870191A publication Critical patent/CN105870191A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors

Abstract

The invention discloses a gate alignment contact part and a method for forming the gate alignment contact part. For example, the method for manufacturing a semiconductor structure comprises the step that a plurality of gate structures are formed on an active area of a substrate. Each gate structure comprises a gate dielectric layer, a gate electrode and a side wall spacer. A plurality of contact plugs are formed, and each contact plug is formed between the side wall spacers of every two adjacent grate structures in the plurality of the gate structures directly. A plurality of contact parts are formed, and each contact part is formed in between the side wall spacers of every two adjacent gate structures of the plurality of gate structures directly. The plurality of the contact parts and the gate structures are formed after the plurality of contact plugs are formed.

Description

Gate alignment contact site and manufacture method thereof
The application is divisional application, its original application be on June 20th, 2014 enter National Phase in China, International filing date is in December, the 2011 International Patent Application PCT/US2011/066989 of 22 days, should The China national application number of original application is 201180075764.1, and invention entitled " gate alignment contacts Portion and manufacture method thereof ".
Technical field
Embodiments of the invention belong to the field of semiconductor device and process, and particularly to gate alignment Contact site and the method forming gate alignment contact site.
Background technology
In the past few decades, the scaling of feature in integrated circuits is to support ever-increasing partly to lead The motive force of body industry.Zoom to the least feature achieve and take at the limited of semiconductor chip The density of the increase of the functional unit on area.Such as, the transistor size reduced allows to accelerate Memorizer or logical device be incorporated on chip, thus cause the system with the product of the capacity of increase Make.But, the pursuit to bigger capacity is not without problem.Optimize the performance of each equipment Necessity becomes to become more and more important.
In the manufacture of IC-components, when device size continues scaled, many grids are brilliant Body pipe (such as tri-gate transistor) becomes more commonly.In conventional process, tri-gate transistor leads to Often it is fabricated in body silicon substrate or silicon-on-insulator substrate.In some instances, body silicon substrate due to Its relatively low cost and because they realize more uncomplicated three gate fabrication process but preferably.? In other example, silicon-on-insulator substrate due to the raising of tri-gate transistor short-channel properties but Preferably.
But, scaling multi-gated transistor is not without consequence.When these of microelectronic circuit are basic When the size of member of formation reduces and when the absolute quantity of the basic member of formation manufactured in given area increases Added-time, the constraint for the photoetching process that patterns these member of formation become and can not keep out.Special , the minimum dimension (critical dimension) of the feature not being patterned in semiconductor laminated and such Have compromise between interval between feature.
Summary of the invention
Embodiments of the invention include gate alignment contact site and the method forming gate alignment contact site.
In an embodiment, semiconductor structure is included in the top table in the three-dimensional active district being arranged in substrate Multiple grid structures of the sidewall layout on face and along three-dimensional active district.Grid structure all includes grid Pole dielectric layer, gate electrode and sidewall spacers.Multiple contact sites are included, and each contact site is straight Connect between the sidewall spacers of two neighboring gate structures being arranged in multiple grid structure.Multiple contacts Connector is also included, and each contact plunger is directly arranged at two neighboring gates knots of multiple grid structure Between the sidewall spacers of structure.
In another embodiment, the method for manufacture semiconductor structure is included in and is formed at having of substrate Multiple grid structure is formed on source region.Each grid structure all includes gate dielectric layer, grid electricity Pole and sidewall spacers.Multiple contact plungers are formed, and each contact plunger is directly tied at multiple grids Formed between the sidewall spacers of two neighboring gate structures of structure.Multiple contact sites are formed, each Shape between the sidewall spacers of contact site directly two neighboring gate structures in multiple grid structures Become.Multiple contact sites and multiple grid structure are formed after forming the plurality of contact plunger.
In another embodiment, the method manufacturing semiconductor structure is included in substrate formation gate line Grid.Gate line grid includes multiple dummy gate electrode line.Shelter the illusory grid being stacked in gate line grid On polar curve and between formed.Patterning hard mask layer only gate line grid dummy gate electrode line On a part and between formed by sheltering lamination, expose the Part II of dummy gate electrode line.Electrolyte Layer on patterning hard mask layer and on the Part II of dummy gate electrode line and between formed.Electricity Dielectric layer flattened with on the Part II of dummy gate electrode line and between formed patterning dielectric Layer, and exposure pattern hard mask layer again.Patterning hard mask layer is from the illusory grid of gate line grid The Part I of polar curve is removed, and again exposes the Part I of dummy gate electrode line.Interlevel dielectric layer exists On patterned dielectric layer and on the Part I of dummy gate electrode line and between formed.Interlayer electricity Dielectric layer and patterned dielectric layer are flattened, to be respectively formed at the Part I of dummy gate electrode line Between rather than on the first permanent interlayer dielectric portion, and be formed at the second of dummy gate electrode line Between part rather than on sacrificial dielectric part.First or Part II of dummy gate electrode line or One or more being patterned in the dummy gate electrode line of both provides in the middle of multiple dummy gate electrode With the trench area in the middle of remaining district of the first permanent interlayer dielectric portion and sacrificial dielectric part. Trench area is filled with the second permanent interlayer dielectric portion.Multiple dummy gate electrode are with permanent grid structure generation Replace.Remaining district of sacrificial dielectric part is removed to provide contact openings.Contact site is then in contact Opening is formed.
Accompanying drawing explanation
Figure 1A-1K illustrates that have gate alignment contact site in manufacture according to an embodiment of the invention Semiconductor structure method in the viewgraph of cross-section of various operations, wherein:
Figure 1A is shown in substrate and forms gate line grid, and gate line grid includes multiple dummy gate electrode Line；
On the dummy gate electrode line of the gate line grid that Figure 1B is shown in Figure 1A and between formed shelter folded Layer；
Fig. 1 C illustrates and is formed patterning hard mask layer, patterning hard mask layer by the lamination of sheltering of Figure 1B On the only Part I of the dummy gate electrode line of gate line grid and between formed, expose illusory grid The Part II of polar curve；
Fig. 1 D is shown on the patterning hard mask layer of Fig. 1 C and at the Part II of dummy gate electrode line On and between formed dielectric layer；
Fig. 1 E illustrates that the dielectric layer of Fig. 1 D is flattened with on the Part II of dummy gate electrode line Patterned dielectric layer exposure pattern hard mask layer again is formed between and；
Fig. 1 F illustrates that the patterning hard mask layer of Fig. 1 E is by from the of the dummy gate electrode line of gate line grid A part is removed, and again exposes the Part I of dummy gate electrode line；
Fig. 1 G is shown in formation and the Part I at dummy gate electrode line on patterned dielectric layer On and between formed interlevel dielectric layer；
Fig. 1 H illustrates that interlevel dielectric layer and patterned dielectric layer are flattened, to be respectively formed at void If between the Part I of gate line rather than on formed the first permanent interlayer dielectric portion, and Between the Part II of dummy gate electrode line rather than on formed sacrificial dielectric part；
Fig. 1 I illustrates first or Part II of the dummy gate electrode line of Fig. 1 H or both one or many Individual dummy gate electrode line is patterned, to provide in multiple dummy gate electrode are worked as and at the first permanent interlayer electricity Trench area in the middle of remaining district of media fraction and sacrificial dielectric part, trench area is filled with second forever Interlayer dielectric part for a long time；
Fig. 1 J illustrates the multiple dummy gate electrode replacing Fig. 1 I with permanent grid structure；And
Fig. 1 K illustrates that remaining district of sacrificial dielectric part is removed to provide contact openings.
Fig. 2 illustrates the semiconductor structure according to an embodiment of the invention with gate alignment contact site Viewgraph of cross-section.
Fig. 3 illustrates the semiconductor structure according to an embodiment of the invention with gate alignment contact site Plane graph.
Fig. 4 illustrates that second half of gate alignment contact site of having according to another embodiment of the present invention is led The plane graph of body structure.
Fig. 5 illustrates the calculating equipment of an implementation according to the present invention.
Detailed description of the invention
Describe gate alignment contact site and the method forming gate alignment contact site.In following description In, a lot of specific details, the most integrated and material situation, in order to provide this are provided The thorough understanding of inventive embodiment.To those of skill in the art it will be apparent that the present invention Embodiment can be carried out in the case of not having these specific detail.In other example, known spy Levy (such as IC design layout) not to be described in detail, in order to the most unnecessarily make this Bright embodiment indigestion.Furthermore, it is to be understood that various embodiment illustrated in the accompanying drawings is illustration Property represents and is not drawn necessarily to scale.
One or more embodiments of the invention relates to gate alignment contact process.Such process can quilt Realize forming the contact patterns for semiconductor structure manufacture (such as IC manufacturing). In an embodiment, contact patterns is formed to be directed at existing gate pattern.On the contrary, conventional method Relate generally to the etching of photolithography contact combination of patterns selective contact and closely registrate with existing gate pattern Extra photoetching process.Such as, conventional process can include being inserted with contacting by patterned contact portion respectively Plug carrys out patterned polysilicon (poly) (grid) grid.
According to one or more embodiments described herein, the method that contact site is formed includes contact patterns Formation, contact patterns is fully aligned with existing gate pattern, simultaneously because the strictest registration is pre- Calculate and eliminate the use of lithography step.In one suchembodiment, the method realizes inherently The wet etching (such as, with the dry or plasma etching contrast realized as usual) of high selectivity Use to produce contact openings.In an embodiment, utilize by combining contact plunger lithography operations now Some gate patterns form contact patterns.In one suchembodiment, the method can eliminate To otherwise as in conventional method uses produce the needs of lithography operations of the key of contact patterns.? In embodiment, trench contact grid is not by independent pattern, but between polycrystalline (grid) line Formed.Such as, in one suchembodiment, trench contact grid patterns it at grid Afterwards but formed before grid cuts.
Figure 1A-1K illustrates that have gate alignment contact site in manufacture according to an embodiment of the invention Semiconductor structure method in the viewgraph of cross-section of various operations.Fig. 2 illustrates according to the present invention's The viewgraph of cross-section of the semiconductor structure with gate alignment contact site of embodiment.
With reference first to Fig. 2, semiconductor structure includes the multiple grid being arranged on the active area 102 of substrate Electrode structure 134.Such as, active area can include the diffusion region 104 as described in fig. 2.Grid structure 134 each include gate dielectric layer 136, gate electrode 138 and sidewall spacers 110.Electrolyte Lid 140 also can be included, as described in more detail below.Multiple contact sites 142 are included, each Contact site is directly arranged at the sidewall spacers of two neighboring gate structures of multiple grid structure 134 Between 110.Multiple contact plungers 128/132 are also included, and each contact plunger is directly arranged at multiple Between the sidewall spacers 110 of two neighboring gate structures of grid structure.Provide below and grid is tied Structure 134, active area 102, diffusion region 104, gate dielectric layer 136, gate electrode 138, sidewall The possible material of interval body 110, dielectric cap 140, contact site 142 and contact plunger 128/132 Select.Therefore, in an embodiment, the sidewall spacers 110 at grid structure 134 it is not arranged so as to And the intermediate layer of material between contact site 142 or residue.
With reference to Figure 1A, the method being used for manufacturing semiconductor structure (such as combining the structure that Fig. 2 describes) In initial point can start with the manufacture of gate line grid 106.Gate line grid 106 can include tool There is the dummy gate electrode 106 of interval body 110.Gate line grid 106 may be formed on active area 102 and It is formed on the diffusion region 104 of active area 102 in some places.Therefore, in an embodiment, source Pole and drain region (such as district 104) were manufactured in this stage.But, final gate pattern does not also have Formed, although grid pattern is formed.Gate line grid 106 can be by nitride cylinder or can quilt Certain other expendable material being referred to as grid dummy material is constituted, as described in more detail below.
In an embodiment, active area 102 is included but not limited to silicon, germanium, silicon-germanium by monocrystal material Or III-V compound semi-conducting material is constituted.Diffusion region 104 is active area in one embodiment The heavily doped region of 102.In one embodiment, active area 102 is made up of IV race material, and one Or some 104 is doped with boron, arsenic, phosphorus, indium or a combination thereof.In another embodiment, active District 102 is made up of III-V material, and one or more part 104 doped with carbon, silicon, germanium, oxygen, Sulfur, selenium or tellurium.In an embodiment, active area 102 is strain at least partially.Active area 102 Can be a part for three dimensional structure (such as patterned semiconductor main body) or complete in one embodiment Portion.Alternatively, in another embodiment, active area 102 is generally plane.
Active area 102 can be included as a part for wider substrate.Substrate can be by being suitable for quasiconductor The material that device manufactures is constituted.In an embodiment, substrate is body substrate.Such as, an embodiment In, substrate is to be included but not limited to silicon, germanium, silicon-germanium or III-V compound half by monocrystal material The body substrate that conductor material is constituted.Alternatively, substrate includes upper epitaxial layer and lower main part, Any of which all can be included but not limited to silicon, germanium, silicon-germanium or III-V by monocrystal material Compound semiconductor materials is constituted.By material, (it includes but not limited to silicon dioxide, silicon nitride Or silicon oxynitride) intermediate insulator layer that constitutes may be arranged between upper epitaxial layer and lower main part.
Gate line grid 106 can be formed by dummy gate electrode 108.Dummy gate electrode 108 in an embodiment by The material being suitable for removing in replacing gate operation is constituted, as discussed below.An embodiment In, dummy gate electrode 108 is made up of polysilicon, non-crystalline silicon, silicon dioxide, silicon nitride or a combination thereof. In another embodiment, protective coating (not shown) (such as silicon dioxide or silicon nitride layer) is illusory Formed on grid 108.In an embodiment, lower floor's dummy gate electrode dielectric layer (the most not shown) quilt Including.In an embodiment, dummy gate electrode 108 also includes sidewall spacers 110, and it can be by being suitable for The material making permanent grid structure electrically insulate with adjacent electrically conducting contact eventually is constituted.Such as, at one In embodiment, interval body 110 is aoxidized such as but not limited to silicon dioxide, nitrogen by dielectric substance Silicon, silicon nitride or mix carbon silicon nitride constitute.
With reference to Figure 1B, shelter lamination 112 on the dummy gate electrode 108 of gate line grid 106 and it Between formed.Shelter lamination 112 and include hard mask layer 114 and ARC (ARC) 116 and figure Case photoresist oxidant layer 118.According to embodiments of the invention, shelter the photoresist of lamination 112 Layer 118 is patterned to the discontinuities being ultimately convenient in the contact patterns subsequently formed (interruption) formation.Discontinuities is referred to alternatively as " contact plunger ".
In an embodiment, hard mask layer 114 is made up of the material of the sacrifice layer being adapted to act as subsequently. Such as, in one embodiment, as described in more detail below, hard mask layer 114 is finally by pattern Change to leave the remaining part subsequently further feature optionally removed.In specific such reality Executing in example, hard mask layer 114 is substantially made up of carbon, such as one layer of organic cross-linked polymeric thing. In one embodiment, hard mask layer 114 is by organic polymer materials (such as bottom antireflective coating (BARC)) constitute.In an embodiment, hard mask layer 114 deposits (CVD) by chemical gaseous phase Technique is formed.
In an embodiment, ARC layer 116 is suitable for the lithographic patterning phase in photoresist oxidant layer 118 Between inhibitory reflex interference.In one suchembodiment, ARC layer 116 is by spin-on-glass materials structure Become.Patterning photoresist oxidant layer 118 can be made up of the material being suitable for using in a lithographic process. In one embodiment, first patterning photoresist oxidant layer 118 by sheltering photo anti-corrosion agent material Equal thick-layer and then it is exposed to light source and is formed.Patterning photoresist oxidant layer 118 can be then By making the thickest photoresist oxidant layer development be formed.In an embodiment, the photic anti-of light source it is exposed to The part of erosion oxidant layer is removed when making photoresist oxidant layer develop.Therefore, patterning photoresist Layer 118 is made up of positive photo-induced corrosion resistant material.In certain embodiments, patterning photoresist oxidant layer 118 by positive photo-induced corrosion resistant material such as but not limited to 248nm resist, 193nm resist, 157nm resist, far ultraviolet rays (EUV) resist, electron beam embossed layer or there is adjacent nitrine naphthalene The phenolic resin as matrix resin of quinone sensitizer is constituted.In another embodiment, the photic of light source it is exposed to The part of resist layer is retained when making photoresist oxidant layer develop.Therefore, patterning photoresist Oxidant layer 118 is made up of negativity photo-induced corrosion resistant material.In certain embodiments, patterning photoresist Oxidant layer 118 is made up of negativity photo-induced corrosion resistant material, such as but not limited to by cis-polyisoprenoid or poly- Ethylene cinnamate is constituted.
With reference to Fig. 1 C, the pattern of photoresist oxidant layer 118 transfers to hard mask layer 114 by etch process With provide on some dummy gate electrode 108 of gate line grid 106 and between hard mask Layer 120.Photoresist oxidant layer 118 is removed.But, the patterned features of ARC layer 116 can be protected Stay, as depicted in Figure 1 C.According to embodiments of the invention, the pattern of photoresist oxidant layer 118 turns Move on to hard mask layer 114 to be exposed to diffusion region 104 dummy gate electrode 108 above, also such as Fig. 1 C institute Describe.In one suchembodiment, the pattern of photoresist oxidant layer 118 by use wait from Daughter etching process and transfer to hard mask layer 114.
With reference to Fig. 1 D, any remainder of ARC layer 116 is removed, and dielectric layer 122 is at figure On case hard mask layer 120 and on the dummy gate electrode 108 that is exposed of gate line grid 106 and Between formed.In an embodiment, dielectric layer 122 is by the material of the sacrifice layer being adapted to act as subsequently Constitute.Such as, in one embodiment, as described in more detail below, other quilt it is ultimately relative to Exposed features optionally removes dielectric layer 122.In certain embodiments, dielectric layer is by dioxy SiClx is constituted.
With reference to Fig. 1 E, dielectric layer 122 is flattened to form patterned dielectric layer 124 again Exposure pattern hard mask layer 120.In an embodiment, by chemical-mechanical planarization (CMP) work Skill operation carrys out planarized dielectric layer 122.In one suchembodiment, CMP operation relates to And use slurry at polishing pad upthrow photoelectric medium layer 122.In another embodiment, dry etching process quilt Use.
With reference to Fig. 1 F, utilize the selectivity to patterned dielectric layer 124 and utilize gate line lattice The selectivity of lower floor's dummy gate electrode 108 of grid 106 removes patterning hard mask layer 120.In embodiment In, patterning hard mask layer 120 is substantially or totally made up of carbon, and utilizes by silicon dioxide structure The selectivity of the patterned dielectric layer 124 become is removed.In an embodiment, patterning hard mask layer 120 are substantially or totally made up of carbon, and utilize cineration technics (ash process) to remove.One In individual embodiment, patterning hard mask layer 120 is made up of carbonaceous material and is utilizing oxygen (O2) gas or Nitrogen (N2) gas and hydrogen (H2) gas combination dry ashing operation in be removed.
With reference to Fig. 1 G, interlevel dielectric layer 126 is on patterned dielectric layer 124 and at grid On the dummy gate electrode 108 that is exposed of line grid 106 and between formed.According to embodiments of the invention, Interlevel dielectric layer 126 provides the Part I of permanent interlevel dielectric layer, as described herein below.? In one embodiment, interlevel dielectric layer 126 is made up of carbofrax material.In specific such reality Execute in example, use chemical gaseous phase deposition (CVD) technique to form carbofrax material.Implement at another In example, interlevel dielectric layer 126 is by such as but not limited to silicon dioxide, silicon nitride or silicon oxynitride Material is constituted.
Flattened to expose with reference to Fig. 1 H, interlevel dielectric layer 126 and patterned dielectric layer 124 The top section of all dummy gate electrode 108 of gate line grid 106.According to embodiments of the invention, Planarization provides the first permanent interlayer dielectric portion 128 and sacrificial dielectric part 130.In embodiment In, interlevel dielectric layer 126 and patterned dielectric layer 124 are operated by CMP and planarize, As described in above in conjunction with Fig. 1 E.
In this stage, the dummy gate electrode 108 of gate line grid 106 includes interval body 110 Cell structure can be perpendicular to and be patterned.As an example, not on diffusion zone, such as every The part of the gate line grid 106 on district can be removed.In another example, patterning produces Discrete dummy gate electrode structure.With reference to Fig. 1 I, in one suchembodiment, such as, pass through photoetching Method and etch process remove not dummy gate electrode 108 on diffusion region 104 part (with accordingly Interval body 110 part).
Referring again to Fig. 1 I, the removed part of gate line grid 106 can be then by the second permanent interlayer Dielectric portion 132 is filled.Second permanent interlayer dielectric portion 132 can be with being similar to first forever For a long time interlayer dielectric part 128 mode and by identical with the first permanent interlayer dielectric portion 128 or Similar material and (such as) is formed by deposition and planarization.Should be understood that regarding in Fig. 1 I Figure can have the horizontal stroke of (such as, into or out paper) on the position different from the cross section shown in Fig. 1 H Cross section.Therefore, now, permanent interlevel dielectric layer can be by the firstth district (not shown in Fig. 1 I) The permanent interlayer dielectric portion 128 of the first of middle formation and the second permanent interlayer formed in the second region The combination of dielectric portion 132 limits.In one suchembodiment, the first permanent interlayer electricity is situated between Matter part 128 and the second permanent interlayer dielectric portion 132 are all made up of carborundum.
In this stage, remaining dummy gate electrode 108 being exposed can be in replacing gate process scheme Replaced.In such scheme, dummy gate electrode material (such as polysilicon or silicon nitride cylindrical material) Can be removed and replace by permanent gate electrode material.In one suchembodiment, permanent grid Dielectric layer is formed the most in this process, contrary with complete from process in early time.
In an embodiment, dummy gate electrode 108 is removed by dry ecthing or wet etching process.A reality Executing in example, dummy gate electrode 108 is constituted by polysilicon or non-crystalline silicon and is used and includes SF6Dry ecthing work Skill is removed.In another embodiment, dummy gate electrode 108 is made up of polysilicon or non-crystalline silicon and uses Including aqueous NH4The wet etching process of OH or Tetramethylammonium hydroxide is removed.An embodiment In, dummy gate electrode 108 is made up of silicon nitride and uses the wet etching including water-bearing phosphate to remove.
With reference to Fig. 1 J, permanent grid structure 134 is formed to include permanent gate dielectric layer 136 He Permanent grid electrode layer or lamination 138.Additionally, in an embodiment, the top of permanent grid structure 134 Part is such as removed by etch process and replaces with dielectric covers 140.In an embodiment, electricity Dielectric cap layer 140 is by interlayer dielectric portion permanent with first be made up of carborundum 128 and second forever Interlayer dielectric part 132 is the same from material composition for a long time.In one suchembodiment, all The permanent interlayer dielectric portion of dielectric covers 140, first 128 and the second permanent interlayer dielectric portion 132 are all made up of carborundum.
In an embodiment, permanent gate dielectric layer 136 is made up of hafnium.Such as, at one In embodiment, permanent gate dielectric layer 136 is made up of material, and described material is such as but not limited to oxygen Change hafnium, nitrogen hafnium oxide, hafnium silicate, lanthana, zirconium oxide, Zirconium orthosilicate., tantalum oxide, barium strontium, Barium metatitanate., strontium titanates, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc or a combination thereof.This Outward, a part for permanent gate dielectric layer 136 can include several layers of the top by diffusion region 104 shape The one layer of native oxide become.In an embodiment, permanent gate dielectric layer 136 is by height k portion, top The lower part divided and be made up of the oxide of semi-conducting material is constituted.In one embodiment, permanent grid Pole dielectric layer 136 is divided the bottom with silicon dioxide or silicon oxynitride to divide to constitute by the top of hafnium oxide.
In an embodiment, permanent grid electrode layer or lamination 138 are made up of metal gates.A reality Execute in example, permanent grid electrode layer or lamination 138 by metal level such as but not limited to nitride metal Thing, metal carbides, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, Palladium, platinum, cobalt, nickel or conducting metal oxide are constituted.In certain embodiments, permanent grid Pole electrode layer or lamination 138 are by setting the NOT function function sets filling formed on layer in metal work function Material is constituted.In an embodiment, permanent grid electrode layer or lamination 138 also include to be situated between by insulated electro The sidewall spacers 110 that material is constituted, as mentioned above.
With reference to Fig. 1 K, relative to the permanent interlayer dielectric portion 128 of dielectric covers 140, first, Being exposed of second permanent interlayer dielectric portion 132, interval body 110 and diffusion region 104 is partly selected Remove to selecting property sacrificial dielectric part 130.In an embodiment, dry ecthing or wet etching process (example are used Such as aqueous hydrofluoric acid (HF) wet etching process) remove sacrificial dielectric part 130.According to this Bright embodiment, sacrificial dielectric part 130 is served as sacrifice occupying device, is formed for contact subsequently.
Refer again to Fig. 2, be once provided with sacrificial dielectric part 130, be the formation of contact site 142. Therefore, contact site 142 is formed between permanent grid structure 134.In an embodiment, contact site 142 Deposition and planarization (such as passing through CMP) by conductive material are formed.Contact site 142 can be by Conductive material is constituted.In an embodiment, contact site 142 is made up of metallics.Metallics is permissible It is simple metal (such as nickel or cobalt), can be maybe alloy, such as metal-metal alloy or metal-partly lead Body alloy (such as silicide material).
Fig. 3 illustrates the plane graph of some feature showing semiconductor structure according to an embodiment of the invention. With reference to Fig. 3, semiconductor structure include being arranged in substrate active area 102 (such as diffusion region 104) it On multiple grid structures 134.Multiple contact sites 142 are included, and each contact site is directly arranged at many Between two neighboring gate structures in individual grid structure 134, such as directly at multiple grid structures 134 In two neighboring gate structures sidewall spacers between.
Therefore, in an embodiment, the method manufacturing semiconductor structure is included in substrate formation grid Line grid.Gate line grid includes multiple dummy gate electrode line.Shelter and be stacked in the illusory of gate line grid On gate line and between formed.Patterning hard mask layer gate line grid dummy gate electrode line only Only on Part I and between formed by sheltering lamination, expose the Part II of dummy gate electrode line.Electricity Dielectric layer on patterning hard mask layer and on the Part II of dummy gate electrode line and between shape Become.Dielectric layer flattened with on the Part II of dummy gate electrode line and between formed patterning Dielectric layer, and exposure pattern hard mask layer again.Patterning hard mask layer is from gate line grid The Part I of dummy gate electrode line is removed, and again exposes the Part I of dummy gate electrode line.Interlayer electricity is situated between Matter layer on patterning hard mask layer and on the Part I of dummy gate electrode line and between shape Become.Interlevel dielectric layer and patterned dielectric layer are flattened, to be respectively formed at dummy gate electrode line Part I between rather than on the first permanent interlayer dielectric portion and be formed at illusory grid Between the Part II of polar curve rather than on sacrificial dielectric part.Dummy gate electrode line first or One or more being patterned in Part II or the dummy gate electrode line of both provides in multiple void If during grid is worked as and in the middle of remaining district of the first permanent interlayer dielectric portion and sacrificial dielectric part Trench area.Trench area is filled with the second permanent interlayer dielectric portion.Multiple dummy gate electrode are with permanent Grid structure replaces.Remaining district of sacrificial dielectric part is removed to provide contact openings.Contact site Formed the most in the contact openings.
In one suchembodiment, form patterning hard mask layer to include forming organic cross-linked polymeric Nitride layer, forms dielectric layer and includes forming layer of silicon dioxide, forms interlevel dielectric layer and includes being formed One layer of carborundum, and include being formed and plane with the second permanent interlayer dielectric portion filling trench area Change second layer carborundum.In specific such embodiment, replace multiple void with permanent grid structure If grid includes forming permanent gate dielectric layer, permanent grid layer and silicon carbide capping layer.Another this In the embodiment of sample, substrate formed gate line grid be included in three-dimensional active district top surface it Upper and along three-dimensional active district sidewall forms dummy gate electrode line.
In an embodiment, one or more methods described herein effectively imagine combine illusory and replace Illusory and the replacement gate process of contact site process.In one suchembodiment, contact site is replaced Process is performed to allow at least one of high temperature of permanent gate stack after replacing gate process Annealing.Such as, in specific such embodiment, at least one of of permanent grid structure moves back Fire is such as performed after gate dielectric layer is formed at than about 600 degrees Celsius of higher temperature. Annealing was performed before the formation in permanent contact portion.
In an embodiment, illusory contact site was formed before the formation of contact site connector.It is to say, Illusory contact site can be formed before the dummy gate electrode structure in cutting grid.Such method can Motility in final layout is provided.In one suchembodiment, contact structures are formed With two or more diffusion region contacts.Such as, Fig. 4 illustrates according to another embodiment of the present invention There is the plane graph of second half conductor structure of gate alignment contact site.
With reference to Fig. 4, semiconductor structure includes the active area 102 (such as diffusion region 104) being arranged in substrate On multiple grid structures 134.Multiple contact sites 142 are included, and each contact site is directly arranged at Between two neighboring gate structures of multiple grid structures 134, such as directly at multiple grid structures 134 Two neighboring gate structures sidewall spacers between.One of contact site 144 is formed and two Diffusion region contacts.Dummy gate electrode grid line by existing before promotes to connect in certain embodiments The formation of contact portion 144, dummy gate electrode grid line is not cut, until contact site 144 is the most illusory Till contact occupying device is formed.
Should be understood that it is not that all aspects of said process are required for being carried out the enforcement in the present invention In the spirit and scope of example.Such as, in one embodiment, never need to form dummy gate electrode. Gate stack described above can be actually the permanent gate stack such as originally formed.At one so Embodiment in, as long as connector is formed and is followed by grid cutting operation, benefit and advantage and just will realize.
Process described herein can be used for manufacturing one or more semiconductor device.Semiconductor device is permissible It is transistor or similar device.Such as, in an embodiment, semiconductor device is for logic or storage Metal-oxide semiconductor (MOS) (MOS) transistor of device or bipolar transistor.Additionally, in embodiment In, semiconductor device has three-dimensional architecture, such as three gated devices, the dual-gated device of independent access Or FIN-FET.
Fig. 5 illustrates the calculating equipment 500 of an implementation according to the present invention.Calculating equipment 500 Accommodate plate 502.Plate 502 can include multiple parts, include but not limited to processor 504 and at least one Communication chip 506.Processor 504 is physically and electrically coupled to plate 502.In some implementations In, at least one communication chip 506 is the most physically and electrically coupled to plate 502.In other realization In mode, communication chip 506 is the part of processor 504.
Applying according to it, calculating equipment 500 can include physically and electrically coupling Other parts to plate 502.These other parts may include but be not limited to volatile memory (such as DRAM), at nonvolatile memory (such as ROM), flash memory, graphic process unit, digital signal Reason device, cipher processor, chipset, antenna, display, touch-screen display, touch screen control Device, battery, audio coder-decoder, video coder-decoder, power amplifier, global positioning system System (GPS) equipment, compass, accelerometer, gyroscope, speaker, photographing unit and Large Copacity are deposited Storage equipment (such as hard disk drive, CD (CD), digital versatile disc (DVD) etc.).
Communication chip 506 realizes travelling to and fro between the radio communication of the transmission of calculating equipment 500 for data. Term " wireless " and derivative thereof can be used for describing and can pass through to use being modulated via non-solid medium The circuit of data, equipment, system, method, technology, communication channel etc. are transmitted in electromagnetic radiation.Should Term does not implies that the equipment being associated does not comprises any electric wire, although they can in certain embodiments Not comprise electric wire.Communication chip 506 can realize any one in multiple wireless standard or agreement, bag Include but be not limited to Wi-Fi (IEEE 802.11 race), WiMAX (IEEE 802.16 race), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, bluetooth, its derivatives and be designated as 3G, 4G, Other wireless protocols any in 5G and Geng Gao generation.Calculating equipment 500 can include multiple communication chip 506. Such as, the first communication chip 506 can be exclusively used in relatively short distance radio communication (such as Wi-Fi and bluetooth), And the second communication chip 506 can be exclusively used in relatively long distance radio communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO etc..
The processor 504 of calculating equipment 500 includes the integrated circuit lead being encapsulated in processor 504. In some implementations of the present invention, the integrated circuit lead of processor includes one or more device, The MOS-FET transistor such as built according to the implementation of the present invention.Term " processor " can Can so that described electronic data is converted into the electronic data that finger processes from depositor and/or memorizer Any equipment of other electronic data being stored in depositor and/or memorizer or the part of equipment.
Communication chip 506 also includes the integrated circuit lead being encapsulated in communication chip 506.According to this Another implementation of invention, the integrated circuit lead of communication chip includes one or more device, example The MOS-FET transistor built such as the implementation according to the present invention.
In other implementation, another parts being contained in calculating equipment 500 can comprise integrated Circuit die, it includes one or more device, such as, builds according to the implementation of the present invention MOS-FET transistor.
In various implementations, calculating equipment 500 can be laptop computer, net book, pen Remember this computer, super computer, smart phone, tablet PC, personal digital assistant (PDA), Super mobile PC, mobile phone, desktop PC, server, printer, scanner, monitor, Set Top Box, amusement control unit, digital camera, portable music player or digital video record Device.In other implementation, calculating equipment 500 can be other electronics any processing data Equipment.
Therefore, gate alignment contact site and the method forming gate alignment contact site are disclosed.Implementing In example, manufacture semiconductor structure method be included in be formed on the active area of substrate formed many Individual grid structure.Grid structure each includes gate dielectric layer, gate electrode and sidewall spacers. Forming multiple contact plunger, be formed directly in multiple grid structure two of each contact plunger are adjacent Between the sidewall spacers of grid structure.Forming multiple contact site, each contact site is formed directly into many Between the sidewall spacers of two neighboring gate structures in individual grid structure.Multiple contact sites and multiple Grid structure is formed after forming multiple contact plungers.In one embodiment, multiple grid structures By replacing multiple dummy gate electrode to be formed before forming multiple contact sites.In one embodiment, Formed multiple contact site include being formed with two or more diffusion region contacts of active area contact knot Structure.

Claims (16)

1. a semiconductor structure, including:
Multiple grid structures, it is on the top surface in three-dimensional active district being arranged in substrate and edge The sidewall described three-dimensional active district is arranged, each of which in the plurality of grid structure includes grid Dielectric layer, gate electrode, sidewall spacers and between described sidewall spacers and with described side The dielectric covers that wall interval body is laterally adjacent, wherein said sidewall spacers includes the first electrolyte material Material, wherein said dielectric covers includes second separate and distinct from described first dielectric substance Dielectric substance, and described first dielectric substance of wherein said sidewall spacers with described electricity be situated between Described second dielectric substance of matter cap rock intersects in generally vertical interface；
Multiple contact sites, each of which in the plurality of contact site is arranged in the plurality of grid structure In two neighboring gate structures described sidewall spacers between, and in the plurality of contact site The top surface of each is the most common with the top surface of the described dielectric covers of the plurality of grid structure Face；And
Multiple contact plungers, each of which in the plurality of contact plunger is arranged in the plurality of grid Between the described sidewall spacers of two neighboring gate structures in structure, and the plurality of contact is inserted The described top table of the described dielectric covers of the top surface of each in plug and the plurality of grid structure Substantially coplanar and with the plurality of contact site the described top surface in face is substantially coplanar.
2. semiconductor structure as claimed in claim 1, described the first of wherein said sidewall spacers Dielectric substance is different materials compared with described second dielectric substance of described dielectric covers.
3. semiconductor structure as claimed in claim 1, each in wherein said multiple contact sites The described sidewall spacers of two neighboring gate structures being all directly arranged in the plurality of grid structure Between.
4. semiconductor structure as claimed in claim 1, each in wherein said multiple contact plungers The described sidewall spacers of individual two neighboring gate structures being all directly arranged in the plurality of grid structure Between body.
5. semiconductor structure as claimed in claim 1, described the first of wherein said sidewall spacers Dielectric substance is different materials compared with described second dielectric substance of described dielectric covers, Each of which in wherein said multiple contact site is directly arranged at two in the plurality of grid structure Between the described sidewall spacers of neighboring gate structures, and every in wherein said multiple contact plunger Between the described sidewall of one two neighboring gate structures being all directly arranged in the plurality of grid structure Between spacer.
6. semiconductor structure as claimed in claim 1, wherein said multiple contact sites include conduction material Material, and the plurality of contact plunger includes carborundum.
7. semiconductor structure as claimed in claim 6, each in wherein said multiple grid structures Individual all include high-K gate electrolyte, metal gates and the carborundum lid as described dielectric covers.
8. semiconductor structure as claimed in claim 1, one of wherein said multiple contact sites are with described Two or more diffusion region contacts in three-dimensional active district.
9. a semiconductor structure, including:
Having by the substrate of the separate multiple active areas in multiple isolation areas, the plurality of active area is along institute The first direction stating substrate has length；
Along multiple gate lines of the second direction of described substrate, described second direction is orthogonal to described One direction, the first grid polar curve in wherein said multiple gate lines is discontinuously with in the plurality of isolation area In an isolation area on the first otch is provided；And
Along multiple trench contact portions of described second direction, the plurality of trench contact portion is with described many Alternately, a trench contact portion in wherein said multiple trench contact portions is with the plurality of for individual gate line Described first grid polar curve direct neighbor in gate line, and in wherein said multiple trench contact portion One trench contact portion is continuous print in the position laterally adjacent with described first otch.
10. semiconductor structure as claimed in claim 9, second in wherein said multiple gate lines Gate line on the side relative with the described first grid polar curve in the plurality of gate line with the plurality of One trench contact portion direct neighbor in trench contact portion, and wherein said multiple gate line In described second gate line discontinuously with provide laterally adjacent with described position and described first otch Second otch.
11. semiconductor structures as claimed in claim 9, in wherein said multiple trench contact portions One trench contact portion is by dielectric spacers and the described first grid in the plurality of gate line Polar curve is separately.
12. semiconductor structures as claimed in claim 9, wherein said multiple active areas are multiple half Conductor fin.
13. semiconductor structures as claimed in claim 9, each in wherein said multiple gate lines Individual all include a pair dielectric sidewall spacers.
14. semiconductor structures as claimed in claim 13, each in wherein said multiple gate lines Individual all include gate dielectric layer, gate electrode and dielectric covers.
15. semiconductor structures as claimed in claim 14, wherein said a pair dielectric sidewall spacers Body includes the material being different from the material of described dielectric covers.
16. semiconductor structures as claimed in claim 14, wherein said gate electrode includes high K Gate-dielectric, metal gates and the carborundum lid as described dielectric covers.
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