CN105870004A - Method for eliminating shallow trench isolation induced dark current of CMOS image sensor - Google Patents
Method for eliminating shallow trench isolation induced dark current of CMOS image sensor Download PDFInfo
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- CN105870004A CN105870004A CN201610212543.9A CN201610212543A CN105870004A CN 105870004 A CN105870004 A CN 105870004A CN 201610212543 A CN201610212543 A CN 201610212543A CN 105870004 A CN105870004 A CN 105870004A
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- 238000002955 isolation Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- 230000006698 induction Effects 0.000 claims description 15
- 230000008030 elimination Effects 0.000 claims description 10
- 238000003379 elimination reaction Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 210000002381 plasma Anatomy 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- BKLWQDSDJBFRDF-ZPUQHVIOSA-N (2e,4e)-5-(4-nitrophenyl)penta-2,4-dienal Chemical compound [O-][N+](=O)C1=CC=C(\C=C\C=C\C=O)C=C1 BKLWQDSDJBFRDF-ZPUQHVIOSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000004899 motility Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention provides a method for eliminating shallow trench isolation induced dark current of a CMOS image sensor. The method comprises the step of step 1: defining positions of STI trenches of a logic region and a pixel region through mask plates; step 2: etching the STI trenches according to the defined positions of the STI trenches; step 3: carrying out disposition and filling on the STI trenches; and step 4: defining a part of pixel regions which need to be subjected to isolation region injection by adopting the mask plates, and carrying out ion implantation for the part of the defined pixel regions which need to be subjected to isolation region injection.
Description
Technical field
The present invention relates to field of semiconductor manufacture, eliminate CMOS figure it is more particularly related to a kind of
Method as sensor shallow trench isolation induction dark current.
Background technology
Cmos image sensor (CIS) is compatible due to its manufacturing process and existing integrated circuit fabrication process,
Compare than original charge coupled device ccd in its performance simultaneously and have many good qualities.Cmos image sensor
Drive circuit and pixel can be integrated, simplify hardware designs, also reduce the merit of system simultaneously
Consumption.CIS is owing to just can take out the signal of telecommunication while gathering optical signal, moreover it is possible to real time processed images information,
Speed is faster than ccd image sensor.Cmos image sensor also has low price, and bandwidth is relatively big, anti-
Fuzzy, the motility of access and the advantage of bigger activity coefficient.
Traditional active pixel is to use photodiode as image sensing device.Common active pixel list
Unit is to be made up of three transistors and a P+/N+/P-photodiode, and this structure is suitable for standard
CMOS manufacturing process.Fig. 1 has provided the schematic diagram of the 4T pixel of back side illumination image sensor rear end,
During illumination, photodiode produces electric charge at N-, and at this moment transfer pipe is closed mode.Then transfer pipe is beaten
Opening, will be stored in the electric charge in photodiode and be transferred to floating node, after transmission, transfer pipe is closed, and
Wait the entrance of illumination next time.Charge signal on floating node is used subsequently to adjust and amplifies transistor.
After reading, floating point is reset to a reference voltage by the reset transistor with reset gate.This design exists
On large-sized pixel cell, the size due to photodiode is relatively big, and (photodiode stores full-well capacity
The ability of electric charge) get a promotion, such that it is able to store more electronics, such that it is able to improve pixel cell
Dynamic range (the brightest ratio with the darkest situation), reduces the noise impact on pixel, and signal to noise ratio can carry
High.For the cmos image sensor pixel cell of existing use P type substrate, reset transistor therein,
Amplifier tube, selection pipe and transfer Guan Douwei N-type MOS.
During original CIS chip manufacturing process, STI (shallow trench isolation) groove (ditch of logic region
Groove depth) about 1000A deeper than the gash depth of pixel region.The position of different gash depths, needs mask
Plate defines, simultaneously need to two step etching completes.Two step etching, can cause surface as barrier layer
SIN (silicon nitride) produces difference in height, thus causes follow-up STI chemical mechanical milling tech easily to have oxide
Residual or the problem crossing grinding.In order to save mask plate, and eliminate the SIN height that two step etching causes
Difference, industry tend to use unified sti trench groove depth method carry out volume production CIS chip.In view of LG region
Sti trench groove depth is required higher, it is impossible to change its degree of depth, so pixel region sti trench groove depth needs
Deepen to consistent with logic area.Sti trench groove depth is deepened, and can cause the long-pending increase of flute surfaces.Sti trench groove
Surface can be because etch process, the technique such as follow-up high-density plasma chemical vapor deposition causes surface to be damaged
Wound, i.e. the SI-key of silicon face is interrupted by technical processs such as plasmas, and unsettled silicon key is easy to capture electronics,
But the also electronics of easily release capture.Thus induce dark current.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that one disappears
Method except cmos image sensor shallow trench isolation induction dark current, it is possible to changed by ion implanting conditions
The method become, avoids the problem that dark current increases.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that a kind of elimination cmos image sensor
The method of shallow trench isolation induction dark current, including:
First step: use the position of mask plate definition logic area and the sti trench groove of pixel region；
Second step: according to the position of the sti trench groove of definition, etch sti trench groove；
Third step: sti trench groove is carried out deposition and fills；
4th step: using mask plate to define needs the partial pixel district carrying out isolation area injection, and for
Define needs to carry out the partial pixel district of isolation area injection, performs ion implanting.
Preferably, in third step, use high-density plasma chemical gas phase process that sti trench groove is entered
Row deposition is filled.
Preferably, the active device of pixel region is made up of N-type device or photodiode.
Preferably, the 4th step uses p-type ion implanting.
Preferably, the ion implanting of the 4th step comprises repeatedly to be injected, and injects every time and uses different Implantation Energy.
Preferably, inject employing non-angular p-type ion implanting every time.
Preferably, the energy range every time injected is 10-20kev, 30～50kev or 60～80kev.
Preferably, the dosage every time injected is between 1E12～5E13.
In the present invention, the sti trench groove depth of CIS imageing sensor need not two kinds of degree of depth, thus avoids
The problem of SIN difference in height in technique, and isolation area is injected and is not interfered with other transistor.Meanwhile, isolation
District injects and is carried out in several steps non-angular injection, forms the gradual joint similar to photodiode, can be followed by effect
Reduction dark current.Meanwhile, after STI deposition is filled, carry out ion implanting again, high energy can be prevented effectively from
The amount ion implanting bombardment damage to STI trench, it is to avoid because the dark current that bombardment damage causes.This
The bright dark current that can effectively suppress to cause owing to deepening pixel region sti trench groove depth increases problem, thus reaches
Reduce the dark current of imageing sensor.And, present invention saves the mask plate of sti trench groove and corresponding work
Skill program.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete
Understand and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows the structural representation of 4T active CMOS image sensor.
Fig. 2 schematically shows elimination cmos image sensor shallow ridges according to the preferred embodiment of the invention
The flow chart of the method for groove isolation induction dark current.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent structure
Accompanying drawing may be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicate identical or
The label that person is similar to.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings to this
Bright content is described in detail.
Before illustrating the principle of the present invention, first briefly describe original twice active area circulation technology step
Suddenly.Specifically, original twice active area circulation technology step is as follows:
First, mask plate is used to define the position of thicker sti trench groove (the referred to here as first sti trench groove)；
Subsequently, the first initial degree of depth of the first sti trench groove is etched；
Hereafter, mask plate is used to define the position of all sti trench grooves；
Hereafter, it is etched for all sti trench grooves, except the first sti trench groove in the most all sti trench grooves
Outside the second sti trench groove there is second degree of depth, and the degree of depth of the first sti trench groove is first degree of depth and second
Degree of depth sum.Now, the first sti trench groove is etched twice, the thickness pixel to be compared of the silicon nitride on its surface
Thin (the thinnest about the 100A) in district；
Hereafter, use mask plate definition pixel region, then make a call to one p-type ion, in order to play isolating n-type
The effect of device, the deficiency of the degree of depth of the second sti trench groove in compensation pixel district；
All sti trench grooves carry out deposition fill.
The present invention, from the dark current reducing imageing sensor, utilizes the mode of ion implanting, it is to avoid STI
The silicon key capture electronics of flute surfaces fracture is directly released in photodiode region, reduces dark current, improves figure
The quality of picture.
Fig. 2 schematically shows elimination cmos image sensor shallow ridges according to the preferred embodiment of the invention
The flow chart of the method for groove isolation induction dark current.
As in figure 2 it is shown, eliminate the isolation of cmos image sensor shallow trench according to the preferred embodiment of the invention
The method of induction dark current includes:
First step S1: use the position of mask plate definition logic area and the sti trench groove of pixel region；
Second step S2: according to the position of the sti trench groove of definition, etch sti trench groove；
Third step S3: sti trench groove is carried out deposition and fills；Such as, in third step S3, use height
Density plasma chemical gas phase process carries out deposition and fills sti trench groove.
4th step S4: use mask plate definition to need the partial pixel district carrying out isolation area injection, and pin
Definition needs to carry out the partial pixel district of isolation area injection, performs ion implanting.
Do not affect the effect of other functions of pixel region while dark current to reach to eliminate, be described below every
The injection zone injected from district and the detail of injection mode.
Owing to the active device of pixel region is all N-type device or photodiode, therefore make in the fourth step s 4
P-type ion implanting is used to reach isolation effect.
Preferably, the ion implanting of the 4th step S4 comprises repeatedly to be injected, and injects every time and uses difference to inject energy
Amount, and inject every time and use non-angular p-type ion implanting.
Owing to sti trench groove depth strengthens, in order to ensure that ion implanting can be fully achieved desired locations, remove
Power supports angle such as；The electronics that the generation of dark current is mainly derived from photodiode is by flute surfaces
Charge-trapping, and also there is different distributions the N-type injection region at photodiode position, and (main distribution includes
Tri-regions of NPPD, DNPPD1, DNPPD2).In order to eliminate possible dark current source targetedly,
Ion implanting in the method for the preferred embodiment of the present invention divides 3 injections, and the energy range every time injected is permissible
For 10-20kev, 30～50kev or 60～80kev, the dosage every time injected is between 1E12～5E13.
Owing to the isolation area Implantation Energy of the present invention is big, implantation step is many, so light to be avoided is injected in isolation area
The region of electric diode and the region of other necessity, can define its concrete district by isolation area photoetching
Territory.
Subsequent technique is constant, according to existing technological process flow.
In the present invention, the sti trench groove depth of CIS imageing sensor need not two kinds of degree of depth, thus avoids
The problem of SIN difference in height in technique, and isolation area is injected and is not interfered with other transistor.Meanwhile, isolation
District injects and is carried out in several steps non-angular injection, forms the gradual joint similar to photodiode, can be followed by effect
Reduction dark current.The present invention can effectively suppress owing to deepening the dark current that pixel region sti trench groove depth causes
Increase problem, thus reduce the dark current of imageing sensor.And, present invention saves sti trench groove
Mask plate and corresponding process.
Furthermore, it is necessary to explanation, unless stated otherwise or point out, otherwise the term in description " first ",
" second ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc., and not
It is intended to indicate that the logical relation between each assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is also
It is not used to limit the present invention.For any those of ordinary skill in the art, without departing from skill of the present invention
In the case of art aspects, technical solution of the present invention is made many by the technology contents that all may utilize the disclosure above
Possible variation and modification, or it is revised as the Equivalent embodiments of equivalent variations.Therefore, every without departing from this
The content of bright technical scheme, according to the present invention technical spirit to any simple modification made for any of the above embodiments,
Equivalent variations and modification, all still fall within the range of technical solution of the present invention protection.
Claims (8)
1. the method eliminating cmos image sensor shallow trench isolation induction dark current, it is characterised in that
Including:
First step: use the position of mask plate definition logic area and the sti trench groove of pixel region；
Second step: according to the position of the sti trench groove of definition, etch sti trench groove；
Third step: sti trench groove is carried out deposition and fills；
4th step: using mask plate to define needs the partial pixel district carrying out isolation area injection, and for
Define needs to carry out the partial pixel district of isolation area injection, performs ion implanting.
Elimination cmos image sensor shallow trench the most according to claim 1 isolation induction dark current
Method, it is characterised in that in third step, uses high-density plasma chemical gas phase process to STI
Groove carries out deposition and fills.
The dark electricity of elimination cmos image sensor shallow trench the most according to claim 1 and 2 isolation induction
The method of stream, it is characterised in that the active device of pixel region is made up of N-type device or photodiode.
Elimination cmos image sensor shallow trench the most according to claim 3 isolation induction dark current
Method, it is characterised in that use p-type ion implanting in the 4th step.
The dark electricity of elimination cmos image sensor shallow trench the most according to claim 1 and 2 isolation induction
The method of stream, it is characterised in that the ion implanting of the 4th step comprises repeatedly to be injected, injects every time and uses not
Same Implantation Energy.
Elimination cmos image sensor shallow trench the most according to claim 5 isolation induction dark current
Method, it is characterised in that inject every time and use non-angular p-type ion implanting.
Elimination cmos image sensor shallow trench the most according to claim 5 isolation induction dark current
Method, it is characterised in that the energy range every time injected is 10-20kev, 30～50kev or 60～80kev.
Elimination cmos image sensor shallow trench the most according to claim 5 isolation induction dark current
Method, it is characterised in that the dosage every time injected is between 1E12～5E13.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610212543.9A CN105870004A (en) | 2016-04-07 | 2016-04-07 | Method for eliminating shallow trench isolation induced dark current of CMOS image sensor |
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| CN201610212543.9A CN105870004A (en) | 2016-04-07 | 2016-04-07 | Method for eliminating shallow trench isolation induced dark current of CMOS image sensor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783899A (en) * | 2016-11-30 | 2017-05-31 | 上海华力微电子有限公司 | A kind of method for reducing cmos image sensor dark current |
| CN108550550A (en) * | 2018-05-04 | 2018-09-18 | 德淮半导体有限公司 | Fleet plough groove isolation structure and forming method thereof, imaging sensor |
| CN111403426A (en) * | 2018-12-28 | 2020-07-10 | 天津大学青岛海洋技术研究院 | CMOS image sensor pixel structure for reducing diffusion dark current |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040033667A1 (en) * | 2002-07-19 | 2004-02-19 | Won-Ho Lee | Method for isolating hybrid device in image sensor |
| CN101202246A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Forming method of pixel unit of CMOS image sensor |
| CN105185747A (en) * | 2015-09-25 | 2015-12-23 | 上海华力微电子有限公司 | Integrated technology of reducing CMOS image sensor white pixels |
-
2016
- 2016-04-07 CN CN201610212543.9A patent/CN105870004A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040033667A1 (en) * | 2002-07-19 | 2004-02-19 | Won-Ho Lee | Method for isolating hybrid device in image sensor |
| CN101202246A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Forming method of pixel unit of CMOS image sensor |
| CN105185747A (en) * | 2015-09-25 | 2015-12-23 | 上海华力微电子有限公司 | Integrated technology of reducing CMOS image sensor white pixels |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783899A (en) * | 2016-11-30 | 2017-05-31 | 上海华力微电子有限公司 | A kind of method for reducing cmos image sensor dark current |
| CN108550550A (en) * | 2018-05-04 | 2018-09-18 | 德淮半导体有限公司 | Fleet plough groove isolation structure and forming method thereof, imaging sensor |
| CN111403426A (en) * | 2018-12-28 | 2020-07-10 | 天津大学青岛海洋技术研究院 | CMOS image sensor pixel structure for reducing diffusion dark current |
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Application publication date: 20160817 |