CN105845682B - Memory element and its manufacturing method - Google Patents
Memory element and its manufacturing method Download PDFInfo
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- CN105845682B CN105845682B CN201510018162.2A CN201510018162A CN105845682B CN 105845682 B CN105845682 B CN 105845682B CN 201510018162 A CN201510018162 A CN 201510018162A CN 105845682 B CN105845682 B CN 105845682B
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- select transistor
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- 230000015654 memory Effects 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004020 conductor Substances 0.000 claims description 81
- 239000000463 material Substances 0.000 claims description 36
- 238000003475 lamination Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 9
- 238000005253 cladding Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 125000004429 atoms Chemical group 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000005755 formation reaction Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- -1 Boron ion Chemical class 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical compound [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- TWXTWZIUMCFMSG-UHFFFAOYSA-N nitride(3-) Chemical compound [N-3] TWXTWZIUMCFMSG-UHFFFAOYSA-N 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WKODDKLNZNVCSL-UHFFFAOYSA-N 1,3,2$l^{2},4$l^{2}-oxazadisiletidine Chemical compound N1[Si]O[Si]1 WKODDKLNZNVCSL-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N Silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 210000003491 Skin Anatomy 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- XCCANNJCMHMXBZ-UHFFFAOYSA-N hydroxyiminosilicon Chemical compound ON=[Si] XCCANNJCMHMXBZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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Abstract
The invention discloses a kind of memory element and its manufacturing methods.Memory element includes multiple set of bit lines, multiple string select transistor grids, multiple electric charge storage layers and multiple contact window plugs.Multiple set of bit lines are configured in substrate, and each group of set of bit lines includes the multiple bit lines arranged in a first direction, and each bit line extends in a second direction.Each string select transistor grid is connect with two groups of set of bit lines, and each group of set of bit lines is controlled by two string select transistor grids.String select transistor grid includes main part and multiple extensions, between extension extends to every two bit lines by the main part, and it is positioned opposite to each other.Electric charge storage layer is between string select transistor grid and bit line.Contact window plug is located on each string select transistor grid, is electrically connected with string select transistor grid.
Description
Technical field
The invention relates to a kind of memory element and its manufacturing methods.
Background technology
Nonvolatile memory (non-volatile memory) can carry out the behaviour such as the deposit, reading, erasing of multiple data
Make, and even if power supply supply discontinuity, stored data will not disappear.Therefore, nonvolatile memory has become many electricity
Prerequisite memory element in sub- product, normal operating when maintaining electric equipment products to be switched on.
In the operation of memory element, bit line is usually controlled by two string select transistor grids.Work as string select transistor
When grid is " ON " state, allow the bit line that is controlled by it of electric current；When string select transistor grid is " OFF " state,
It can then stop the bit line that electric current is controlled by it.However in traditional memory element, string select transistor grid only with position
One side of line contacts, therefore even if when string select transistor grid is " OFF " state, it would still be possible to have leakage current.
Invention content
A kind of memory element of present invention offer and its manufacturing method are surrounded by string select transistor grid is made in bit line
Three faces of conductor layer can reduce leakage current when carrying out memory element operation.
The present invention memory element, including multiple set of bit lines, multiple string select transistor grids, multiple electric charge storage layers with
And multiple contact window plugs.Multiple set of bit lines are configured in substrate, each group of set of bit lines include arrange in a first direction it is a plurality of
Bit line, each bit line extend in a second direction.Each string select transistor grid is connect with two groups of set of bit lines, and each group of position
Line group is controlled by two string select transistor grids, and string select transistor grid includes main part and multiple extensions, extension
Between every two bit lines being extended to by main part, and it is positioned opposite to each other.Electric charge storage layer be located at string select transistor grid with
Between bit line.Contact window plug is located on each string select transistor grid, is electrically connected with string select transistor grid.
Described in one embodiment of the invention, in above-mentioned memory element, the string select transistor grid has fish-bone
Shape section.
Described in one embodiment of the invention, in above-mentioned memory element, three faces of each bit line are selected by the string
Transistor gate surrounds.
Described in one embodiment of the invention, in above-mentioned memory element, top surface, the bottom surface and first of each bit line
Side wall is surrounded by the string select transistor grid, and the second sidewall of each bit line is contacted with dielectric layer.
The present invention also provides a kind of manufacturing methods of memory element, including lamination and hard mask layer are formed in substrate,
Described in lamination include alternately storehouse multiple first dielectric layers and multiple first conductor layers.Pattern the hard mask layer and institute
Lamination is stated, to form multiple openings.First dielectric layer of the open circumferential between first conductor layer is removed,
Expose the part surface of the multiple first conductor layer of the open circumferential.Form electric charge storage layer, cladding described first
The exposed part surface of conductor layer.It is filled in the opening in being formed in the substrate, and fills in multiple first conductor layers
Between the second conductor layer.Pattern second conductor layer, the hard mask layer, first dielectric layer, charge storage
Layer and first conductor layer are deposited, to form multiple string select transistor grids and multiple set of bit lines, each group of set of bit lines includes
The multiple bit lines arranged in a first direction, each bit line extend in a second direction, and the string select transistor grid includes main body
Portion and multiple extensions, between the extension extends to every two bit lines by the main part, and it is positioned opposite to each other.
The contact window plug being electrically connected with the string select transistor grid is formed on each described string select transistor grid.
Described in one embodiment of the invention, in the manufacturing method of above-mentioned memory element, the opening is along third direction
It is arranged as first row and second row, the opening of the first row is with the opening of the second row in the second direction
It is upper aligned with each other.
Described in one embodiment of the invention, in the manufacturing method of above-mentioned memory element, the opening is along third direction
It is arranged as first row and second row, the opening of the first row is with the opening of the second row in the second direction
On intermesh.
The present invention also provides a kind of manufacturing methods of memory element, including lamination and hard mask layer are formed in substrate,
Described in lamination include alternately storehouse multiple first dielectric layers and multiple first conductor layers.Pattern the hard mask layer and institute
Lamination is stated, to form multiple openings.First dielectric layer of the open circumferential between first conductor layer is removed,
Expose the part surface of the multiple first conductor layer of the open circumferential.Form electric charge storage layer, cladding described first
The exposed part surface of conductor layer.In forming the second conductor material layer in the substrate, fill in the opening, and fill in
Between the multiple first conductor layer.Using the hard mask layer as stop-layer, a flatening process is carried out, removes part described the
Two conductor material layers, in forming the second conductor layer in the substrate.Pattern second conductor layer, the hard mask layer, institute
State the first dielectric layer, the electric charge storage layer and first conductor layer, with formed multiple string select transistor grids with it is multiple
Set of bit lines, each group of set of bit lines include the multiple bit lines arranged in a first direction, and each bit line extends in a second direction, the string
Selection transistor grid includes main part and multiple extensions, and the extension extends to every two institutes rheme by the main part
Between line, and it is positioned opposite to each other.It is formed and the string select transistor grid on each described string select transistor grid
The contact window plug that pole is electrically connected.
Described in one embodiment of the invention, in the manufacturing method of above-mentioned memory element, the opening is along third direction
It is arranged as first row and second row, the opening of the first row is with the opening of the second row in the second direction
It is upper aligned with each other.
Described in one embodiment of the invention, in the manufacturing method of above-mentioned memory element, the opening is along third direction
It is arranged as first row and second row, the opening of the first row is with the opening of the second row in the second direction
On intermesh.
Based on above-mentioned, memory element provided by the invention and its manufacturing method, it can be formed and surround three of conductor layer in bit line
The string select transistor grid in a face, to efficiently reduce leakage current when carrying out memory element operation.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Description of the drawings
Figure 1A to Fig. 1 I is the upper schematic diagram according to the manufacturing method of the memory element depicted in one embodiment of the invention.
Fig. 2A to Fig. 2 I is the diagrammatic cross-section according to the manufacturing method of the memory element depicted in one embodiment of the invention.
Fig. 3 A to Fig. 3 I are to regard signal according to the upper of manufacturing method of the memory element depicted in another embodiment of the present invention
Figure.
Fig. 4 A to Fig. 4 I are to illustrate according to the section of the manufacturing method of the memory element depicted in another embodiment of the present invention
Figure.
Fig. 5 A to Fig. 5 D are to regard signal according to the upper of manufacturing method of the memory element depicted in further embodiment of this invention
Figure.
Fig. 6 is the operation chart of the memory element of the present invention.
【Symbol description】
110、210：Substrate
112、112a、212、212a：Dielectric layer
113、113a、213、213a：Lamination
114、114a、214、214a：First conductor layer
114b、214b：Bit line
115、215：Set of bit lines
116、116a、116b、216、216a、216b、316a、316b：Hard mask layer
118、218、318：Opening
120、120a、220、220a、320、320a：Wash in a pan empty region
122、122a、222、222a、322：Electric charge storage layer
124、224：Second conductor material layer
124a、224a：Second conductor layer
124b、224b、324b：String select transistor grid
125a、225a：Main part
125b、225b：Extension
126、226、326：Dielectric layer
128、228：Contact window plug
410：Shared source pad
412：Shared source contact plug
414a、414b：String selection line
416：Set of bit lines
418：Wordline
420：It is grounded selection line
422：Contact hole
424：String select transistor grid
d1、d2、d3、d4：Distance
D1、D2、D3：Direction
Specific implementation mode
Below in an example, the same or analogous component of same or analogous numbers, can be identical
Or similar material, or can be formed in same or like method.For example, the lamination in second embodiment
213 material and forming method can be to the material identical of the lamination 113 in first embodiment or similar, or can be with phase
With or similar method formed.
Figure 1A to Fig. 1 I is to regard signal according to the upper of manufacturing method of the memory element depicted in first embodiment of the invention
Figure.Fig. 2A to Fig. 2 I is the diagrammatic cross-section according to the manufacturing method of the memory element depicted in first embodiment of the invention.
Figure 1A and Fig. 2A are please referred to, substrate 110 is provided, substrate 110 is, for example, semiconductor base, semiconducting compound substrate
Or there is semiconductor base (Semiconductor Over Insulator, SOI) on insulating layer.Semiconductor is, for example, IVA races
Atom, such as silicon or germanium.Semiconducting compound is, for example, that the atom of IVA races is formed by semiconducting compound, e.g. carbon
SiClx or germanium silicide or Group IIIA atom are formed by semiconducting compound, e.g. GaAs with VA races atom.Substrate
110 can have doping, and the doping of substrate 110 can be p-type or N-type.The doping of p-type can be Group IIIA ion, e.g.
Boron ion.N-type doping can be VA races ion, e.g. arsenic or phosphorus.
Please continue to refer to Figure 1A and Fig. 2A, in formation lamination 113 and hard mask layer 116 in substrate 110.Lamination 113 wraps
Include alternately multiple first dielectric layers 112 of storehouse and multiple first conductor layers 114.The material of first dielectric layer 112 includes oxidation
Object, nitride or combinations thereof.The material of first conductor layer 114 is conductor, including polysilicon, monocrystalline silicon, non-crystalline silicon, multi-crystal silicification
Metal, metal or other applicable conductors.First layer dielectric layer 112 and the method for the first conductor layer 114 formation are, for example,
Chemical vapour deposition technique or spin-coating method.The thickness of every 1 first dielectric layer 112 is, for example, 200 angstroms~500 angstroms, every 1 first conductor
The thickness of layer 114 is, for example, 200 angstroms~500 angstroms, but not limited to this.The material of hard mask layer 116 include silica, silicon nitride,
Silicon oxynitride, silicon carbide, fire sand or combinations thereof, the method formed is, for example, chemical vapour deposition technique.Hard mask layer 116
Thickness be, for example, 800 angstroms~1300 angstroms.
Figure 1B and Fig. 2 B are please referred to, hard mask layer 116 and lamination 113 are patterned, to form multiple openings
118.Opening 118 is arranged in two rows.The shortest distance between first row of openings and the second row of openings is d1.Patterned method is for example
It is first to form patterned mask layer (not being painted) on hard mask layer 116, then carries out anisotropic etching technics to pattern
Hard mask layer 116 and lamination 113.Anisotropic etching e.g. dry etching or wet etching.
Fig. 1 C and Fig. 2 C are please referred to, 118 peripheries of opening, the first dielectric layer between the first conductor layer 114a are removed
112a is formed to expose the part surface of multiple first conductor layer 114a on 118 peripheries of opening and is washed in a pan empty region 120.Herein,
The region that first dielectric layer 112a is removed is known as washing in a pan empty region 120.Wash in a pan the shortest distance between empty region 120 and opening 118
For d2, in one embodiment, d2 is less than d1/2, that is, the naughty empty region of first row open circumferential is washed in a pan with second row open circumferential
Empty region is not connected to each other.It includes etc. that tropisms etching method, e.g. dry etching method or wet method are carved to form the method for washing in a pan empty region
Erosion method.
Fig. 1 D and Fig. 2 D are please referred to, forms electric charge storage layer 122 on the exposed part surfaces of the first conductor layer 114a.Electricity
The cladding of lotus storage layer 122 washes in a pan the surface of the first conductor layer 114a in empty region 120.Electric charge storage layer 122 can be charge trapping
Layer, is formed by dielectric material, e.g. oxide skin(coating) or nitride layer.Electric charge capture layer can also be lamination, e.g.
ONO (oxide-nitride-oxide) layer, that is, including three layers of silicon oxide/silicon nitride/silicon oxide.Electric charge storage layer 122
The method of formation is, for example, thermal oxidation method, chemical vapour deposition technique or atomic layer deposition method.
Fig. 1 E, Fig. 2 E, Fig. 1 F and Fig. 2 F are please referred to, the second conductor material layer 124 is formed, the second conductor material layer 124 is filled out
Enter in opening 118 and fills between multiple first conductor layer 114a.The material of second conductor layer 124 is conductor, including more
Crystal silicon, monocrystalline silicon, non-crystalline silicon, multi-crystal silicification metal, metal or other applicable conductors.Metal be, for example, tungsten, aluminium, copper or its
Alloy.The material of second conductor material layer 124 can be with the material identical of the first conductor layer 114a, also can be different.Then, with reference to figure
1F and Fig. 2 F remove the second conductor material layer washed in a pan on hard mask layer 116a other than empty region 120 using photoetching and etching method
124, to form the second conductor layer 124a.The method of etching includes anisotropic etching, e.g. dry etching method.
Fig. 1 G and Fig. 2 G are please referred to, photoetching and etching technics are carried out, to pattern the second conductor layer 124a, hard mask layer
116a, the first dielectric layer (be located at and wash in a pan other than empty region 120, be not painted in figure), electric charge storage layer 122 and the first conductor layer
114a, to form multiple string select transistor grid 124b, hard mask layer 116b, multiple electric charge storage layer 122a and multiple bit lines
Group 115.Each group of set of bit lines 115 includes the multiple bit lines 114b of D1 arrangements in a first direction, and each bit line 114b is along second
Direction D2 extends.String select transistor grid 124b includes main part 125a and multiple extension 125b.Multiple extension 125b
Main body 125a is extended between every two bit line 114b, and positioned opposite to each other.In one embodiment, main part 125a with
The configuration of extension 125b makes string select transistor grid 124b for example with herring-bone form section.Also, each bit line 114b's
Three faces are surrounded by string select transistor grid 124b.In one embodiment, the top surface, bottom surface of each bit line 114b, Yi Ji
One side wall is surrounded by string select transistor grid 124b.
Fig. 1 H, Fig. 2 H, Fig. 1 I and Fig. 2 I are please referred to, after forming the second dielectric layer 126 in substrate 110, in each string
The contact window plug 128 being electrically connected with string select transistor grid 124b is formed on selection transistor grid 124b.Second is situated between
The material of electric layer 126 includes the combination or combinations thereof of oxide, nitride, ONO and polysilicon.The mode of formation is, for example, chemistry
Vapour deposition process.The material of contact window plug 128 includes metal (being, for example, tungsten, aluminium) or alloy (being, for example, aluminium copper).Shape
At method be, for example, first in substrate 110 formed third dielectric layer (not being painted) to cover wordline, then remove string selection crystal
Part third dielectric layer on tube grid 124b forms multiple openings for exposing string select transistor grid 124b, later in base
Third conductor layer (not being painted) is formed on bottom 110, the third conductor layer is made to insert in the opening, finally carries out a planarization
Technique removes the third conductor layer on the third dielectric layer, to form contact window plug 128.Contact window plug 128
Material include metal (be, for example, tungsten, aluminium) or alloy (being, for example, aluminium copper).
Referring once again to Fig. 1 I and Fig. 2 I, memory element according to an embodiment of the invention includes multiple set of bit lines 115, more
A string select transistor grid 124b, multiple electric charge storage layer 122a and multiple contact window plugs 128.Set of bit lines 115 configures
In in substrate 110.Each group of set of bit lines 115 includes the multiple bit lines 114b of D1 arrangements in a first direction.The edges each bit line 114b
Second direction D2 extends.Each string select transistor grid 124b is connect with two groups of set of bit lines 115, and each group of set of bit lines
115 are controlled by two string select transistor grid 124b.String select transistor grid 124b includes that main part 125a prolongs with multiple
Extending portion 125b.Between extension 125b extends to every two bit line 114b by main part 125a, and it is positioned opposite to each other.Also,
Three faces of each bit line 114b are surrounded by string select transistor grid 124b.Electric charge storage layer 122a is located at string select transistor
Between grid 124b and bit line 114b.Contact window plug 128 is located on each string select transistor grid 124b, brilliant with string selection
Body tube grid 124b is electrically connected.
Fig. 3 A to Fig. 3 I are to regard signal according to the upper of manufacturing method of the memory element depicted in second embodiment of the invention
Figure.Fig. 4 A to Fig. 4 I are the diagrammatic cross-section according to the manufacturing method of the memory element depicted in second embodiment of the invention.
Fig. 3 A and Fig. 4 A are please referred to, according to the method and material of above-mentioned first embodiment, in forming lamination in substrate 210
213 and hard mask layer 216.Lamination 213 includes multiple first dielectric layers 212 and multiple first conductor layers 214 of alternately storehouse.
Please refer to Fig. 3 B and Fig. 4 B, according to the method for above-mentioned first embodiment, to hard mask layer 216 and lamination 213 into
Row patterning, to form multiple openings 218.Opening 218 is arranged in two rows.Most short distance between first row of openings and the second row of openings
From for d3.
Fig. 3 C and Fig. 4 C are please referred to, according to the method for above-mentioned first embodiment, 218 peripheries of opening is removed, is led positioned at first
The first dielectric layer 212a between body layer 214a, to expose the part table of multiple first conductor layer 214a on 218 peripheries of opening
Face forms and washes in a pan empty region 220.The shortest distance washed in a pan between empty region 220 and opening 218 is d4, and in one embodiment, d4 is less than
D3/2, that is, the naughty empty region of first row open circumferential is not connected to each other with the naughty empty region of second row open circumferential.
Fig. 3 D and Fig. 4 D are please referred to, it is exposed in the first conductor layer 214a according to the method and material of above-mentioned first embodiment
Part surface on formed electric charge storage layer 222.The cladding of electric charge storage layer 222 washes in a pan the first conductor layer 214a in empty region 220
Surface.
Fig. 3 E, Fig. 4 E, Fig. 3 F and Fig. 4 F are please referred to, according to the method and material of above-mentioned first embodiment, second is formed and leads
Body material layer 224.Second conductor material layer 224 is filled in opening 218 and is filled between multiple first conductor layer 214a.The
The material of two conductor material layers 224 can be with the material identical of the first conductor layer 214a, also can be different.Then, with hard mask layer
216a is that stop-layer carries out a flatening process, removes the second conductor material washed in a pan on hard mask layer 216a other than empty region 220
Layer 224 forms the second conductor layer 224a.Flatening process is for example including chemical mechanical milling tech.
Fig. 3 G and Fig. 4 G are please referred to, according to the method and material of above-mentioned first embodiment, carries out photoetching and etching technics, with
Patterning hard mask layer 216a, the second conductor layer 224a, the first dielectric layer (be located at and wash in a pan other than empty region 220, be not painted in figure),
Electric charge storage layer 222 and the first conductor layer 214a, to form multiple string select transistor grid 224b, hard mask layer 216b, more
A electric charge storage layer 222a and multiple set of bit lines 215.Each group of set of bit lines 215 includes the multiple bit lines of D1 arrangements in a first direction
214b, and D2 extends each bit line 214b in a second direction.String select transistor grid 224b include main part 225a with it is multiple
Extension 225b.Between multiple extension 225b extend to every two bit line 214b by main part 225a, and it is positioned opposite to each other.
In one embodiment, the configuration of main part 225a and extension 225b makes string select transistor grid 224b for example with herring-bone form
Section.Also, three faces of each bit line 214b are surrounded by string select transistor grid 224b.In one embodiment, each
Top surface, bottom surface and the first side wall of line 214b is surrounded by string select transistor grid 224b.
Fig. 3 H, Fig. 4 H, Fig. 3 I and Fig. 4 I are please referred to, according to the method and material of above-mentioned first embodiment, in substrate 210
After forming the second dielectric layer 226, formed and string select transistor grid 224b on each string select transistor grid 224b
The contact window plug 228 of electric connection.
Referring once again to Fig. 3 I and Fig. 4 I, memory element according to another embodiment of the present invention include multiple set of bit lines 215,
Multiple string select transistor grid 224b, multiple electric charge storage layer 222a and multiple contact window plugs 228.Set of bit lines 215 is matched
It is placed in substrate 210.Each group of set of bit lines 215 includes the multiple bit lines 214b of D1 arrangements in a first direction.Each bit line 214b
D2 extends in a second direction.Each string select transistor grid 224b is connect with two groups of set of bit lines 215, and each group of set of bit lines
215 are controlled by two string select transistor grid 224b.String select transistor grid 224b includes that main part 225a prolongs with multiple
Extending portion 225b.Between extension 225b extends to every two bit line 214b by main part 225a, and it is positioned opposite to each other.Also,
Three faces of each bit line 214b are surrounded by string select transistor grid 224b.Electric charge storage layer 222a is located at string select transistor
Between grid 224b and bit line 214b.Contact window plug 228 is located on each string select transistor grid 224b, brilliant with string selection
Body tube grid 224b is electrically connected.
Fig. 5 A to Fig. 5 D are to regard signal according to the upper of manufacturing method of the memory element depicted in third embodiment of the invention
Figure.
Please refer to Figure 1B and Fig. 3 B, in the opening 118 and 218 of above-mentioned first embodiment and second embodiment, first
Row of openings 118/218 and the second row of openings 118/218 are aligned with each other in a second direction d 2.However, Fig. 5 A are please referred to, in this hair
In bright 3rd embodiment, the first row of openings 318 and the second row of openings 318 in hard mask layer 316a are mutual in a second direction d 2
Staggeredly.Due to opening 318 between distance compared with it is aligned with each other when it is big, thus manufacture memory element when can get larger work
Skill nargin (process window).
Fig. 5 B are please referred to, according to the method and material of above-mentioned first embodiment and second embodiment, is formed and washes in a pan empty region
320.However, the naughty empty region 320 on 318 peripheries of each opening is not connected to each other, but not limited to this.In third embodiment of the invention
In, the plan view shape for washing in a pan empty region 320 is circle, but not limited to this, also can be that ellipse, rectangle etc. are each in other embodiments
Kind shape.Then, exposed in first conductor layer according to the method and material of above-mentioned first embodiment and second embodiment
Part surface forms electric charge storage layer 322, coats the surface for washing in a pan the first conductor layer described in empty region 320.
Fig. 5 C are please referred to, according to the method and material of above-mentioned first embodiment and second embodiment, form multiple set of bit lines
With multiple string select transistor grid 324b.Each group of set of bit lines is included in vertical direction (first direction D1：It is pierced by the side of paper
To) arrangement multiple bit lines, each bit line in a second direction D2 extend.The type of the bit line and string select transistor grid 324b
State and configuration are similar to second embodiment to above-mentioned first embodiment.Specifically, three faces of each bit line are brilliant by string selection
Body tube grid 324b is surrounded.In one embodiment, the top surface, bottom surface of each bit line and the first side wall are by string select transistor
Grid 324b is surrounded.
Fig. 5 D are please referred to, according to the method and material of above-mentioned first embodiment and second embodiment, shape on the substrate
At the second dielectric layer 326.Later, can continue to be formed and string select transistor grid on each string select transistor grid 324b
The contact window plug that pole 324b is electrically connected.
Fig. 6 is the operation chart of the memory element of the present invention.
Fig. 6 is please referred to, memory element of the invention includes multiple set of bit lines 416 that D2 extends in a second direction, shared source
Pole weld pad 410, multiple shared source contact plugs 412, multiple wordline 418 extended along third direction D3, along third direction D3
Ground connection selection line 420, multiple contact holes 422, string selection line (SSL) 414a, 414b and the multiple string select transistors of extension
Grid 424.Shared source pad 410 is located on multiple shared source contact plugs 412.Shared source contact plug 412 connects
It (is not painted) to source area.Contact hole 422 is connected to drain area (not being painted).The selection line 414a and string selection line 414b that goes here and there distinguishes
It is coupled with multiple string select transistor grids 424.Each string select transistor grid 424 is connect with two groups of set of bit lines 416, and
Each group of set of bit lines 416 is controlled by two string select transistor grids 424.Multiple wordline 418 be configured at string selection line 414b with
It is grounded between selection line 420.In figure 6, when one of string select transistor grid 424 is " ON " state, allow electric current
The two groups of set of bit lines 416 controlled by it；When one of string select transistor grid 424 is " OFF " state, then can hinder
Two groups of set of bit lines 416 that gear electric current is controlled by it.In the memory element of the present invention, since three faces of bit line are selected by string
Transistor gate surrounds (as shown in Fig. 2 I, Fig. 4 I), therefore, when two string select transistor grid for controlling one group of set of bit lines 416
When at least one of pole 424 string select transistor grid 424 is " OFF " state, it is possible to reduce leakage current.
In conclusion memory element provided by the invention and its manufacturing method, can form and surround three of conductor layer in bit line
The string select transistor grid in a face, therefore when carrying out memory element operation, leakage current can be efficiently reduced.The present invention can
Manufacture applied to semiconductor elements such as nonvolatile memory, NAND gate flash memories (NAND Flash Memory).And its work
Artistic skill and prior art are integrated, of low cost.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, thus it is of the invention
Protection domain subject to be defined depending on appended claims range.
Claims (10)
1. a kind of memory element, including：
Multiple set of bit lines, are configured in substrate, and each group of set of bit lines includes the multiple bit lines arranged in a first direction, each bit line
Extend in a second direction；
Multiple string select transistor grids, each string select transistor grid are connect with set of bit lines described in two groups, and every
One group of set of bit lines is controlled by two string select transistor grids, the string select transistor grid include main part with it is multiple
Extension, between the extension extends to every two bit lines by the main part, and it is positioned opposite to each other；
Multiple electric charge storage layers, between the string select transistor grid and the bit line；And
Multiple contact window plugs are located on each string select transistor grid, electrical with the string select transistor grid
Connection.
2. memory element according to claim 1, wherein the string select transistor grid has herring-bone form section.
3. memory element according to claim 1, wherein three faces of each bit line are by the string select transistor grid
It surrounds.
4. memory element according to claim 3, wherein the top surface of each bit line, bottom surface and the first side wall are described
String select transistor grid surrounds, and the second sidewall of each bit line is contacted with dielectric layer, which is each bit line
Top surface, the part that is not surrounded by the string select transistor grid except bottom surface and the first side wall.
5. a kind of manufacturing method of memory element, including：
Lamination and hard mask layer are formed in substrate, wherein the lamination include alternately multiple first dielectric layers of storehouse with it is multiple
First conductor layer；
The hard mask layer and the lamination are patterned, to form multiple openings；
First dielectric layer of the open circumferential between first conductor layer is removed, the open circumferential is exposed
The multiple first conductor layer part surface；
Electric charge storage layer is formed, the part table of the multiple first conductor layer of the open circumferential is exposed described in cladding
Face；
It is filled in the opening in being formed in the substrate, and fills in the second conductor between the multiple first conductor layer
Layer；
Pattern second conductor layer, the hard mask layer, first dielectric layer, the electric charge storage layer and described first
Conductor layer, to form multiple string select transistor grids and multiple set of bit lines, each group of set of bit lines includes arranging in a first direction
Multiple bit lines, each bit line extends in a second direction, and the string select transistor grid includes main part and multiple extensions,
Between the extension extends to every two bit lines by the main part, and it is positioned opposite to each other；And
The contact hole being electrically connected with the string select transistor grid is formed on each described string select transistor grid
Plug.
6. the manufacturing method of memory element according to claim 5, wherein the opening is arranged as first along third direction
Row and second row, the opening of the first row are mutually opposite in this second direction with the opening of the second row
Together.
7. the manufacturing method of memory element according to claim 5, wherein the opening is arranged as first along third direction
Row and second row, the opening of the first row mutually intersect in this second direction with the opening of the second row
It is wrong.
8. a kind of manufacturing method of memory element, including：
Lamination and hard mask layer are formed in substrate, wherein the lamination include alternately multiple first dielectric layers of storehouse with it is multiple
First conductor layer；
The hard mask layer and the lamination are patterned, to form multiple openings；
First dielectric layer of the open circumferential between first conductor layer is removed, the open circumferential is exposed
The multiple first conductor layer part surface；
Electric charge storage layer is formed, the part table of the multiple first conductor layer of the open circumferential is exposed described in cladding
Face；
It in forming the second conductor material layer in the substrate, fills in the opening, and fills in the multiple first conductor
Between layer；
Using the hard mask layer as stop-layer, a flatening process is carried out, part second conductor material layer is removed, in described
The second conductor layer is formed in substrate；
Pattern second conductor layer, the hard mask layer, first dielectric layer, the electric charge storage layer and described first
Conductor layer, to form multiple string select transistor grids and multiple set of bit lines, each group of set of bit lines includes arranging in a first direction
Multiple bit lines, each bit line extends in a second direction, and the string select transistor grid includes main part and multiple extensions,
Between the extension extends to every two bit lines by the main part, and it is positioned opposite to each other；And
The contact hole being electrically connected with the string select transistor grid is formed on each described string select transistor grid
Plug.
9. the manufacturing method of memory element according to claim 8, wherein the opening is arranged as first along third direction
Row and second row, the opening of the first row are mutually opposite in this second direction with the opening of the second row
Together.
10. the manufacturing method of memory element according to claim 8, wherein the opening is arranged as first along third direction
Row and second row, the opening of the first row mutually intersect in this second direction with the opening of the second row
It is wrong.
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|---|---|---|---|
| CN201510018162.2A CN105845682B (en) | 2015-01-14 | Memory element and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510018162.2A CN105845682B (en) | 2015-01-14 | Memory element and its manufacturing method |
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| CN105845682B true CN105845682B (en) | 2018-08-31 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811516A (en) * | 2010-12-14 | 2014-05-21 | 桑迪士克3D有限责任公司 | Non-volatile memory having 3d array of read/write elements with low current structures and methods thereof |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811516A (en) * | 2010-12-14 | 2014-05-21 | 桑迪士克3D有限责任公司 | Non-volatile memory having 3d array of read/write elements with low current structures and methods thereof |
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