CN105827555A - Data equalizing method and equalizer - Google Patents
Data equalizing method and equalizer Download PDFInfo
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- CN105827555A CN105827555A CN201510005303.7A CN201510005303A CN105827555A CN 105827555 A CN105827555 A CN 105827555A CN 201510005303 A CN201510005303 A CN 201510005303A CN 105827555 A CN105827555 A CN 105827555A
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Abstract
The invention discloses a data equalizing method and an equalizer. The data equalizing method comprises the steps of acquiring received frequency domain chip data and generated frequency domain SCH estimation, acquiring frequency domain chip data with SCH being eliminated according to the frequency domain chip data and the frequency domain SCH estimation, and outputting the frequency domain chip data after data equalizing treatment is carried out on the frequency domain chip data with the SCH being eliminated. Time domain conversion is not required to be carried out before data equalization, so that the computation complexity and a treatment test are reduced, and the power consumption of UE is lowered.
Description
Technical field
The invention belongs to communication technical field, particularly relate to data balancing method and the equalizer of a kind of chip-level.
Background technology
High-speed slender body theory (the High-SpeedDownlinkPacketAccess+ of evolution, HSDPA+) have been used for strengthening existing WCDMA (WidebandCodeDivisionMultipleAccess, WCDMA) system, higher data rate is provided for mobile subscriber, 42Mbps is reached in order to ensure downstream rate, HSDPA/HSDPA+ system have employed three key properties: adaptive modulation and coding (AdaptiveModulationandCoding, AMC), hybrid automatic retransmission request (HybridAutomaticRepeatRequest, and fast dispatch HARQ).Typical WCDMA receiver generally uses RAKE framework, owing to RAKE receiver is reducing multi-access inference (MultipleAccessInterference, MAI) (Inter-PathInterference is disturbed and/or between link, IPI) aspect is not very good, when in system, the quantity of mobile subscriber increases or during in non line of sight condition, the performance of RAKE receiver will necessarily deteriorate.On the contrary, in HSDPA system, chip equalizer can realize reducing MAI and IPI for cost with complexity, can become the optional solution of RAKE receiver simultaneously.
At the senior receiver defined in 3GPPTS25.101 by following tagsort:
Type1: receive diversity (RXdiversity)
Type2: linear minimum mean-squared error (LinearMinimumMeanSquareError, LMMSE) chip-level equalizer (chip-levelequalizer, EQ)
Type3:RXdiversity+LMMSEEQ
Type3I:RXdiversity+ considers the EQ of interference
Existing for WCDMA downlink linear receiver, approximate minimum mean square (MMSE) equalizer by mistake is individual preferably alternative.Relative to traditional RAKE receptor and zero forcing equalizer, MMSE chip-level equalizer improves performance, but shortcoming is the higher computation complexity brought due to matrix transpose.
HSDPA+ has the advantages that to provide high data rate for packet data service, and in order to obtain higher data rate in HSDPA+ system, high-order modulating is used, such as 64QAM.Higher modulating mode is more sensitive to the interference from synchronous channel SCH, this is because SCH is not orthogonal data coding, SCH chip power more mono-than high-speed physical downlink shared channel (HS-PDSCH) HS-PDSCH is big.In order to less SCH interference strengthens handling capacity, it is necessary to SCH interference can be eliminated in the data balancing stage.
It is illustrated in figure 1 SCH based on time domain interference elimination and realizes principle.From figure 1 it appears that after time domain channel estimates that the signal produced with SCH sequencer carries out convolutional calculation, the SCH obtaining receiving estimates；In the time domain, estimate that the chip data received are carried out interference eliminates, and obtains the chip data after the elimination SCH received according to the SCH received；Carrying out the chip data after the elimination SCH of the reception that Fourier transformation (FFT) obtains frequency domain the most again, the channel estimation in frequency domain after estimating FFT with time domain channel carries out equilibrium treatment, is equalized the output data of device.
Above-mentioned SCH based on time domain disturbs elimination, realize in time domain owing to SCH interference eliminates, then data balancing has to wait SCH elimination to complete in time domain, then could start to realize frequency domain data equilibrium, therefore, SCH based on time domain eliminates causing balancing procedure waiting time increase and complexity are higher.
Accordingly, it would be desirable to a kind of method of novel actuating code chip level data balancing, MAI can not only be suppressed, and recover the orthogonality of coding, reduce IPI, and be not also not result in that the waiting time increases with complexity for cost.
Summary of the invention
In view of this, it is an object of the present invention to provide a kind of data balancing method and equalizer, in order to solve present in prior art during data balancing, cause the waiting time long to suppress MAI and IPI, the problem that complex disposal process is high.In order to some aspects of the embodiment disclosed are had a basic understanding, shown below is simple summary.This summarized section is not extensive overview, is not key/critical component to be determined or the protection domain describing these embodiments.Its sole purpose is to present some concepts, in this, as the preamble of following detailed description by simple form.
The embodiment of the present invention provides a kind of data balancing method, including:
The frequency domain SCH obtaining frequency domain chip data and the generation received estimates；
Estimate to be eliminated the frequency domain chip data after SCH according to described frequency domain chip data and described frequency domain SCH；
Export after frequency domain chip data after eliminating SCH are carried out data balancing process.
In some optional embodiments, frequency domain chip data and the frequency domain SCH of generation that described acquisition receives estimate, specifically include:
The chip data received are transformed to frequency domain chip data；
The SCH signal of generation is converted to frequency domain SCH signal, and time domain channel is estimated to be transformed to channel estimation in frequency domain, obtains described frequency domain SCH according to described frequency domain SCH signal and described channel estimation in frequency domain and estimates.
In some optional embodiments, the described frequency domain SCH obtaining receiving according to described frequency domain SCH signal and described channel estimation in frequency domain estimates, specifically includes:
Described frequency domain SCH signal is multiplied with described channel estimation in frequency domain, obtains described frequency domain SCH and estimate.
In some optional embodiments,
The chip data received are carried out fast Fourier transform FFT, obtains frequency domain chip data；
The SCH signal produced is carried out fast Fourier transform FFT, obtains frequency domain SCH signal；
Estimate to carry out fast Fourier transform FFT to time domain channel, obtain channel estimation in frequency domain.
In some optional embodiments, estimate to be eliminated the frequency domain chip data after SCH according to described frequency domain chip data and described frequency domain SCH, specifically include:
Estimate to subtract each other by described frequency domain chip data and described frequency domain SCH, the frequency domain chip data after the SCH that is eliminated；Or
Estimate to be added by described frequency domain chip data and described frequency domain SCH of the inverted, the frequency domain chip data after the SCH that is eliminated.
In some optional embodiments, export after the frequency domain chip data after eliminating SCH are carried out data balancing process, specifically include:
Frequency domain chip data after eliminating SCH input data as one, and channel estimation in frequency domain inputs data as another, carries out data balancing process, the frequency domain chip data output after processing.
The present invention also provides for a kind of equalizer, including:
Signal acquisition module, estimates for obtaining the frequency domain SCH of frequency domain chip data and the generation received；
Interference cancellation module, the frequency domain chip data after the SCH that estimates according to described frequency domain chip data and described frequency domain SCH to be eliminated；
Balance processing module, exports after the frequency domain chip data after eliminating SCH are carried out data balancing process.
In some optional embodiments, described signal acquisition module, specifically for:
The chip data received are transformed to frequency domain chip data；
The SCH signal of generation is converted to frequency domain SCH signal, and time domain channel is estimated to be transformed to channel estimation in frequency domain, obtains described frequency domain SCH according to described frequency domain SCH signal and described channel estimation in frequency domain and estimates.
In some optional embodiments, described signal acquisition module, specifically for:
Described frequency domain SCH signal is multiplied with described channel estimation in frequency domain, obtains described frequency domain SCH and estimate.
In some optional embodiments, described signal acquisition module, specifically for:
The chip data received are carried out fast Fourier transform FFT, obtains frequency domain chip data；
The SCH signal produced is carried out fast Fourier transform FFT, obtains frequency domain SCH signal；
Estimate to carry out fast Fourier transform FFT to time domain channel, obtain channel estimation in frequency domain.
In some optional embodiments, described interference cancellation module, specifically for:
Estimate to subtract each other by described frequency domain chip data and described frequency domain SCH, the frequency domain chip data after the SCH that is eliminated；Or
Estimate to be added by described frequency domain chip data and described frequency domain SCH of the inverted, the frequency domain chip data after the SCH that is eliminated.
In some optional embodiments, described balance processing module, specifically for:
Frequency domain chip data after eliminating SCH input data as one, and channel estimation in frequency domain inputs data as another, carries out data balancing process, the frequency domain chip data output after processing.
The data balancing method of embodiment of the present invention offer and equalizer, the frequency domain SCH obtaining frequency domain chip data and the generation received estimates, estimate to be eliminated the frequency domain chip data after SCH according to described frequency domain chip data and described frequency domain SCH, export after carrying out data balancing process.The method realizes SCH interference in a frequency domain and eliminates, and need not perform time domain conversion again, decrease computation complexity and process test, reducing the power consumption of UE before data balancing.And when eliminating interference during data balancing, it is possible to realize suppression MAI, reduce IPI, and do not increase the waiting time, the most not with complexity as cost, it is achieved be simple and convenient.
For above-mentioned and relevant purpose, one or more embodiments include the feature that will be explained in below and be particularly pointed out in the claims.Description below and accompanying drawing describe some modes in some illustrative aspects, and the utilizable various modes of principle of only each embodiment of its instruction in detail.Other benefit and novel features will be considered in conjunction with the accompanying along with detailed description below and become obvious, and the disclosed embodiments are intended to include all these aspect and their equivalent.
Figure of description
Fig. 1 is that in prior art, SCH based on time domain interference elimination realizes principle schematic；
Fig. 2 is the flow chart of data balancing method in the embodiment of the present invention；
Fig. 3 be in the embodiment of the present invention data balancing method realize principle schematic；
Fig. 4 is the structural representation of equalizer in the embodiment of the present invention.
Detailed description of the invention
The following description and drawings illustrate specific embodiments of the present invention fully, to enable those skilled in the art to put into practice them.Other embodiments can include structure, logic, electric, process and other change.Embodiment only represents possible change.Unless explicitly requested, otherwise individually assembly and function are optional, and the order operated can change.The part of some embodiments and feature can be included in or replace part and the feature of other embodiments.The scope of embodiment of the present invention includes the gamut of claims, and all obtainable equivalent of claims.In this article, these embodiments of the present invention can be represented by " inventing " individually or generally with term, this is only used to conveniently, and if in fact disclose the invention more than, it is not meant to automatically limit this application in the range of any single invention or inventive concept.
Increase and complexity problem to solve the prior art waiting time in balancing procedure, the embodiment of the present invention provides the data balancing method of a kind of new chip-level, before the data balancing of actuating code chip level, the interference realizing synchronizing channel based on frequency domain eliminates, thus reduce the waiting time, and do not increase complexity.
The data balancing method that the embodiment of the present invention provides, it realizes flow process as in figure 2 it is shown, comprise the steps:
Step S101: the frequency domain SCH obtaining frequency domain chip data and the generation received estimates.
After receiving chip data, the chip data received are transformed to frequency domain chip data.
Produce a SCH signal, the SCH signal of generation is converted to frequency domain SCH signal, generate a time domain channel and estimate, estimate to be transformed to channel estimation in frequency domain by time domain channel, obtain frequency domain SCH according to frequency domain SCH signal and channel estimation in frequency domain and estimate.
Step S102: estimate according to the frequency domain SCH of the frequency domain chip data received and generation, the frequency domain chip data after the SCH that is eliminated.
Optionally, can estimate to subtract each other by frequency domain chip data and frequency domain SCH, the frequency domain chip data after the SCH that is eliminated.
Optionally, frequency domain SCH is estimated that march is all, estimate to be added by frequency domain chip data and frequency domain SCH of the inverted, the frequency domain chip data after the SCH that is eliminated.
Step S103: export after the frequency domain chip data after eliminating SCH are carried out data balancing process.
When frequency domain chip data carry out data balancing process, the frequency domain chip data after eliminating SCH input data as input data and channel estimation in frequency domain as another, carry out data balancing process, the frequency domain chip data output after processing.
Said method is in a frequency domain, from the frequency domain chip data signal received, deduct SCH receive the estimated value of signal, obtain the frequency domain chip data after the elimination SCH of frequency domain, input data as equilibrium treatment, channel estimation in frequency domain, as another input data of equilibrium treatment, obtains data output after data balancing processes.
The data balancing method that the embodiment of the present invention provides, it realizes principle and illustrates as shown in Figure 3.Including following processing procedure:
The chip data received are carried out fast Fourier transform (FastFourierTransformation, FFT), obtains frequency domain chip data.The SCH signal produced is carried out fast Fourier transform (FFT), obtains frequency domain SCH signal.Estimate to carry out fast Fourier transform (FFT) to time domain channel, obtain channel estimation in frequency domain.Thus realize each signal is transformed from the time domain to frequency domain.
Wherein, SCH signal can be produced by SCH sequencer.SCH sequencer can be an independent module, and the local SCH sequence of independent generation, it is also possible to from other unit, such as cell search unit input produces SCH sequence.
Having used multiplier in Fig. 3, be multiplied with channel estimation in frequency domain by frequency domain SCH signal, the frequency domain SCH obtaining receiving estimates.Optionally, the multiplier in Fig. 3 is multiplied and can also replace with proportional zoom.
Fig. 3 uses subtractor, has estimated to subtract each other by the frequency domain SCH of the frequency domain chip data of reception with reception, obtain the frequency domain chip data after the elimination SCH received.Optionally, the subtractor in Fig. 3 also can be replaced by adder, only need to estimate to negate to the frequency domain SCH received before performing additional calculation.
Based on same inventive concept, the embodiment of the present invention also provides for a kind of equalizer, its structure as shown in Figure 4, including signal acquisition module 401, interference cancellation module 402 and balance processing module 403.
Signal acquisition module 401, estimates for obtaining the frequency domain SCH of frequency domain chip data and the generation received.
Interference cancellation module 402, the frequency domain chip data after the SCH that estimates according to described frequency domain chip data and described frequency domain SCH to be eliminated.
Balance processing module 403, exports after the frequency domain chip data after eliminating SCH are carried out data balancing process.
Preferably, above-mentioned signal acquisition module 401, specifically for being transformed to frequency domain chip data by the chip received data；The SCH signal of generation is converted to frequency domain SCH signal, and time domain channel is estimated to be transformed to channel estimation in frequency domain, obtains frequency domain SCH according to frequency domain SCH signal and channel estimation in frequency domain and estimates.
Preferably, above-mentioned signal acquisition module 401, specifically for frequency domain SCH signal is multiplied with channel estimation in frequency domain, obtains frequency domain SCH and estimate.
Preferably, above-mentioned signal acquisition module 401, specifically for the chip data received are carried out fast Fourier transform FFT, obtain frequency domain chip data；The SCH signal produced is carried out fast Fourier transform FFT, obtains frequency domain SCH signal；Estimate to carry out fast Fourier transform FFT to time domain channel, obtain channel estimation in frequency domain.
Preferably, above-mentioned interference cancellation module 402, specifically for estimating to subtract each other by frequency domain chip data and frequency domain SCH, the frequency domain chip data after the SCH that is eliminated；Or estimate to be added by frequency domain chip data and frequency domain SCH of the inverted, the frequency domain chip data after the SCH that is eliminated.
Preferably, above-mentioned balance processing module 403, specifically for using the frequency domain chip data after elimination SCH as input data, channel estimation in frequency domain inputs data as another, carries out data balancing process, the frequency domain chip data output after processing.
The above-mentioned data balancing method of embodiment of the present invention offer and equalizer, compared with the elimination of existing time domain SCH, for estimating that the convolution operation that the SCH received is carried out is operated replacement by frequency domain convolution.This is equivalent to carry out the SCH signal of generation fast Fourier transform (FFT) and carries out pointwise with channel estimation in frequency domain afterwards and be multiplied, and so relative time domain operation processing delay is negligible, and can reuse FFT operation and reduce convolution complexity.
Said method SCH interference elimination before data balancing need not perform time domain conversion, and the circuit changed owing to performing time domain compares FFT needs much bigger amount of calculation, and therefore this processing mode greatly reduces amount of calculation.Eliminate and in frequency domain chip-level data balancing owing to channel estimation in frequency domain information may apply to SCH interference, therefore can reuse FFT operation.Eliminate due to SCH interference and data balancing exists simultaneously, i.e. connect SCH interference and eliminate and data balancing, reduce computation complexity and processing delay, reduce UE power consumption.
Said method strengthens the estimation to the SCH received, this is because time domain performs the SCH received estimating, the channel relying on to be come by SCH sequence transformation estimates the output of time-domain information.When time domain channel-estimation information is bigger (packet is containing very many taps), the amount of calculation of conversion will be very big, and need time-based the blocking estimated by a time domain channel to reduce amount of calculation in existing method.And the SCH interference that so can limit reception eliminates the precision estimated.
Unless otherwise specific statement, term such as processes, calculates, computing, determine, display etc. can refer to that one or more processes or calculating system or the action of similar devices and/or process, described action and/or process will be indicated as the data manipulation that the physics (such as electronics) in the depositor of processing system or memorizer is measured and other data being converted into the physical quantity being similarly represented as in the memorizer of processing system, depositor or the storage of other this type of informations, transmitting or display device.Information and signal can use any one of multiple different technology and method to represent.Such as, the data mentioned in running through above description, instruct, order, information, signal, bit, symbol and chip can represent by voltage, electric current, electromagnetic wave, magnetic field or particle, light field or particle or its combination in any.
The particular order of the step during disclosed in should be understood that or level are the examples of illustrative methods.Based on design preference, it should be appreciated that during the particular order of step or level can be rearranged in the case of without departing from the protection domain of the disclosure.Appended claim to a method gives the key element of various step with exemplary order, and is not limited to described particular order or level.
In above-mentioned detailed description, various features combine together in single embodiment, to simplify the disclosure.Should not be construed to reflect such intention by this open method, i.e. the embodiment of theme required for protection is it will be clear that the more feature of feature stated in each claim of ground.On the contrary, as the following claims reflect, the present invention is in the state fewer than whole features of disclosed single embodiment.Therefore, appending claims is hereby expressly incorporated in detailed description, and wherein each claim is alone as the single preferred embodiment of the present invention.
It should also be appreciated by one skilled in the art that the various illustrative box, module, circuit and the algorithm steps that combine the embodiments herein description all can be implemented as electronic hardware, computer software or a combination thereof.In order to clearly demonstrate the interchangeability between hardware and software, above various illustrative parts, frame, module, circuit and step are all generally described around its function.It is implemented as hardware as this function and is also implemented as software, depend on the design constraint specifically applied and whole system is applied.Those skilled in the art can realize described function for each application-specific in the way of flexible, but, this realize decision-making and should not be construed as the protection domain deviating from the disclosure.
Step in conjunction with the method described by the embodiments herein or algorithm can be embodied directly in hardware, the processor software module performed or a combination thereof.Software module may be located in the storage medium of RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, depositor, hard disk, mobile disk, CD-ROM or other form any well known in the art.A kind of exemplary storage medium is connected to processor, thus enables a processor to from this read information, and can write information to this storage medium.Certainly, storage medium can also be the ingredient of processor.Processor and storage medium may be located in ASIC.This ASIC may be located in user terminal.Certainly, processor and storage medium can also be present in user terminal as discrete assembly.
Realizing for software, technology described in this application can realize by the module (such as, process, function etc.) performing herein described function.These software codes can be stored in memory cell and be performed by processor.Memory cell can be implemented in processor, it is also possible to realizing outside processor, in the case of the latter, it is communicably coupled to processor via various means, and these are all well known in the art.
Described above includes the citing of one or more embodiment.Certainly, all possible combination describing parts or method in order to describe above-described embodiment is impossible, but it will be appreciated by one of ordinary skill in the art that each embodiment can do further combinations and permutations.Therefore, embodiment described herein is intended to all such changes, modifications and variations fallen within scope of appended claims.Additionally, the term with regard to using in description or claims " comprises ", the mode that contains of this word is similar to term and " includes ", as being explained as link word in the claims just as " including, ".Additionally, use any one term in the description of claims " or " be intended to represent " non-exclusionism or ".
Claims (12)
1. a data balancing method, it is characterised in that including:
The frequency domain SCH obtaining frequency domain chip data and the generation received estimates；
Estimate to be eliminated the frequency domain chip data after SCH according to described frequency domain chip data and described frequency domain SCH；
Export after frequency domain chip data after eliminating SCH are carried out data balancing process.
2. the method for claim 1, it is characterised in that frequency domain chip data and the frequency domain SCH of generation that described acquisition receives estimate, specifically include:
The chip data received are transformed to frequency domain chip data；
The SCH signal of generation is converted to frequency domain SCH signal, and time domain channel is estimated to be transformed to channel estimation in frequency domain, obtains described frequency domain SCH according to described frequency domain SCH signal and described channel estimation in frequency domain and estimates.
3. method as claimed in claim 2, it is characterised in that the described frequency domain SCH obtaining receiving according to described frequency domain SCH signal and described channel estimation in frequency domain estimates, specifically includes:
Described frequency domain SCH signal is multiplied with described channel estimation in frequency domain, obtains described frequency domain SCH and estimate.
4. method as claimed in claim 2, it is characterised in that
The chip data received are carried out fast Fourier transform FFT, obtains frequency domain chip data；
The SCH signal produced is carried out fast Fourier transform FFT, obtains frequency domain SCH signal；
Estimate to carry out fast Fourier transform FFT to time domain channel, obtain channel estimation in frequency domain.
5. the method as described in claim 1-4 is arbitrary, it is characterised in that estimate to be eliminated the frequency domain chip data after SCH according to described frequency domain chip data and described frequency domain SCH, specifically include:
Estimate to subtract each other by described frequency domain chip data and described frequency domain SCH, the frequency domain chip data after the SCH that is eliminated；Or
Estimate to be added by described frequency domain chip data and described frequency domain SCH of the inverted, the frequency domain chip data after the SCH that is eliminated.
6. the method as described in claim 1-4 is arbitrary, it is characterised in that export after the frequency domain chip data after eliminating SCH are carried out data balancing process, specifically include:
Frequency domain chip data after eliminating SCH input data as one, and channel estimation in frequency domain inputs data as another, carries out data balancing process, the frequency domain chip data output after processing.
7. an equalizer, it is characterised in that including:
Signal acquisition module, estimates for obtaining the frequency domain SCH of frequency domain chip data and the generation received；
Interference cancellation module, the frequency domain chip data after the SCH that estimates according to described frequency domain chip data and described frequency domain SCH to be eliminated；
Balance processing module, exports after the frequency domain chip data after eliminating SCH are carried out data balancing process.
8. equalizer as claimed in claim 7, it is characterised in that described signal acquisition module, specifically for:
The chip data received are transformed to frequency domain chip data；
The SCH signal of generation is converted to frequency domain SCH signal, and time domain channel is estimated to be transformed to channel estimation in frequency domain, obtains described frequency domain SCH according to described frequency domain SCH signal and described channel estimation in frequency domain and estimates.
9. equalizer as claimed in claim 8, it is characterised in that described signal acquisition module, specifically for:
Described frequency domain SCH signal is multiplied with described channel estimation in frequency domain, obtains described frequency domain SCH and estimate.
10. equalizer as claimed in claim 8, it is characterised in that described signal acquisition module, specifically for:
The chip data received are carried out fast Fourier transform FFT, obtains frequency domain chip data；
The SCH signal produced is carried out fast Fourier transform FFT, obtains frequency domain SCH signal；
Estimate to carry out fast Fourier transform FFT to time domain channel, obtain channel estimation in frequency domain.
11. equalizer as described in claim 7-10 is arbitrary, it is characterised in that described interference cancellation module, specifically for:
Estimate to subtract each other by described frequency domain chip data and described frequency domain SCH, the frequency domain chip data after the SCH that is eliminated；Or
Estimate to be added by described frequency domain chip data and described frequency domain SCH of the inverted, the frequency domain chip data after the SCH that is eliminated.
12. equalizer as described in claim 7-10 is arbitrary, it is characterised in that described balance processing module, specifically for:
Frequency domain chip data after eliminating SCH input data as one, and channel estimation in frequency domain inputs data as another, carries out data balancing process, the frequency domain chip data output after processing.
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