CN105826385B - Method of manufacturing semiconductor device having fin-shaped pattern - Google Patents

Method of manufacturing semiconductor device having fin-shaped pattern Download PDF

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Publication number
CN105826385B
CN105826385B CN201610032156.7A CN201610032156A CN105826385B CN 105826385 B CN105826385 B CN 105826385B CN 201610032156 A CN201610032156 A CN 201610032156A CN 105826385 B CN105826385 B CN 105826385B
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fin
pattern
forming
fin pattern
oxide film
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CN105826385A (en
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刘庭均
朴世玩
都承右
朴寅源
成石铉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps: forming a first fin-shaped pattern including an upper portion and a lower portion on a substrate; forming a second fin pattern by removing a portion of an upper portion of the first fin pattern; forming a dummy gate electrode crossing the second fin pattern on the second fin pattern; and forming a third fin pattern by removing a portion of an upper portion of the second fin pattern after forming the dummy gate electrode, wherein a width of the upper portion of the second fin pattern is smaller than a width of the upper portion of the first fin pattern and larger than a width of the upper portion of the third fin pattern.

Description

Method of manufacturing semiconductor device having fin-shaped pattern
Cross Reference to Related Applications
This application claims priority from korean patent application No.10-2015-0012630, filed by the korean intellectual property office on 27/1/2015, which is incorporated herein by reference in its entirety.
Technical Field
The present inventive concept relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that adjusts a channel shape of a fin field effect transistor (FINFET).
Background
One technique for increasing the integration density of semiconductor devices is to use multi-gate transistors in which a fin-shaped semiconductor body is formed on a substrate and a gate is formed on a surface of the semiconductor body. Since such multi-gate transistors utilize three-dimensional channels, they can be more easily scaled. Multi-gate transistors may also exhibit improved current control capability without increasing the gate length of the transistor. The multi-gate transistor may also reduce or eliminate Short Channel Effects (SCE) in which the channel region potential is affected by the drain voltage.
Disclosure of Invention
Aspects of the inventive concept provide a method for manufacturing a semiconductor device, which may exhibit improved performance by enhancing a width effect by adjusting a channel shape of a fin field effect transistor (FINFET).
Aspects of the inventive concept are not limited to the above aspects, and other aspects not described will be clearly understood by those skilled in the art from the following description.
According to an aspect of the inventive concept, there is provided a method for manufacturing a semiconductor device, the method including: forming a first fin-shaped pattern including an upper portion and a lower portion on a substrate; forming a second fin pattern by removing a portion of an upper portion of the first fin pattern; forming a dummy gate electrode crossing the second fin pattern on the second fin pattern; and forming a third fin pattern by removing a portion of an upper portion of the second fin pattern after forming the dummy gate electrode, wherein a width of the upper portion of the second fin pattern at a first height above the upper surface of the substrate is less than a width of the upper portion of the first fin pattern at the first height and is greater than a width of the upper portion of the third fin pattern at the first height.
In some embodiments, the step of forming the second fin pattern comprises: a first oxide film is formed along a contour of an upper portion of the first fin pattern, and then the first oxide film is removed.
In some embodiments, the step of forming the first oxide film includes: a portion of an upper portion of the first fin pattern is oxidized.
In some embodiments, the step of forming the third fin pattern comprises: forming a second oxide film along an outline of an upper portion of the second fin pattern before forming the dummy gate electrode; and removing the second oxide film after the dummy gate electrode is formed.
In some embodiments, the step of forming the second oxide film includes: a portion of an upper portion of the second fin pattern is oxidized.
In some embodiments, the method may further comprise the step of: a third oxide film is formed along a contour of an upper portion of the third fin pattern by oxidizing a portion of the upper portion of the third fin pattern.
In some embodiments, the first fin pattern includes sidewalls, an upper surface, and corner portions where the sidewalls meet the upper surface. The method may further comprise the steps of: before forming the second fin pattern, corners are rounded by etching the first fin pattern.
In some embodiments, the method may further comprise the step of: a field insulating film is formed on the substrate before rounding the corner portions. The upper portion of the first fin-shaped pattern protrudes above the upper surface of the field insulating film.
In some embodiments, the step of forming the first fin pattern comprises: forming a fourth fin-shaped pattern including an upper portion and a lower portion on the substrate; forming a field insulating film directly contacting a lower portion of the fourth fin pattern and not directly contacting an upper portion of the fourth fin pattern; and removing a portion of an upper portion of the fourth fin pattern after forming the field insulating film.
In some embodiments, the step of forming the first fin pattern comprises: and forming an oxide film along the contour of the upper part of the fourth fin-shaped pattern, and removing the oxide film.
In some embodiments, a width of an upper portion of the first fin pattern at the first height is less than a width of an upper portion of the fourth fin pattern at the first height.
In some embodiments, the fourth fin pattern includes sidewalls, an upper surface, and corner portions where the sidewalls meet the upper surface. The method may further comprise: before forming the first fin pattern, corners are rounded by etching the fourth fin pattern.
In some embodiments, the method may further comprise the step of: and forming a gate electrode crossing the third fin pattern on the third fin pattern. The formation of the gate electrode includes the steps of: forming a trench by removing the dummy gate electrode; and forming a conductive material in the trench after forming the third fin pattern.
In some embodiments, the forming of the first fin pattern includes: a field insulating film is formed on the substrate, the field insulating film directly contacting a lower portion of the first fin pattern and not directly contacting an upper portion of the first fin pattern.
In some embodiments, the forming of the second fin pattern includes modifying a profile of sidewalls of the first fin pattern to form the second fin pattern, and the forming of the third fin pattern includes modifying a profile of sidewalls of the second fin pattern to form the third fin pattern.
In some embodiments, the method may further comprise the step of: recesses are formed in the second fin pattern by etching both sides of the dummy gate electrode, and then source/drains are formed in the respective recesses before forming the third fin pattern.
According to another aspect of the inventive concept, there is provided a method for manufacturing a semiconductor device, the method including: forming a first fin pattern including an upper portion protruding above an upper surface of a field insulating film and a lower portion surrounded by the field insulating film; etching the corner part of the first fin-shaped pattern, at which the upper surface of the first fin-shaped pattern is connected with the side wall, so as to round the corner part of the first fin-shaped pattern; forming a second fin pattern by modifying a profile of sidewalls of the first fin pattern including the rounded corner portions; forming a dummy gate electrode crossing the second fin pattern on the second fin pattern; and forming a third fin pattern by modifying a profile of sidewalls of the second fin pattern vertically overlapping the dummy gate electrode.
In some embodiments, the step of forming the second fin pattern comprises: forming a first oxide film along a contour of an upper portion of the first fin pattern including rounded corner portions by oxidizing a portion of the upper portion of the first fin pattern; and removing the first oxide film.
In some embodiments, the step of forming the third fin pattern comprises: forming a second oxide film along a contour of an upper portion of the second fin-shaped pattern by oxidizing a portion of the upper portion of the second fin-shaped pattern before forming the dummy gate electrode; and removing at least a portion of the second oxide film after forming the dummy gate electrode to form a third fin pattern.
In some embodiments, the method may further comprise the step of: before removing at least a part of the second oxide film, a trench exposing the part of the second oxide film is formed by removing the dummy gate electrode.
In some embodiments, the method may further comprise the step of: forming a third oxide film along the profile of the third fin-shaped pattern exposed through the trench; and forming a gate electrode in the trench on the third oxide film.
In some embodiments, a width of an upper portion of the second fin pattern at a first height above the upper surface of the substrate is less than a width of an upper portion of the first fin pattern at the first height and greater than a width of an upper portion of the third fin pattern at the first height.
According to still another aspect of the inventive concept, there is provided a method for manufacturing a semiconductor device, the method including: forming a first fin-shaped pattern having an upper portion and a lower portion on a substrate; forming a first oxide film along a contour of the first fin-shaped pattern by oxidizing a portion of the first fin-shaped pattern; forming a second fin-shaped pattern by removing the first oxide film; forming a second oxide film along the contour of the second fin-shaped pattern by oxidizing a portion of the second fin-shaped pattern; and forming a first gate electrode crossing the second fin pattern on the second oxide film.
In some embodiments, the step of forming the first fin pattern comprises: a field insulating film is formed on the substrate, the field insulating film directly contacting a lower portion of the first fin pattern and not directly contacting an upper portion of the first fin pattern.
In some embodiments, a first oxide film is formed along a contour of an upper portion of the first fin pattern, and a second oxide film is formed along a contour of an upper portion of the second fin pattern.
In some embodiments, the method may further comprise the step of: before forming the first oxide film, etching the corner part of the first fin-shaped pattern where the upper surface of the first fin-shaped pattern is connected with the side wall so as to round the corner part of the first fin-shaped pattern.
In some embodiments, the step of forming the first fin pattern comprises: forming a fourth fin-shaped pattern having an upper portion and a lower portion on the substrate; forming a field insulating film directly contacting a lower portion of the fourth fin pattern and not directly contacting an upper portion of the fourth fin pattern; forming a fourth oxide film along a contour of the fourth fin-shaped pattern by oxidizing a portion of the fourth fin-shaped pattern after forming the field insulating film; and removing the fourth oxide film.
In some embodiments, a fourth oxide film is formed along a contour of an upper portion of the fourth fin pattern.
In some embodiments, the method may further comprise the step of: before forming the fourth oxide film, a corner portion where the upper surface of the fourth fin pattern and the sidewall meet is etched to round the corner portion of the fourth fin pattern.
In some embodiments, a width of an upper portion of the first fin pattern at a first height above the upper surface of the substrate is less than a width of an upper portion of the fourth fin pattern at the first height and greater than a width of an upper portion of the second fin pattern at the first height.
In some embodiments, the method may further comprise the step of: forming a trench exposing the second oxide film by removing the first gate electrode; and forming a conductive material filling the trench.
In some embodiments, the method may further comprise the step of: forming a third fin pattern by removing the second oxide film exposed by the trench; and forming a third oxide film along the profile of the third fin-shaped pattern exposed by the trench.
In some embodiments, forming the third oxide film includes the steps of: a portion of the third fin pattern is oxidized.
According to still another aspect of the inventive concept, there is provided a method for manufacturing a semiconductor device, the method including: forming a first fin-shaped pattern including an upper portion and a lower portion in a first region on a substrate, and forming a second fin-shaped pattern including an upper portion and a lower portion in a second region on the substrate; forming a third fin pattern by removing a portion of an upper portion of the first fin pattern; forming a fourth fin pattern by removing a portion of an upper portion of the second fin pattern; forming a first oxide film along a contour of the third fin-shaped pattern by oxidizing a portion of an upper portion of the third fin-shaped pattern; forming a second oxide film along the contour of the fourth fin-shaped pattern by oxidizing a portion of the upper portion of the fourth fin-shaped pattern; forming a mask pattern on the first region of the substrate, wherein the mask pattern covers the third fin-shaped pattern with the first oxide film thereon; forming a fifth fin pattern by removing the second oxide film; forming a third oxide film along a contour of the fifth fin pattern by oxidizing a portion of an upper portion of the fifth fin pattern; removing the mask pattern, and then forming a first dummy gate electrode crossing the third fin pattern on the first oxide film and forming a second dummy gate electrode crossing the fifth fin pattern on the third oxide film; and forming a sixth fin pattern by removing at least a portion of the first oxide film and a seventh fin pattern by removing at least a portion of the third oxide film after forming the first dummy gate electrode and the second dummy gate electrode.
In some embodiments, the step of forming the third fin pattern comprises: forming a fourth oxide film along the contour of the upper part of the first fin-shaped pattern; and subsequently removing the fourth oxide film, and wherein the step of forming the fourth fin pattern comprises: forming a fifth oxide film along the contour of the upper part of the second fin-shaped pattern; and subsequently removing the fifth oxide film.
In some embodiments, the first fin pattern includes sidewalls, an upper surface, and corner portions at which the sidewalls of the first fin pattern meet the upper surface, and the second fin pattern includes sidewalls, an upper surface, and corner portions at which the sidewalls of the second fin pattern meet the upper surface. The method may further comprise the steps of: before forming the third fin-shaped pattern and the fourth fin-shaped pattern, corner portions of the first fin-shaped pattern and corner portions of the second fin-shaped pattern are rounded.
In some embodiments, the method may further comprise the step of: a field insulating film is formed on the substrate before rounding corner portions of the first fin-shaped pattern and corner portions of the second fin-shaped pattern. An upper portion of the first fin pattern and an upper portion of the second fin pattern protrude above an upper surface of the field insulating film.
In some embodiments, the step of forming the sixth fin pattern and the seventh fin pattern includes: forming a first trench and a second trench exposing each of the first oxide film and the third oxide film by removing the first dummy gate electrode and the second dummy gate electrode; and removing the first oxide film and the third oxide film exposed through the first trench and the second trench, respectively.
In some embodiments, the method may further comprise the step of: forming a fourth oxide film and a fifth oxide film along the contour of the upper part of the sixth fin-shaped pattern and the contour of the upper part of the seventh fin-shaped pattern respectively; and forming a first gate electrode filling the first trench on the fourth oxide film and a second gate electrode filling the second trench on the fifth oxide film.
According to still another aspect of the inventive concept, there is provided a method for manufacturing a semiconductor device, the method including: forming a first fin pattern and a field insulating film on a substrate, the field insulating film covering a lower portion of the first fin pattern and an upper portion of the first fin pattern protruding above the field insulating film; converting an outer portion of an upper portion of the first fin pattern into a first oxide film; forming a second fin-shaped pattern by removing the first oxide film; converting an outer portion of an upper portion of the second fin pattern exposed through the field insulating film into a second oxide film; and forming a third fin pattern by removing at least a portion of the second oxide film. A width of an upper portion of the second fin pattern at a first height above the upper surface of the substrate is less than a width of an upper portion of the first fin pattern at the first height and greater than a width of an upper portion of the third fin pattern at the first height, and a second height of the second fin pattern above the upper surface of the substrate is less than the first height of the first fin pattern above the upper surface of the substrate and greater than a third height of the third fin pattern above the upper surface of the substrate.
In some embodiments, the third fin pattern may extend in the first direction, and the method may further include: an electrode structure extending in a second direction crossing the first direction is formed on the substrate.
In some embodiments, a width of a lower portion of the third fin pattern may be greater than a width of an upper portion of the third fin pattern and may be equal to a width of a lower portion of the second fin pattern.
In some embodiments, the method may further comprise the step of: a dummy gate electrode is formed to intersect the second fin pattern, and then spacers are formed on sidewalls of the dummy gate electrode and the second oxide film. In the embodiment, the step of removing at least a part of the second oxide film may include: the portion of the second oxide film exposed through the spacer is removed.
In some embodiments, the method may further include rounding a corner portion of at least one of the first to third fin patterns.
Drawings
The above and other aspects and features of the present inventive concept will become more apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings, wherein:
fig. 1A to 14C are intermediate-stage diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the inventive concept;
fig. 15 to 17B are intermediate-stage diagrams illustrating a method for manufacturing a semiconductor device according to another embodiment of the inventive concept;
fig. 18 to 30 are intermediate-stage diagrams illustrating a method for manufacturing a semiconductor device according to still another embodiment of the inventive concept;
fig. 31 is a block diagram of a memory card including a semiconductor device manufactured using a manufacturing method according to an embodiment of the inventive concept;
fig. 32 is a block diagram of an information processing system including a semiconductor device manufactured by a manufacturing method according to an embodiment of the inventive concept; and
fig. 33 is a block diagram of an electronic device including a semiconductor device manufactured using a manufacturing method according to an embodiment of the inventive concept.
Detailed Description
The inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like reference numerals refer to like elements throughout the specification and drawings. In the drawings, the thickness of some layers and regions may be exaggerated for clarity.
It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element or component discussed below could be termed a second element or component without departing from the teachings of the present inventive concept.
The use of the terms "a" and "an" and "the" and similar referents in the context of describing the concepts of the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. It will be understood that the terms "comprising," "having," "including," and "containing" are open-ended terms (i.e., meaning "including, but not limited to,") unless otherwise noted.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It should be noted that the use of any and all examples, or exemplary terminology provided herein is intended merely to better illuminate the inventive concept and does not pose a limitation on the scope of the inventive concept unless otherwise claimed.
A method for manufacturing a semiconductor device according to an embodiment of the inventive concept will be described with reference to fig. 1A to 14C, which illustrate intermediate structures formed in the method for manufacturing a semiconductor device.
For example, fig. 1B is a sectional view taken along line a-a of fig. 1A, and fig. 3B is a sectional view taken along line a-a of fig. 3A. Fig. 8B is a sectional view taken along line a-a of fig. 8A, and fig. 9B is a sectional view taken along line B-B of fig. 9A. Fig. 10B and 11B are sectional views taken along line B-B of fig. 10A and 11A, respectively. Fig. 12B and 12C are sectional views taken along line a-a and line B-B of fig. 12A, respectively, and fig. 13B and 13C are sectional views taken along line a-a and line B-B of fig. 13A, respectively. Fig. 14B and 14C are sectional views taken along line a-a and line B-B of fig. 14A, respectively.
Referring to fig. 1A and 1B, a first mask pattern 2001 extending in a first direction X1 is formed on a substrate 100.
For example, the substrate 100 may be a silicon substrate, bulk silicon, or SOI (silicon on insulator). In other embodiments, the substrate 100 may include another semiconductor such as germanium, or may be a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor, for example. The substrate 100 may also be an element in which an epitaxial layer is formed on a base substrate.
Taking a group IV-IV compound semiconductor as an example, the substrate 100 may be a binary compound or a ternary compound containing at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these compounds with a group IV element.
Taking a III-V compound semiconductor As an example, the substrate 100 may be a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) As group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) As group V elements.
In the method for manufacturing a semiconductor device according to an embodiment of the inventive concept, the substrate 100 will be described as a silicon substrate.
For example, the first mask pattern 2001 may include silicon dioxide, silicon nitride, silicon oxynitride, a metal film, photoresist, SOG (spin on glass), or SOH (spin on hard mask), but is not limited thereto.
Referring to fig. 2, a portion of the substrate 100 may be etched using the first mask pattern 2001 as an etch mask. One or more first trenches 2101 may be formed in the substrate 100 by etching a portion of the substrate 100 not covered by the first mask pattern 2001.
By etching the substrate 100 in the above manner, the first fin pattern 110 may be formed on the substrate 100. Since the first fin-shaped pattern 110 is formed using the first mask pattern 2001 as an etching mask, the first fin-shaped pattern 110 may extend in the first direction X1 like the first mask pattern 2001.
The first mask patterns 2001 may remain on the corresponding first fin patterns 110.
Referring to fig. 3A and 3B, a preliminary field insulating film 105P is formed on the substrate to fill the first trench 2101.
For example, the preliminary field insulating film 105P may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. For example, the preliminary field insulating film 105P may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or a combination thereof.
The upper surface of the first fin pattern 110 and the upper surface of the preliminary field insulating film 105P may be located on the same plane by a planarization process such as, for example, a chemical mechanical polishing process. The first mask pattern 2001 may be removed by a planarization process, but embodiments of the inventive concept are not limited thereto. For example, in other embodiments, the first mask pattern 2001 may be removed before forming the preliminary field insulating film 105P or may be removed after performing the recess process described below with reference to fig. 4.
Referring to fig. 4, the upper portion of the first fin pattern 110 may be exposed by recessing the upper portion of the preliminary field insulating film 105P to form the field insulating film 105.
The recessing process may be a selective etch process. By removing a portion of the preliminary field insulating film 105P, the first fin pattern 110 may protrude upward from the upper surface of the field insulating film 105.
Each of the first fin patterns 110 may include a lower portion 112 and an upper portion 111 above the lower portion 112. The lower portion 112 of each first fin pattern may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 111 of each first fin pattern may not directly contact the field insulating film 105. In other words, the portion of each first fin pattern 110 protruding upward from the upper surface of the field insulating film 105 includes the upper portion 111 of each first fin pattern 110.
It should also be understood that, in other embodiments, the upper portion 111 of the first fin pattern 110 may be formed by an epitaxial process, which is opposite to the recess process. In the embodiment, after the preliminary field insulating film 105P of fig. 3A and 3B is formed, an epitaxial process is performed using the exposed upper surface of the first fin-shaped pattern 110 as a seed, so that the upper portion 111 of the first fin-shaped pattern 110 protruding upward from the upper surface of the preliminary field insulating film 105P may be formed. In the embodiment, the preliminary field insulating film 105P may have a flat upper surface.
The first fin pattern 110 may also be doped to adjust the threshold voltage of the transistor it forms. In the case where the semiconductor device is an NMOS fin-shaped transistor, the impurity ions doped in the first fin-shaped pattern 110 may be boron (B), and in the case of a PMOS fin-shaped transistor, the impurity ions doped in the first fin-shaped pattern may be phosphorus (P) or arsenic (As).
A doping step for adjusting a threshold voltage may be performed after exposing the upper portion 111 of the first fin pattern 110.
The height of the upper portion 111 of each first fin pattern 110 protruding above the upper surface of the field insulating film 105 may be 2H. The width of the first fin pattern 110 at a point half the height of the upper portion 111 may be W1. In other words, at a height H1 above the lowermost portion of the first fin pattern 110 or above the upper surface of the substrate 100, the width of the first fin pattern 110 in the second direction Y1 in fig. 3A may be the first width W1.
The first fin pattern 110 includes an upper surface 110U, sidewalls 110S, and corner portions 110C where the upper surface 110U and the sidewalls 110S meet. In fig. 4, the corner portion 110C of the first fin-shaped pattern may have an angular shape.
Referring to fig. 5, the corner portions 110C of the first fin pattern may be rounded by etching the first fin pattern 110. That is, the corner portions 110C of the first fin pattern may be etched to have a circular shape.
At a height H1 above the lowermost portion of the first fin pattern 110, the corrected first width of the first fin pattern 110 having rounded corner portions may be W11.
In fig. 4 and 5, at a height H1 above the lowermost portion of the first fin pattern 110, the width W1 of the first fin pattern 110 before corner rounding has been shown to be substantially equal to the width W11 of the first fin pattern 110 after corner rounding, but embodiments of the inventive concept are not limited thereto.
That is, it is desirable that the upper portion 111 of the first fin pattern may be partially etched while rounding the corner portions 110C of the first fin pattern. In this case, the width W1 of the first fin pattern 110 before corner rounding may be larger than the width W11 of the first fin pattern after corner rounding 110.
In the discussion that follows, the width W1 of the first fin pattern 110 before rounding is the same as the width W11 of the first fin pattern 110 after rounding.
Referring to fig. 6, a first oxide film 115 may be formed along the profile of the first fin pattern 110.
The first oxide film 115 may be formed along the contour of the upper portion 111 of the first fin pattern 110 protruding above the upper surface of the field insulating film 105. The first oxide film 115 may be formed along the profile of the upper portion 111 of the first fin pattern including rounded corner portions.
The first oxide film 115 may be formed by oxidizing the upper portion 111 of the first fin pattern 110 having rounded corner portions.
For example, the first oxide film 115 may be formed using chemical oxidation, ultraviolet oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like. When the first oxide film 115 is formed using chemical vapor deposition, atomic layer deposition, or the like, a portion of the first fin-shaped pattern 110 may be oxidized.
For example, the first oxide film 115 may be formed to cure surface defects such as charge trapping sites of the first fin pattern 110, which may be generated during the formation of the first fin pattern 110.
Referring to fig. 7, the second fin pattern 120 protruding over the upper surface of the field insulating film 105 may be formed by removing the first oxide film 115.
The first oxide film 115 may be removed using an etching process or the like. For example, the first oxide film 115 may be removed using a Chemical Oxide Removal (COR), Siconi, or descum.
The second fin pattern 120 may include a lower portion 122 and an upper portion 121 above the lower portion 122. The lower portion 122 of the second fin pattern 120 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 121 of the second fin pattern 120 may not directly contact the field insulating film 105.
When removing a portion of the field insulating film 105 is not considered during the removal of the first oxide film 115, the lower portion 122 of the second fin pattern 120 may be substantially the same as the lower portion 112 of the first fin pattern 110.
At a height H1 above a lowermost portion of the second fin pattern 120, a width of the second fin pattern 120 may be a second width W2. The width W2 of the second fin pattern 120 may be narrower than the width W1 of the first fin pattern 110 before rounding and the width W11 of the first fin pattern 110 after rounding.
In other words, the width W2 of the upper portion 121 of the second fin pattern 120 may be narrower than the width W1 of the upper portion 111 of the first fin pattern 110 before rounding and the width W11 of the upper portion 111 of the first fin pattern 110 after rounding.
Referring to fig. 6 and 7, the second fin pattern 120 may be formed by removing a portion of the upper portion 111 of the first fin pattern 110.
In other words, during the formation and removal of the first oxide film 115, the profile of the sidewalls 110S of the first fin pattern 110 changes. Accordingly, the second fin pattern 120 may be formed by modifying the profile of the sidewalls 110S of the first fin pattern including rounded corners.
The sidewalls 120S of the second fin pattern 120 may include a first inflection point 120P.
Referring to fig. 8A and 8B, a second oxide film 125 may be formed along the contour of the upper portion 121 of the second fin pattern 120 protruding above the upper surface of the field insulating film 105.
The second oxide film 125 may be formed by oxidizing a portion of the second fin pattern 120. For example, the second oxide film 125 may be formed by oxidizing a portion of the upper portion 121 of the second fin pattern 120.
For example, the second oxide film 125 can be formed using chemical oxidation, ultraviolet oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, or atomic layer deposition.
Next, a first dummy gate electrode 205 may be formed. Specifically, a first dummy gate electrode layer may be formed, and a mask pattern 2002 may be formed on the first dummy gate electrode layer. The first dummy gate electrode layer may then be etched using mask 2002 as an etch mask to form first dummy gate electrode 205. The first dummy gate electrode 205 may extend in the second direction Y1 to intersect the second fin pattern 120.
The first dummy gate electrode 205 is formed on the second fin pattern 120 and on the second oxide film 125 formed along the contour of the upper portion 121 of the second fin pattern 120.
For example, the first dummy gate electrode 205 may include polysilicon, amorphous silicon, or the like. For example, the second mask pattern 2002 may include silicon dioxide, silicon nitride, silicon oxynitride, or the like.
In fig. 8A and 8B, the second oxide film 125 is illustrated as being exposed at both sides of the first dummy gate electrode 205, but embodiments of the inventive concept are not limited thereto. For example, in other embodiments, the second oxide film 125 that does not vertically overlap the first dummy gate electrode 205 may be removed during an etching process for forming the first dummy gate electrode 205. Here, a first structure formed on an underlying substrate "vertically overlaps" a second structure formed on the substrate if both the first structure and the second structure are bisected simultaneously by a line perpendicular to a plane defined through the top surface of the substrate.
In the method for manufacturing a semiconductor device according to an embodiment of the inventive concept, the first dummy gate electrode 205 is described as a replacement gate electrode, but is not limited thereto.
In other words, it is needless to say that the gate electrode can be formed using a material to be used as a gate electrode of the transistor instead of the dummy gate electrode. It is also understood that a high dielectric constant gate insulating film may be formed between the second oxide film 125 and the gate electrode.
Referring to fig. 9A and 9B, first gate spacers 210 may be formed on sidewalls of the first dummy gate electrode 205.
After forming the insulating film covering the first dummy gate electrode 205 and the second fin pattern 120, the first gate spacer 210 may be formed by etching the insulating film. For example, the first gate spacer 210 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO)2) At least one of silicon oxycarbonitride (SiOCN), or a combination thereof.
Next, a recess 155 may be formed in the second fin pattern 120 by removing portions of the second fin pattern 120 exposed at both sides of the first dummy gate electrode 205. The upper surface of the second fin pattern 120 exposed through the field insulating film 105 may be disposed on the same plane as that of the upper surface of the field insulating film 105, but embodiments of the inventive concept are not limited thereto.
Referring to fig. 10A and 10B, the source/drain 150 may be formed on the second fin pattern 120 located at each side of the first dummy gate electrode 205.
Source/drains 150 may be formed by filling recesses 155. Source/drains 150 may be formed by epitaxial processing. For example, source/drain 150 may be a raised source/drain.
When the semiconductor device is a PMOS transistor, the source/drains 150 may comprise a compressively stressed material. For example, the compressive stress material may be a material having a lattice constant greater than Si, and may be, for example, SiGe. The compressive stress material may increase the mobility of carriers in the channel region by applying a compressive stress to the second fin pattern 120 (and thus to the third fin pattern 130).
Alternatively, when the semiconductor device is an NMOS transistor, the source/drain 150 may include a tensile stress material. For example, when the second fin pattern 120 is silicon, the source/drain 150 may be a material (e.g., SiC) having a lattice constant smaller than that of silicon. For example, the tensile stress material may increase the mobility of carriers in the channel region by applying tensile stress to the second fin pattern 120 (and thus to the third fin pattern 130).
In fig. 10A, although the respective source/drains 150 adjacent to each other in the second direction Y1 are illustrated as being spaced apart from each other, not contacting each other, this is merely for convenience of explanation, and embodiments of the present invention are not limited thereto. It is needless to say that the source/drains 150 adjacent to each other in the second direction Y1 may contact each other.
Referring to fig. 11A and 11B, an etch stop film 170 is formed to cover the source/drain 150 and the first dummy gate electrode 205. An interlayer insulating film 180 covering the source/drain 150 and the first dummy gate electrode 205 may be formed on the etch stop film 170.
Next, a planarization operation may be performed on the interlayer insulating film 180 until the upper surface of the first dummy gate electrode 205 is exposed. The second mask pattern 2002 may be removed by the planarization operation.
For example, the etch stop film 170 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO)2) At least one of silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or combinations thereof.
The etch stop film 170 may be formed by, for example, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), and/or combinations thereof.
For example, the interlayer insulating film 180 may include one of silicon oxide, silicon nitride, silicon oxynitride, TEOS (tetraethylorthosilicate), FOX (flowable oxide), tosz (tonen silazen), USG (undoped silica glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethylorthosilicate), or a low dielectric constant material. For example, low dielectric constant materials may include FSG (fluorosilicate glass), CDO (carbon doped silicon oxide), xerogels, aerogels, amorphous carbon fluorides, OSG (organosilicate glass), parylene, BCB (bis benzocyclobutene), SiLK, polyimides, porous polymer materials, and the like.
For example, the interlayer insulating film 180 may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), coating, or a combination thereof.
Referring to fig. 12A to 12C, a second trench 2102 extending in the second direction Y1 may be formed by removing the first dummy gate electrode 205.
The side surfaces of the second trench 2102 may be defined by sidewalls of the first gate spacer 210.
As the second trench 2102 is formed, the field insulating film 105 is exposed, and the second oxide film 125 formed along the contour of the upper portion 121 of the second fin pattern 120 may be exposed.
Referring to fig. 13A to 13C, a third fin pattern 130 protruding above the upper surface of the field insulating film 105 is formed by removing the second oxide film 125.
Specifically, the third fin pattern 130 is formed by removing a portion of the second oxide film 125 exposed through the second trench 2102. The remaining portion of the second oxide film 125 under the first gate spacer 210 may remain. That is, the third fin pattern 130 may include a remaining portion of the second oxide film 125 under the first gate spacer 210.
For example, the second oxide film 125 may be removed using an etching process or the like. For example, the second oxide film 125 may be removed using a chemical oxide removal process (COR), Siconi, or descumming, but the removal technique is not limited thereto.
The third fin pattern 130 may include a lower portion 132 and an upper portion 131 above the lower portion 132. The lower portion 132 of the third fin pattern 130 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 131 of the third fin pattern 130 may not directly contact the field insulating film 105.
When the disappearance of the field insulating film 105 is not considered during the removal of the second oxide film 125, the lower portion 132 of the third fin pattern 130 may be substantially the same as the lower portion 122 of the second fin pattern 120.
The width of the third fin pattern 130 at a distance H1 above the lowermost portion of the third fin pattern 130 may be a third width W3. The width W3 of the third fin pattern 130 may be narrower than the width W2 of the second fin pattern 120, and may be narrower than the width W1 of the first fin pattern 110 before rounding and the width W11 of the first fin pattern 110 after rounding.
In other words, the width W3 of the upper portion 131 of the third fin pattern 130 may be narrower than the width W1 of the upper portion 111 of the first fin pattern 110 before rounding, the width W11 of the upper portion 111 of the first fin pattern 110 after rounding, and the width W2 of the upper portion 121 of the second fin pattern 120.
Referring to fig. 8A, 8B, and 13A to 13C, the third fin pattern 130 may be formed by removing a portion of the upper portion 121 of the second fin pattern 120.
In other words, the profile of the sidewalls 120S of the second fin pattern 120 is changed during the formation and removal of the second oxide film 125. Accordingly, the third fin pattern 130 may be formed by modifying the profile of the sidewalls 120S of the second fin pattern 120. The third fin pattern 130 may be formed by modifying the profile of the sidewalls 120S of the second fin pattern 120 vertically overlapping the first dummy gate electrode 205.
The sidewalls 130S of the third fin pattern 130 may include a second inflection point 130P.
Referring to fig. 14A to 14C, the third oxide film 135 may be formed along the profile of the third fin pattern 130 exposed through the second trench 2102. The third oxide film 135 may be formed along the contour of the upper portion 131 of the third fin pattern 130 protruding above the upper surface of the field insulating film 105.
The third oxide film 135 may be formed by oxidizing the exposed portion of the third fin pattern 130. For example, the third oxide film 135 may be formed by oxidizing a portion of the upper portion 131 of the third fin pattern 130.
For example, the third oxide film 135 can be formed by chemical oxidation, UV oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like.
Next, the first high-permittivity insulating film 215 may be formed along the side walls and the bottom surface of the second trench 2102. The first high-permittivity insulating film 215 may be formed along the outline of the field insulating film 105 and the portion of the third fin-shaped pattern 130 protruding above the field insulating film 105. The first high-permittivity insulating film 215 may be formed on the third oxide film 135.
For example, the first high-dielectric-constant insulating film 215 may include one or more of silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.
For example, the first high-dielectric-constant insulating film 215 may be formed by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or a combination thereof.
The first gate electrode 220 may be formed by filling the second trench 2102 with a conductive material. The first gate electrode 220 may extend in the second direction Y1 to cross the third fin pattern 130. The first gate electrode 220 may be formed on the third fin pattern 130 with the first high dielectric constant insulating film 215 interposed between the first gate electrode 220 and the third fin pattern 130.
The first gate electrode 220 may include metal layers 221 and 222. As shown, the first gate electrode 220 may be formed by a lamination of two or more metal layers 221, 222. The first metal layer 221 may be used to adjust a work function, and the second metal layer 222 may be used to fill a space formed by the first metal layer 221.
For example, the first metal layer 221 may include at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, or a combination thereof. For example, the second metal layer 222 may include at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, or a metal alloy.
Fig. 15 to 17B are intermediate-stage diagrams illustrating a method for manufacturing a semiconductor device according to another embodiment of the inventive concept. For ease of description, the following discussion will focus primarily on the differences between the embodiment of fig. 1-14C and the embodiment of fig. 15-17B.
For ease of reference, fig. 17B is a cross-sectional view taken along line a-a of fig. 17A. Fig. 15 shows a process that may be performed after the processes of fig. 1 to 7.
Referring to fig. 15, a second oxide film 125 may be formed along the profile of the exposed portion of the second fin pattern 120. The second oxide film 125 may be formed by oxidizing the exposed portion of the second fin pattern 120.
The second oxide film 125 may be formed along the contour of the upper portion 121 of the second fin pattern 120 protruding above the upper surface of the field insulating film 105.
For example, the second oxide film 125 may be formed by chemical oxidation, UV oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, or atomic layer deposition.
Referring to fig. 16, the second oxide film 125 may be removed to form a fourth fin pattern 140 protruding above the upper surface of the field insulating film 105.
The second oxide film 125 may be removed using an etching process or the like. For example, the second oxide film 125 may be removed using Chemical Oxide Removal (COR), Siconi, or descumming.
The fourth fin pattern 140 may include a lower portion 142 and an upper portion 141 above the lower portion 142. The lower portion 142 of the fourth fin pattern 140 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 141 of the fourth fin pattern 140 may not directly contact the field insulating film 105.
The width of the fourth fin pattern 140 at a height H1 above the lowermost portion of the fourth fin pattern 140 may be a fourth width W4. The width W4 of the fourth fin pattern 140 may be narrower than the width W2 of the second fin pattern 120 and the width W11 of the first fin pattern 110 after rounding.
In other words, the width W4 of the upper portion 141 of the fourth fin pattern 140 may be narrower than the width W2 of the second fin pattern 120 and the width W11 of the first fin pattern 110 after rounding.
Referring to fig. 15 and 16, the fourth fin pattern 140 may be formed by removing a portion of the upper portion 121 of the second fin pattern 120.
In other words, the profile of the sidewalls 120S of the second fin pattern 120 is changed during the formation and removal of the second oxide film 125. Accordingly, the fourth fin pattern 140 may be formed by modifying the profile of the sidewalls 120S of the second fin pattern 120.
The sidewalls of the fourth fin pattern 140S may include a third inflection point 140P.
Referring to fig. 17A and 17B, a fourth oxide film 145 may be formed along the profile of the fourth fin pattern 140. The fourth oxide film 145 may be formed along the contour of the upper portion 141 of the fourth fin pattern 140 protruding above the upper surface of the field insulating film 105.
The fourth oxide film 145 may be formed by oxidizing a portion of the upper portion 141 of the fourth fin pattern 140.
For example, the fourth oxide film 145 may be formed by chemical oxidation, UV oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like.
Next, a first dummy gate electrode 205 may be formed. Specifically, a first dummy gate electrode layer may be formed, and a mask pattern 2002 may be formed on the first dummy gate electrode layer. The first dummy gate electrode layer may then be etched using mask 2002 as an etch mask to form first dummy gate electrode 205. The first dummy gate electrode 205 may extend in the second direction Y1 to intersect the fourth fin pattern 140.
The first dummy gate electrode 205 is formed on the fourth fin pattern 140. The first dummy gate electrode 205 may be formed on the fourth oxide film 145 formed along the contour of the upper portion 141 of the fourth fin pattern 140.
In fig. 17A and 17B, the fourth oxide film 145 is illustrated as being exposed at both sides of the first dummy gate electrode 205, but embodiments of the inventive concept are not limited thereto. For example, in other embodiments, those portions of the fourth oxide film 145 that do not vertically overlap the first dummy gate electrode 205 may be removed in the etching process for forming the first dummy gate electrode 205.
Next, the first gate electrode 220 may be formed by the process described above with reference to fig. 9A to 14C. In these processes, the third fin pattern 130 may be formed by removing the fourth oxide film 145 formed along the profile of the fourth fin pattern 140.
Fig. 18 to 30 are intermediate-stage diagrams illustrating a method for manufacturing a semiconductor device according to still another embodiment of the inventive concept. For ease of description, the following discussion will focus primarily on differences from the embodiments described above with reference to fig. 1-14C.
For ease of reference, fig. 19 to 26 show the processing performed after fig. 18 in cross sections taken along the line a-a and the line C-C of fig. 18. Fig. 29 and 30 show the processing performed after fig. 28A in cross sections taken along the line a-a and the line C-C of fig. 28A. Fig. 27B is a sectional view taken along lines a-a and C-C of fig. 27A, and fig. 28B is a sectional view taken along lines a-a and C-C of fig. 28A.
Referring to fig. 18, a first mask pattern 2001 may be formed on a substrate 100. The first mask pattern 2001 may extend along the first direction X1 on the first region I, and may extend along the third direction X2 on the second region II.
The substrate 100 may include a first region I and a second region II. The first zone I and the second zone II may be zones spaced apart from each other, or may be zones connected to each other.
Referring to fig. 19, a first trench 2101 and a third trench 2103 may be formed in the substrate 100 by etching those portions of the substrate 100 not covered by the first mask pattern 2001. The first trench 2101 may be formed in the first region I, and the third trench 2103 may be formed in the second region II.
By etching a portion of the substrate 100, the first fin pattern 110 may be formed in the first region I of the substrate 100, and the fifth fin pattern 310 may be formed in the second region II of the substrate 100.
Since the fin pattern is formed using the first mask pattern 2001 as an etch mask, the first fin pattern 110 extends in the first direction X1, and the fifth fin pattern 310 extends in the third direction X2.
The first mask pattern 2001 may remain on the first fin pattern 110 and on the fifth fin pattern 310.
Referring to fig. 20, a field insulating film 105 may be formed on a substrate 100. A portion of the first fin pattern 110 and a portion of the fifth fin pattern 310 may protrude above the upper surface of the field insulating film 105.
The lower portion 112 of the first fin pattern 110 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 111 of the first fin pattern 110 may not directly contact the field insulating film 105.
The lower portion 312 of the fifth fin pattern 310 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 311 of the fifth fin pattern 310 may not directly contact the field insulating film 105.
The width of the first fin pattern 110 at a height H above the upper surface of the field insulating film 105 may be W1, and the width of the fifth fin pattern 310 may be W5. In other words, at a height H1 above a lowermost portion of the first fin pattern 110, the width of the first fin pattern 110 may be a first width W1, and at the same height H1, the width of the fifth fin pattern 310 may be a fifth width W5.
The fifth fin pattern 310 includes an upper surface 310U, sidewalls 310S, and corner portions 310C where the upper surface 310S meets the sidewalls 310C. As shown in fig. 20, the corner portion 310C may have an angular shape.
Referring to fig. 21, through an etching process, the first fin pattern 110 may be etched to round its corner portions 110C, and the fifth fin pattern 310 may be etched to round its corner portions 310C.
The corrected fifth width of the fifth fin pattern 310 having a rounded corner portion may be W51 at a height H1 above the lowermost portion of the fifth fin pattern 310.
In fig. 20 and 21, it has been described that the width W1 of the first fin pattern 110 before rounded corners is substantially the same as the width W11 of the first fin pattern 110 after rounded corners at a height H1 above the lowermost portion of the first fin pattern 110, and the width W5 of the fifth fin pattern 310 before rounded corners is substantially the same as the width W51 of the fifth fin pattern 310 after rounded corners at a height H1 above the lowermost portion of the fifth fin pattern 310, but it should be understood that the inventive concept is not limited thereto.
Referring to fig. 22, the first oxide film 115 may be formed along the profile of the first fin pattern 110, and the fifth oxide film 315 may be formed along the profile of the fifth fin pattern 310.
The fifth oxide film 315 may be formed along the contour of the upper portion 311 of the fifth fin pattern 310 protruding above the upper surface of the field insulating film 105 and including rounded corner portions.
The first oxide film 115 may be formed by oxidizing a portion of the first fin pattern 110, and the fifth oxide film 315 may be formed by oxidizing a portion of the fifth fin pattern 310.
For example, the first oxide film 115 and the fifth oxide film 315 may be formed by chemical oxidation, UV oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, atomic layer deposition, or the like.
Referring to fig. 23, the second fin pattern 120 may be formed in the first region I by removing the first oxide film 115, and the sixth fin pattern 320 may be formed in the second region II by removing the fifth oxide film 315.
The first oxide film 115 and the fifth oxide film 315 may be removed using an etching process. For example, the first oxide film 115 and the fifth oxide film 315 may be removed by chemical oxide film removal (COR), Siconi, or descumming.
The lower portion 322 of the sixth fin pattern 320 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 321 of the sixth fin pattern 320 may not directly contact the field insulating film 105.
The width of the sixth fin pattern 320 at a height H1 above the lowermost portion of the sixth fin pattern 320 may be a sixth width W6. The sixth width W6 of the sixth fin pattern 320 may be narrower than the fifth width W5 of the fifth fin pattern 310 before rounding and the width W51 of the fifth fin pattern 310 after rounding.
Referring to fig. 22 and 23, the second fin pattern 120 and the sixth fin pattern 320 may be formed by removing respective portions of the first fin pattern 110 and respective portions of the fifth fin pattern 310. Specifically, the second and sixth fin patterns 120 and 320 may be formed by removing respective portions of the upper portion 111 of the first fin pattern 110 and respective portions of the upper portion 311 of the fifth fin pattern 310.
In the process of forming and removing the first oxide film 115 and the fifth oxide film 315, the profiles of the sidewalls 110S of the first fin pattern 110 and the sidewalls 310S of the fifth fin pattern 310 are changed. Specifically, the sidewalls 320S of the sixth fin pattern 320 may include a fourth inflection point 320P.
Referring to fig. 24, the second oxide film 125 may be formed along the profile of the second fin pattern 120, and the sixth oxide film 325 may be formed along the profile of the sixth fin pattern 320. The second oxide film 125 and the sixth oxide film 325 may be formed along the contour of the upper portion 121 of the second fin pattern and the contour of the upper portion 321 of the sixth fin pattern, respectively, protruding above the upper surface of the field insulating film 105.
The second oxide film 125 may be formed by oxidizing a portion of the second fin pattern upper portion 121, and the sixth oxide film 325 may be formed by oxidizing a portion of the sixth fin pattern upper portion 321.
Next, a third mask pattern 2003 may be formed to cover the second fin pattern 120 on the first region I of the substrate 100. The second oxide film 125 is also covered with the third mask pattern 2003.
Since the third mask pattern 2003 is formed on the first region I, the sixth fin pattern 320 and the sixth oxide film 325 may be exposed through the third mask pattern 2003.
Referring to fig. 25, the sixth oxide film 325 may be removed by an etching process using the third mask pattern 2003 as an etching mask. The seventh fin pattern 330 may be formed on the second region II by removing the sixth oxide film 325. For example, the sixth oxide film 325 may be removed using Chemical Oxide Removal (COR), Siconi, or descumming.
The seventh fin pattern 330 may include a lower portion 332 and an upper portion 331 over the lower portion 332. The lower portion 332 of the seventh fin pattern 330 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 331 of the seventh fin pattern may not directly contact the field insulating film 105.
The width of the seventh fin pattern 330 at a height H1 above the lowermost portion 330 of the seventh fin pattern may be a seventh width W7. The width W7 of the seventh fin pattern 330 may be narrower than the sixth width W6 of the sixth fin pattern 320 and the width W51 of the fifth fin pattern 310 after rounding.
In other words, the width W7 of the upper portion 331 of the seventh fin pattern may be narrower than the width W6 of the sixth fin pattern 320 and the width W51 of the fifth fin pattern 310 after rounding.
Referring to fig. 24 and 25, a seventh fin pattern 330 may be formed by removing a portion of the sixth fin pattern 320. Specifically, the seventh fin pattern 330 may be formed by removing a portion of the upper portion 321 of the sixth fin pattern 330.
In the process of forming and removing the sixth oxide film 325, the profile of the sidewalls 320S of the sixth fin pattern 320 is changed. Accordingly, the seventh fin pattern 330 may be formed by modifying the profile of the sidewalls 320S of the sixth fin pattern 320.
The sidewalls 330S of the seventh fin pattern 330 may include a fifth inflection point 330P.
Referring to fig. 26, a seventh oxide film 335 may be formed along the profile of the seventh fin pattern 330. The seventh oxide film 335 may be formed along the contour of the upper portion 331 of the seventh fin pattern 330 protruding above the upper surface of the field insulating film 105.
The seventh oxide film 335 may be formed by oxidizing a portion of the seventh fin pattern 330. For example, the seventh oxide film 335 may be formed by oxidizing a portion of the upper portion 331 of the seventh fin pattern 330.
For example, the seventh oxide film 335 can be formed using chemical oxidation, UV oxidation, double plasma oxidation, thermal oxidation, chemical vapor deposition, or atomic layer deposition.
Next, the third mask pattern 2003 may be removed to expose the second fin pattern 120 having the second oxide film 125 thereon.
In fig. 24 to 26, the third mask pattern 2003 has been described as being formed after the second oxide film 125 and the sixth oxide film 325 are formed, but embodiments of the inventive concept are not limited thereto.
Unlike fig. 24 to 26, the third mask pattern 2003 may be formed without forming the second oxide film 125 and the sixth oxide film 325. In this case, after the seventh fin pattern 330 is formed while changing the profile of the sidewall 320S of the sixth fin pattern 320, the third mask pattern 2003 is removed. After removing the third mask pattern 2003, the second oxide film 125 and the seventh oxide film 335 may be formed along the outline of the second fin pattern 120 and the outline of the seventh fin pattern 330, respectively.
Referring to fig. 27A and 27B, a first dummy gate electrode 205 and a second dummy gate electrode 405 may be formed. Specifically, a first dummy gate electrode layer may be formed, and a mask pattern 2002 may be formed on the first dummy gate electrode layer. The first dummy gate electrode layer may then be etched using mask 2002 as an etch mask to form a first dummy gate electrode 205 on the first region I and a second dummy gate electrode 405 on the second region II. The first dummy gate electrode 205 may extend in the second direction Y1 to intersect the second fin pattern 120, and the second dummy gate electrode 405 may extend in the fourth direction Y2 to intersect the seventh fin pattern 330.
The first dummy gate electrode 205 may be formed on the second oxide film 125 formed along the contour of the upper portion 121 of the second fin pattern 120, and the second dummy gate electrode 405 may be formed on the seventh oxide film 335 formed along the contour of the upper portion 331 of the seventh fin pattern 330.
In fig. 27A and 27B, it is illustrated that the second oxide film 125 is exposed at both sides of the first dummy gate electrode 205 extending along the second direction Y1 and the seventh oxide film 335 is exposed at both sides of the second dummy gate electrode 405 extending along the fourth direction Y2, but embodiments of the inventive concept are not limited thereto.
Next, as described in fig. 9A to 11B, sources/drains are formed on both sides of the first dummy gate electrode 205 and both sides of the second dummy gate electrode 405, respectively. Then, the etching stopper film 170 and the interlayer insulating film 180 are formed.
Next, the interlayer insulating film 180 may be planarized until the upper surface of the first dummy gate electrode 205 and the upper surface of the second dummy gate electrode 405 are exposed.
Referring to fig. 28A and 28B, the second trench 2102 extending in the second direction Y1 may be formed by removing the first dummy gate electrode 205, and the fourth trench 2104 extending in the fourth direction Y2 may be formed by removing the second dummy gate electrode 405.
As the fourth trench 2104 is formed, the field insulating film 105 may be exposed, and the seventh oxide film 335 formed along the contour of the upper portion 331 of the seventh fin pattern 330 may be exposed. That is, the seventh oxide film 335 exposed by the fourth trench 2104 may be a portion vertically overlapping with the second dummy gate electrode 405.
Referring to fig. 29, the third and eighth fin patterns 130 and 340 are formed to protrude above the upper surface of the field insulating film 105 by removing the second and seventh oxide films 125 and 335.
Specifically, the third fin pattern 130 may be formed by removing the portion of the second oxide film 125 exposed by the second trench 2102, and the eighth fin pattern 340 may be formed by removing the portion of the seventh oxide film 335 exposed by the fourth trench 2104.
For example, the second oxide film 125 and the seventh oxide film 335 may be removed using Chemical Oxide Removal (COR), Siconi, or descumming.
The lower portion 342 of the eighth fin pattern 340 may directly contact the field insulating film 105, and may be surrounded by the field insulating film 105. The upper portion 341 of the eighth fin pattern may not directly contact the field insulating film 105.
The width of the eighth fin pattern 340 at a height H1 above the lowermost portion of the eighth fin pattern 340 may be an eighth width W8. The width W8 of the eighth fin pattern 340 may be narrower than the width W7 of the seventh fin pattern 330 and may be narrower than the width W6 of the sixth fin pattern 320.
The eighth fin pattern 340 may be formed by removing a portion of the upper portion 331 of the seventh fin pattern 330.
In the process of forming and removing the seventh oxide film 335, the profile of the sidewall 330S of the seventh fin pattern 330 is changed. Accordingly, the eighth fin pattern 340 may be formed by modifying the profile of the sidewalls 330S of the seventh fin pattern 330. The eighth fin pattern 340 may be formed by modifying the profile of the sidewalls 330S of the seventh fin pattern 330 vertically overlapping the second dummy gate electrode 405.
The sidewall 340S of the eighth fin pattern 340 may include a sixth inflection point 340P.
In the above process, the third fin pattern 130 is formed by two modification processes of the sidewall profile, and the eighth fin pattern 340 is formed by three modification processes of the sidewall profile.
As shown in the figure, the width and height of the fin-shaped pattern protruding above the upper surface of the field insulating film 105 are reduced each time the modification process of the sidewall profile is performed.
It is assumed that the width W1 of the first fin pattern 110 is substantially the same as the width W5 of the fifth fin pattern 310, and that the height of the upper portion 111 of the first fin pattern 110 is substantially the same as the height of the upper portion 311 of the fifth fin pattern 310.
At this time, since the number of modification processes for forming the sidewall profile of the third fin pattern 130 is different from the number of modification processes for forming the sidewall profile of the eighth fin pattern 340, the width W3 of the third fin pattern 130 may be different from the width W8 of the eighth fin pattern 340. For example, the width W3 of the third fin pattern 130 may be greater than the width W8 of the eighth fin pattern 340.
In addition, a height H2 of the upper portion 131 of the third fin pattern 130 may be different from a height H3 of the upper portion 341 of the eighth fin pattern 340. For example, the height H2 of the upper portion 131 of the third fin pattern 130 may be higher than the height H3 of the upper portion 341 of the eighth fin pattern 340.
Further, the slope 130S of the sidewalls of the upper portion 131 of the third fin pattern 130 at a portion higher than the second inflection point 130P may be different from the slope 340S of the sidewalls of the upper portion 341 of the eighth fin pattern 340 at a portion higher than the sixth inflection point 340P, wherein the slope is measured with respect to the upper surface of the substrate 100 in each case. For example, the slope 130S of the sidewall of the upper portion 131 of the third fin pattern 130 at a portion higher than the second inflection point 130P may be less than the slope 340S of the sidewall of the upper portion 341 of the eighth fin pattern 340 at a portion higher than the sixth inflection point 340P.
That is, the slope 340S of the sidewall of the upper portion 341 of the eighth fin pattern 340 of the portion higher than the sixth inflection point 340P may be almost vertical as compared to the slope 130S of the sidewall of the upper portion 131 of the third fin pattern 130 of the portion higher than the second inflection point 130P.
Referring to fig. 30, a third oxide film 135 may be formed along the profile of the third fin pattern 130 exposed through the second trench 2102. The eighth oxide film 345 may be formed along the profile of the eighth fin pattern 340 exposed through the fourth trench 2104.
Next, the first high-permittivity insulating film 215 is formed along the side walls and the bottom surface of the second trench 2102, and the second high-permittivity insulating film 415 is formed along the side walls and the bottom surface of the fourth trench 2104.
The second high-permittivity insulating film 415 may be formed along the contour of the field insulating film 105 and the contour of the portion of the eighth fin pattern 340 protruding above the field insulating film 105. The second high-permittivity insulating film 415 may be formed on the eighth oxide film 345.
Next, the first gate electrode 220 may be formed by filling the second trench 2102 with a conductive material, and the second gate electrode 420 may be formed by filling the fourth trench 2104 with a conductive material. The second gate electrode 420 includes layers 421 and 422.
The first gate electrode 220 may be formed on the third fin pattern 130 having the first high-permittivity insulation film 215 thereon, and the second gate electrode 420 may be formed on the eighth fin pattern 340 having the second high-permittivity insulation film 415 thereon.
Fig. 31 is a block diagram of a memory card including a semiconductor device manufactured according to an embodiment of the inventive concept.
Referring to fig. 31, a memory 1210 including one or more semiconductor devices manufactured according to an embodiment of the inventive concept may be included in a memory card 1200. The memory card 1200 may include a memory controller 1220 that controls data exchange between the host 1230 and the memory 1210. The SRAM 1221 can be used as an operation memory of the central processing unit 1222. The host interface 1223 may include a protocol for connecting the host 1230 to the memory card 1200 to exchange data. The error correction code 1224 may detect and correct errors in data read from the memory 1210. The memory interface 1225 may be coupled with the memory 1210. The central processing unit 1222 may perform overall control operations associated with data exchange of the memory controller 1220.
Fig. 32 is a block diagram of an information processing system including one or more semiconductor devices according to an embodiment of the inventive concept.
Referring to fig. 32, an information processing system 1300 may have a memory system 1310 including a semiconductor device manufactured according to an embodiment of the inventive concept. The information handling system 1300 may include a memory system 1310, a modem 1320, a central processing unit 1330, RAM 1340, and a user interface 1350 electrically connected to the system bus 1360. The memory system 1310 may include a memory 1311 and a memory controller 1312, and may have substantially the same configuration as that of the memory card 1200 shown in fig. 31. Data processed by the central processing unit 1330 or data received from an external device may be stored in the memory system 1310. The information processing system 1300 may be applied to memory cards, SSDs, camera image sensors, and various other chip sets. For example, the memory system 1310 may be configured to employ an SSD, and in this case, the information processing system 1300 can reliably and stably process large-capacity data.
Fig. 33 is a block diagram of an electronic device including one or more semiconductor devices according to an embodiment of the inventive concept.
Referring to fig. 33, an electronic device 1400 may include a semiconductor device manufactured according to an embodiment of the inventive concept. The electronic device 1400 may be used in a wireless communication device (e.g., a PDA, a notebook computer, a laptop computer, a web tablet, a wireless telephone, and/or a wireless digital music player) or various devices that send and receive information in a wireless communication environment.
Electronic device 1400 may include a controller 1410, an input/output device 1420, a memory 1430, and a wireless interface 1440. Here, the memory 1430 may include a semiconductor device manufactured according to an embodiment of the inventive concept. The controller 1410 may include a microprocessor, digital signal processor, or similar processor. The memory 1430 may be used to store commands (or user data) processed by the controller 1410. The wireless interface 1440 may be used to transmit and receive data over a wireless data network. The wireless interface 1440 may include an antenna and/or a wireless transceiver. For example, electronic device 1400 may employ third generation communication system protocols such as CDMA, GSM, NADC, E-TDMA, WCDMA and CDMA 2000.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the inventive concept being indicated by the appended claims rather than by the foregoing description.

Claims (18)

1. A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a first fin-shaped pattern including an upper portion and a lower portion on a substrate;
forming a field insulating film in direct contact with a lower portion of the first fin pattern and not in contact with an upper portion of the first fin pattern;
forming a second fin pattern by removing a portion of an upper portion of the first fin pattern, a sidewall of the second fin pattern including a first inflection point located above an upper surface of the field insulating film;
forming a dummy gate electrode crossing the second fin pattern on the second fin pattern; and
forming a third fin pattern by removing a portion of an upper portion of the second fin pattern after forming the dummy gate electrode, a sidewall of the third fin pattern including a second inflection point located above an upper surface of the field insulating film,
wherein a width of an upper portion of the second fin pattern at a first height above an upper surface of the substrate is less than a width of an upper portion of the first fin pattern at the first height and greater than a width of an upper portion of the third fin pattern at the first height.
2. The method of claim 1, wherein forming the second fin pattern comprises: and forming a first oxidation film along the outline of the upper part of the first fin-shaped pattern, and then removing the first oxidation film.
3. The method of claim 1, wherein forming the third fin pattern comprises:
forming a second oxide film along an outline of an upper portion of the second fin pattern before forming the dummy gate electrode, an
After the dummy gate electrode is formed, the second oxide film is removed.
4. The method of claim 3, further comprising the step of: and forming a third oxide film along the contour of the upper part of the third fin-shaped pattern by oxidizing a part of the upper part of the third fin-shaped pattern.
5. The method of claim 1, wherein the first fin pattern comprises sidewalls, an upper surface, and corner portions at which the sidewalls meet the upper surface, the method further comprising: rounding the corner portion by etching the first fin pattern before forming the second fin pattern.
6. The method of claim 1, wherein forming the first fin-shaped pattern comprises:
forming a fourth fin pattern comprising an upper portion and a lower portion on the substrate,
forming a field insulating film directly contacting a lower portion of the fourth fin pattern and not directly contacting an upper portion of the fourth fin pattern, an
Removing a portion of an upper portion of the fourth fin pattern after forming the field insulating film.
7. The method of claim 6, wherein forming the first fin-shaped pattern comprises:
forming an oxide film along a contour of an upper portion of the fourth fin pattern, an
And removing the oxide film.
8. The method of claim 6, wherein a width of an upper portion of the first fin pattern at the first height is less than a width of an upper portion of the fourth fin pattern at the first height.
9. The method of claim 1, further comprising the step of: forming recesses in the second fin pattern by etching both sides of the dummy gate electrode, and then forming source/drains in the corresponding recesses before forming the third fin pattern.
10. A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a first fin-shaped pattern having an upper portion and a lower portion on a substrate;
forming a first oxide film along the contour of the first fin-shaped pattern by oxidizing a part of the first fin-shaped pattern;
forming a second fin-shaped pattern by removing the first oxide film;
forming a second oxide film along the contour of the second fin-shaped pattern by oxidizing a part of the second fin-shaped pattern;
forming a first gate electrode crossing the second fin pattern on the second oxide film;
forming a trench exposing the second oxide film by removing the first gate electrode; and
and forming a third fin-shaped pattern by removing the second oxide film exposed by the trench.
11. The method of claim 10, wherein forming the first fin-shaped pattern comprises:
forming a field insulating film on the substrate, the field insulating film directly contacting a lower portion of the first fin pattern and not directly contacting an upper portion of the first fin pattern.
12. The method of claim 11, further comprising:
before the first oxide film is formed, etching corner parts of the first fin-shaped pattern, where the upper surface of the first fin-shaped pattern is connected with the side wall, so as to round the corner parts of the first fin-shaped pattern.
13. The method of claim 10, wherein forming the first fin-shaped pattern comprises:
forming a fourth fin-shaped pattern having an upper portion and a lower portion on the substrate;
forming a field insulating film directly contacting a lower portion of the fourth fin pattern and not directly contacting an upper portion of the fourth fin pattern;
forming a fourth oxide film along a contour of the fourth fin-shaped pattern by oxidizing a portion of the fourth fin-shaped pattern after forming the field insulating film; and
and removing the fourth oxide film.
14. The method of claim 13, wherein a width of an upper portion of the first fin pattern at a first height above an upper surface of the substrate is less than a width of an upper portion of the fourth fin pattern at the first height and greater than a width of an upper portion of the second fin pattern at the first height.
15. A method of manufacturing a semiconductor device, the method comprising:
forming a first fin-shaped pattern on a substrate;
converting an outer portion of an upper portion of the first fin pattern into a first oxide film;
forming a second fin-shaped pattern by removing the first oxide film;
converting an outer portion of an upper portion of the second fin pattern into a second oxide film;
forming a dummy gate electrode crossing the second fin pattern;
forming spacers on sidewalls of the dummy gate electrode and on the second oxide film;
forming a third fin-shaped pattern by removing at least a portion of the second oxide film exposed through the spacer,
wherein a width of an upper portion of the second fin pattern at a first height above an upper surface of the substrate is less than a width of an upper portion of the first fin pattern at the first height and greater than a width of an upper portion of the third fin pattern at the first height, and
wherein a height of the second fin pattern above the upper surface of the substrate is less than a height of the first fin pattern above the upper surface of the substrate and greater than a height of the third fin pattern above the upper surface of the substrate.
16. The method of claim 15, wherein the third fin pattern extends along a first direction, the method further comprising:
forming a field insulating film covering a sidewall of a lower portion of the first fin-shaped pattern before forming the second fin-shaped pattern; and
after forming the second fin pattern, forming electrode structures on the substrate extending in a second direction that intersects the first direction.
17. The method of claim 15, wherein a width of a lower portion of the third fin pattern is greater than a width of an upper portion of the third fin pattern and equal to a width of a lower portion of the second fin pattern.
18. The method of claim 15, further comprising the step of: rounding a corner portion of at least one of the first fin-shaped pattern, the second fin-shaped pattern and the third fin-shaped pattern.
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