CN105826214B - A kind of preparation method of bonded wafer structure - Google Patents
A kind of preparation method of bonded wafer structure Download PDFInfo
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- CN105826214B CN105826214B CN201610371516.6A CN201610371516A CN105826214B CN 105826214 B CN105826214 B CN 105826214B CN 201610371516 A CN201610371516 A CN 201610371516A CN 105826214 B CN105826214 B CN 105826214B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract
The present invention relates to technical field of manufacturing semiconductors; more particularly to a kind of preparation method of bonded wafer structure; by the way that protective layer of the metal wire as low-K material in subsequent DV or TE etching process is arranged in the two sides of the low-K material layer in the region of the pre-formed interconnected pores of the first wafer; to realize the protection in DV or TE etching process to low-K material; low-K material is damaged with eliminating to stack in technique, and provides strong technical support toward two-step process simplification for three steps in stacking technique.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of preparation methods of bonded wafer structure.
Background technique
As electronic equipment and memory are towards miniaturization and slimming development, there has also been more for volume and thickness to chip
High requirement.The three-dimensionally integrated of wafer is the solution that chip performance is improved while keeping prior art node, this
Technology integrates the same or different chip of two or more functions by bonding, this to be integrated in holding chip
The performance of chip is improved while volume；The metal interconnection between functional chip is shortened simultaneously, so that fever, power consumption, prolonging
It is greatly reduced late；And the bandwidth between functional module is greatly improved, to be mentioned while keeping prior art node
The high performance of chip.
(Stacking) technology of stacking has been play an important role in the three-dimensionally integrated technique of current wafer, in Stack Technology
In, by two steps, (silicon etching (Silicon Etch, abbreviation SE)+deep hole etches (Deep Via, abbreviation DV) or etching groove
The technique that (Trench Etch, abbreviation TE) links two wafers is that current industry studies more technique, its relatively before SE+DV+
The technique of tri- step of TE saves great amount of cost and realizes process optimization.
But the stacking of two-step process connects processing procedure in second step DV or TE technique to wafer low K (low K) material
Many damages are will cause, so as to cause going wrong in device (device) performance, this is that those skilled in the art are reluctant
What opinion arrived.
Summary of the invention
In view of the above problems, the invention discloses a kind of preparation methods of bonded wafer structure, including walk as follows
It is rapid:
Step S1 provides the first crystalline substance of a first medium layer including the first substrate and positioned at first substrate
Circle, is provided with low-K material layer and the first metal layer on the low-K material layer in the first medium layer, and described the
The region of pre-formed interconnected pores, and the low K material in the region for being located at the pre-formed interconnected pores are provided in one wafer
The two sides of the bed of material are provided with metal wire；
Step S2 provides the second crystalline substance of a second dielectric layer including the second substrate and positioned at second substrate
It is round, second metal layer is provided in the second dielectric layer；
Step S3 is bonded first wafer and second wafer to form bonded wafer, and first wafer position
On second wafer；
Step S4 etches the bonded wafer, is given the first metal layer and the second metal layer with being formed
Exposed interconnected pores, wherein during etching is located at the low-K material layer in the region of the pre-formed interconnected pores, institute
State the low-K material layer that metal wire protection is located at except the region of the pre-formed interconnected pores；
Step S5 is filled the interconnected pores, to be formed the first metal layer and second metal layer electricity
The interconnection line of connection.
The preparation method of above-mentioned bonded wafer structure, wherein the first metal layer is being located at first wafer
It is disconnected at the region of pre-formed interconnected pores.
The preparation method of above-mentioned bonded wafer structure, wherein in the bonded wafer, the disconnection of the first metal layer
The projection of part in vertical direction partially overlaps with the second metal layer.
The preparation method of above-mentioned bonded wafer structure, wherein the material of the metal wire is copper.
The preparation method of above-mentioned bonded wafer structure, wherein first substrate and second substrate are silicon lining
Bottom.
The preparation method of above-mentioned bonded wafer structure, wherein in the step S4, the etching bonded wafer
Step is the technique that first silicon etching carries out via etch again.
The preparation method of above-mentioned bonded wafer structure, wherein in the step S4, the etching bonded wafer
Step is the technique that first silicon etching carries out etching groove again.
The preparation method of above-mentioned bonded wafer structure, wherein in the step S4, formed etching the bonded wafer
Before the processing step of the interconnected pores, include the steps that carrying out first substrate thinned.
The preparation method of above-mentioned bonded wafer structure, wherein the material of the interconnection line is metal.
Foregoing invention is with the following advantages or beneficial effects:
The invention discloses a kind of preparation methods of bonded wafer structure, pass through the pre-formed interconnected pores in the first wafer
Protective layer of the two sides setting metal wire of low-K material layer in region as low-K material in subsequent DV or TE etching process, thus
The protection in DV or TE etching process to low-K material is realized, low-K material is damaged with eliminating to stack in technique, and is heap
Three steps provide strong technical support toward two-step process simplification in folded technique.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1~5 are the flowage structure schematic diagrames of the preparation method of bonded wafer structure in the embodiment of the present invention；
Fig. 6 is the flow diagram of the preparation method of bonded wafer structure in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment with reference to the accompanying drawing, but not as limit of the invention
It is fixed.
As shown in fig. 6, this method includes following step present embodiment discloses a kind of preparation method of bonded wafer structure
It is rapid:
It is brilliant to provide one first including the first substrate 21 and the first medium layer 22 on the first substrate 21 for step 1
It is round, low-K material layer 24 is provided in the first medium layer 22 (actually in the low-K material layer 24 and inner metal layer 25 such as figure
Shown interval setting is not just repeated herein due to the inner metal layer 25 and the improved emphasis of non-present invention) and be located at low
The first metal layer 23 on K material layer 24 is provided with region (the i.e. subsequent pre- carry out DV of pre-formed interconnected pores in first wafer
Or TE technique is to form the region of deep hole or groove), and two of the low-K material layer 24 in the region for being located at pre-formed interconnected pores
Side is provided with metal wire 26 (metal wire 26 can be the copper wire of reservation), it is preferred that first substrate 21 is silicon substrate, such as Fig. 1
Shown in structure.
In a preferred embodiment of the invention, the setting of metal wire 26 need to meet the following: 1, metal wire 26 is right
Claim on the TM (second metal layer 13) that the region of subsequent pre-formed deep hole allows deep hole to be self-aligned to the second wafer；2, symmetrical gold
Belong to line 26 between spacing be greater than or equal to subsequent pre-formed deep hole size (width)；3, between symmetrical metal wire 26
Spacing be less than or equal to subsequent pre-formed groove size (width)；4, the spacing between every layer of symmetrical metal wire 26 will connect
Closely, there can be no gaps, and low K material is exposed.
In a preferred embodiment of the invention, above-mentioned the first metal layer 23 is in the pre-formed interconnection for being located at the first wafer
It is disconnected at the region in hole, specifically, the two are golden as shown in Figure 1, the first metal layer 23 includes two metal layers 231,232
Belong to and being isolated between layer 231 and 232 by first medium layer 22, and the region between two metal layers 231 and 232 is just
The region of the pre-formed interconnected pores of the first wafer of part, therefore during being subsequently formed interconnected pores, the interconnected pores just position
Between two metal layers 231 and 232, and the distance between two metal layers 231 and 232 are just equal to the width of interconnected pores.
It is brilliant to provide one second including the second substrate 11 and the second dielectric layer 12 on the second substrate 11 for step 2
It is round, it is provided with second metal layer 13 in second dielectric layer 12, and the second metal layer 13 is located at the pre-formed interconnection of the second wafer
The underface in the region in hole；Preferably, which is silicon substrate, structure as shown in Figure 2.
Step 3 is bonded the first wafer and the second wafer to form bonded wafer, and the first wafer be located at the second wafer it
On, since the technique of two wafer bondings together to be well known to those skilled in the art, just do not repeated herein；At this
It invents in a preferred embodiment, in the bonded wafer, the projection of the breaking part of the first metal layer 23 in vertical direction
It is overlapped with part second metal layer 13.
Step 4 after carrying out reduction process to the first substrate 21, continues to etch bonded wafer, to be formed the first metal layer
23 and second metal layer 13 give exposed interconnected pores (wherein, the first metal layer 23 partial sidewall exposure, second metal layer
13 portion of upper surface exposure), wherein during etching is located at the low-K material layer 24 in the region of pre-formed interconnected pores, gold
Belong to line 26 and protect the low-K material layer 24 being located at except the region of pre-formed interconnected pores in the first wafer, to avoid in the first wafer
Low-K material layer 24 except the region of pre-formed interconnected pores damages.
In a preferred embodiment of the invention, in above-mentioned steps S4, the step of etching bonded wafer is first silicon etching
The technique of via etch is carried out again.
In a preferred embodiment of the invention, in above-mentioned steps S4, the step of etching bonded wafer is first silicon etching
The technique of etching groove is carried out again.
Step 5 is filled interconnected pores, with formed the first metal layer 23 and second metal layer 13 be electrically connected it is mutual
Line 3.
In a preferred embodiment of the invention, the material that above-mentioned interconnection line 3 is filled is metal.
To sum up, the invention discloses a kind of preparation methods of bonded wafer structure, by the pre-formed mutual of the first wafer
Even protection of the two sides setting metal wire of the low-K material layer in the region in hole as low-K material in subsequent DV or TE etching process
Layer damages low-K material with eliminating to stack in technique to realize the protection in DV or TE etching process to low-K material,
And strong technical support is provided toward two-step process simplification for three steps in stacking technique.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (9)
1. a kind of preparation method of bonded wafer structure, which comprises the steps of:
Step S1 provides first wafer including the first substrate and the first medium layer positioned at first substrate, institute
It states and is provided with low-K material layer, inner metal layer and the first metal layer in first medium layer, wherein the low-K material layer and described
The setting of inner metal layer interval, the first metal layer is located on the low-K material layer and the inner metal layer, and described the
The region of pre-formed interconnected pores, and the low K material in the region for being located at the pre-formed interconnected pores are provided in one wafer
The two sides of the bed of material are provided with metal wire；
Step S2 provides second wafer including the second substrate and the second dielectric layer positioned at second substrate, institute
It states and is provided with second metal layer in second dielectric layer；
Step S3 is bonded first wafer and second wafer to form bonded wafer, and first wafer is located at institute
It states on the second wafer；
Step S4 etches the bonded wafer, is exposed the first metal layer and the second metal layer with being formed
Interconnected pores, wherein etching be located at the pre-formed interconnected pores region the low-K material layer during, the gold
Belong to the low-K material layer that line protection is located at except the region of the pre-formed interconnected pores；
The thickness of the metal wire is greater than the overall thickness of the low-K material layer；
Step S5 is filled the interconnected pores, is electrically connected the first metal layer and the second metal layer with being formed
Interconnection line；
The region of the pre-formed interconnected pores is region of the subsequent progress DV or TE technique to form deep hole or groove；
Spacing between the metal wire is greater than or equal to the size of the deep hole；
Spacing between the metal wire is less than or equal to the size of the groove.
2. the preparation method of bonded wafer structure as described in claim 1, which is characterized in that the first metal layer is being located at
It is disconnected at the region of the pre-formed interconnected pores of first wafer.
3. the preparation method of bonded wafer structure as claimed in claim 2, which is characterized in that described in the bonded wafer
The projection of the breaking part of the first metal layer in vertical direction partially overlaps with the second metal layer.
4. the preparation method of bonded wafer structure as described in claim 1, which is characterized in that the material of the metal wire is
Copper.
5. the preparation method of bonded wafer structure as described in claim 1, which is characterized in that first substrate and described
Two substrates are silicon substrate.
6. the preparation method of bonded wafer structure as claimed in claim 5, which is characterized in that in the step S4, the quarter
The technique that the step of losing the bonded wafer carries out via etch for first silicon etching again.
7. the preparation method of bonded wafer structure as claimed in claim 5, which is characterized in that in the step S4, the quarter
The technique that the step of losing the bonded wafer carries out etching groove for first silicon etching again.
8. the preparation method of bonded wafer structure as described in claim 1, which is characterized in that in the step S4, etching
The bonded wafer is formed before the processing step of the interconnected pores, include thes steps that carrying out first substrate thinned.
9. the preparation method of bonded wafer structure as described in claim 1, which is characterized in that the material of the interconnection line is gold
Belong to.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610371516.6A CN105826214B (en) | 2016-05-30 | 2016-05-30 | A kind of preparation method of bonded wafer structure |
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| CN201610371516.6A CN105826214B (en) | 2016-05-30 | 2016-05-30 | A kind of preparation method of bonded wafer structure |
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| CN105826214A CN105826214A (en) | 2016-08-03 |
| CN105826214B true CN105826214B (en) | 2019-04-30 |
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| US8933544B2 (en) * | 2012-07-12 | 2015-01-13 | Omnivision Technologies, Inc. | Integrated circuit stack with integrated electromagnetic interference shielding |
| CN104051414B (en) * | 2013-03-12 | 2018-03-23 | 台湾积体电路制造股份有限公司 | Interconnection structure and method |
| US9536777B2 (en) * | 2013-03-13 | 2017-01-03 | Taiwan Semiconductor Manufacutring Company, Ltd. | Interconnect apparatus and method |
| US10056353B2 (en) * | 2013-12-19 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC interconnect apparatus and method |
| US20150348874A1 (en) * | 2014-05-29 | 2015-12-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC Interconnect Devices and Methods of Forming Same |
| CN104319258B (en) * | 2014-09-28 | 2017-08-04 | 武汉新芯集成电路制造有限公司 | A kind of silicon perforation technique |
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