CN105826201A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN105826201A CN105826201A CN201510012092.XA CN201510012092A CN105826201A CN 105826201 A CN105826201 A CN 105826201A CN 201510012092 A CN201510012092 A CN 201510012092A CN 105826201 A CN105826201 A CN 105826201A
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Abstract
The invention provides a method for forming a semiconductor device. The method comprises a step of forming a first gate electrode on a semiconductor substrate, a step of forming a side wall at the side wall of the first gate electrode, a step of forming a semiconductor material layer on the semiconductor substrate, the first gate electrode and the side wall, wherein the upper surface of the semiconductor material layer is higher than that of the first gate electrode, a step of removing the semiconductor material layer which is higher than the first gate electrode, a step of etching the remaining semiconductor material layer until the semiconductor material layer which covers the side wall is removed; a step of patterning a remaining semiconductor material layer part, and forming two first out connection parts at two sides of the gate electrode, and a step of correspondingly forming a first source electrode and a first drain electrode under the two first out connection parts. According to the scheme of the invention, since the partial semiconductor material layer on the side wall is etched, the parasitic capacitance between the first gate electrode and the first source electrode and the first drain electrode is reduced and even eliminated, the signal crosstalk between the first gate electrode and the first source electrode and the first drain electrode is reduced and even eliminated, the normal operation of the device is ensured, and the performance is excellent.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the forming method of a kind of semiconductor device.
Background technology
In technical field of semiconductors, CMOS (ComplementaryMetalOxideSemiconductor under low-voltage driving, CMOS) high voltage metal-oxide semiconductor field effect transistor (hereinafter referred to as high voltage transistor) under field-effect transistor (hereinafter referred to as low voltage transistor) and high drive, can be integrated in a Semiconductor substrate.Due to high voltage transistor, such as lateral double diffusion metal oxide semiconductor (Lateraldouble-diffusionMetal-Oxide-semiconductor, LDMOS) field-effect transistor, there is high breakdown voltage, meet high pressure resistant, to realize the aspects such as power control requirement, it is widely used in high-voltage power integrated circuit, as logic element device.
The forming method of the existing semiconductor device being integrated with low voltage transistor and high voltage transistor includes:
With reference to Fig. 1, it is provided that Semiconductor substrate 1, being formed on semiconductor substrate 1: be positioned at the high voltage transistor 2,3 of the first well region 10 and be positioned at the low voltage transistor 4 in the second district 20, the first well region 10 is dielectrically separated from by fleet plough groove isolation structure 5 with the second well region 20；
As a example by high voltage transistor 2, high voltage transistor 2 has grid 20, is formed with hard mask layer 6 on grid 20, is formed with side wall 7 at grid 20 and hard mask layer 6 sidewall.
With reference to Fig. 2, on semiconductor substrate 1, on hard mask layer 6 and side wall 7 sidewall forms semiconductor material layer 8；Semiconductor material layer 8 is divided into: the Part I 81 in Semiconductor substrate 1 and the Part II 82 on hard mask layer 6 and the Part III 83 of side wall 7 sidewall.
With reference to Fig. 3, forming patterned mask layer 9 on semiconductor material layer 8, define corresponding source electrode, the stub-out of drain locations, for improving alignment precision, patterned mask layer 9 covers the semi-conducting material layer segment on side wall 7；
The mask layer 9 graphically changed is mask, and etching semiconductor material layer 8 (with reference to Fig. 3), to exposing hard mask layer 6 upper surface and Semiconductor substrate 1 upper surface, forms stub-out 21,22 in the position of grid 20 both sides correspondence source electrode and drain electrode；
With reference to Fig. 4, remove patterned mask layer；
Afterwards, with hard mask layer as mask, to stub-out 21,22 and under Semiconductor substrate carry out ion implanting, be correspondingly formed source electrode 23 and drain electrode 24 for 21,22 times in stub-out, stub-out 21,22 picks out electrically connect with source electrode 23 and drain electrode 24 respectively；
Finally, hard mask layer is removed.
But, with reference to Fig. 4, owing to the Part III 83 on side wall 7 does not etches away, stub-out 21,22 links together with Part III 83.Forming parasitic capacitance (parasiticcapacitance) between Part III 83 and grid 20, parasitic capacitance can cause the signal cross-talk between grid 20 and source electrode 21 and drain electrode 22, and disturbance means is properly functioning.And, there is also the probability punctured between grid 20 and Part III 83, same problem exists in high voltage transistor 3 and low voltage transistor 4 so that grid directly electrically connects with source electrode or drain electrode, and this can cause component failure.
Summary of the invention
The problem that the present invention solves is, uses prior art to be formed in the semiconductor device being integrated with low voltage transistor and high voltage transistor, there is parasitic capacitance, cause signal cross-talk in device, even cause component failure between grid and its source electrode or drain electrode.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor device, and the forming method of this semiconductor device includes:
Semiconductor substrate is provided；
Form first grid on the semiconductor substrate；
Side wall is formed at described first grid sidewall；
On the semiconductor substrate, forming semiconductor material layer on first grid and on side wall, the upper surface of described semiconductor material layer is higher than first grid upper surface；
Remove the semi-conducting material layer segment higher than described first grid upper surface；
After residue semi-conducting material layer segment is etched back to, residue semi-conducting material layer segment is patterned, the Semiconductor substrate of described first grid both sides is formed two first stub-outs；
After residue semi-conducting material layer segment is etched back to, residue semi-conducting material layer segment is patterned, the Semiconductor substrate of described first grid both sides is formed two first stub-outs；
To two first stub-outs and under Semiconductor substrate carry out ion implanting, the Semiconductor substrate below two first stub-outs is formed the first source electrode and first drain electrode.
Alternatively, use chemical mechanical milling tech, remove the semi-conducting material layer segment higher than described first grid upper surface.
Alternatively, the material of described semiconductor material layer is polysilicon.
Alternatively, described spacer material is silicon oxide.
Alternatively, the method at described first grid sidewall formation side wall includes:
Spacer material layer is formed on the semiconductor substrate with on first grid；
Described spacer material layer is etched back to, to the upper surface exposing described first grid.
Alternatively, on the semiconductor substrate, on first grid and form semiconductor material layer on side wall before, described first grid is formed hard mask layer；
Described side wall is also located at described hard mask layer sidewall.
Alternatively, the grid during described first grid is high voltage transistor or the grid in low voltage transistor.
Alternatively, when forming described first grid, the first source electrode and the first drain electrode, form the 3rd grid, the 3rd source electrode of described 3rd grid both sides and the 3rd drain electrode the most on the semiconductor substrate；
Described first grid and the 3rd grid one of them be the grid in high voltage transistor, another is the grid in low voltage transistor.
Alternatively, described first grid is the grid of high voltage transistor, before forming described first grid, also includes:
Described Semiconductor substrate is carried out the first type ion implanting to form the first well region, the doping type transoid of described first type ion and Semiconductor substrate；
First well region is carried out Second-Type ion implanting to form the second well region, described first type ion and the type transoid of Second-Type ion；
Described second well region is carried out the first type ion implanting, forms two first drift regions in first grid both sides respectively；
First fleet plough groove isolation structure is formed in each described first drift region；
In described first grid Semiconductor substrate between two first fleet plough groove isolation structures；
Described first source electrode and the first drain electrode lay respectively in two first drift regions of first grid both sides, and are isolated with first grid by the first fleet plough groove isolation structure.
Alternatively, described first grid is the grid of high voltage transistor, before forming described first grid, also includes:
Described Semiconductor substrate is carried out the first type ion implanting to form the first well region, the doping type transoid of described first type ion and Semiconductor substrate；
Described first well region is carried out Second-Type ion implanting, forms two second drift regions in first grid both sides respectively；
Second fleet plough groove isolation structure is formed in each described second drift region；
On the described first grid the first well region between two second fleet plough groove isolation structures；
Described first source electrode and the first drain electrode lay respectively in two second drift regions of first grid both sides, and are isolated with first grid by the second fleet plough groove isolation structure.
Alternatively, described second grid is the grid of low voltage transistor, described Semiconductor substrate is carried out the first type ion implanting to form the first well region before or after, in described Semiconductor substrate, also carry out ion implanting to form the 3rd well region, described 3rd well region and the first well region are spaced apart；
When forming the first fleet plough groove isolation structure in described first drift region, between described 3rd well region and the first well region, also form the 3rd fleet plough groove isolation structure；
When forming described first grid, also form the 3rd grid at described 3rd well region；
When described first grid sidewall forms described side wall, also form side wall at described 3rd gate lateral wall, and expose the 3rd source electrode and the 3rd drain electrode；
When the position of corresponding described first source electrode and the first drain electrode forms two first stub-outs respectively, the position of the most corresponding described 3rd source electrode and the 3rd drain electrode forms two the 3rd stub-outs；
When described 3rd well region and the first drift region have homotype doping, when forming the first source electrode and the first drain electrode, also two the 3rd stub-outs and the 3rd well region below are carried out ion implanting, under two the 3rd stub-outs, form the 3rd source electrode and the 3rd drain electrode respectively.
Alternatively, described first stub-out covers described first source electrode and the fleet plough groove isolation structure part adjacent with described first source electrode, and another first stub-out described covers described first drain electrode and the fleet plough groove isolation structure part adjacent with described first drain electrode；
Described 3rd stub-out covers described 3rd source electrode and the fleet plough groove isolation structure part adjacent with described 3rd source electrode, and another the 3rd stub-out described covers described 3rd drain electrode and the fleet plough groove isolation structure part adjacent with described 3rd drain electrode.
Compared with prior art, technical scheme has the advantage that
When forming semiconductor material layer, semiconductor material layer upper surface is higher than first grid upper surface, and in prior art, semiconductor material layer is formed at side wall sidewall；Afterwards, remove the semi-conducting material layer segment higher than described first grid upper surface, make residue semiconductor material layer portion of upper surface maintain an equal level with first grid upper surface；Then, remaining semi-conducting material layer segment is etched back to, to removing the semi-conducting material layer segment covered on side wall；Afterwards, remaining semi-conducting material layer segment is patterned, forms two first stub-outs respectively with the position of corresponding first source electrode and the first drain electrode；To two first stub-outs and under Semiconductor substrate carry out ion implanting, formed respectively the first source electrode and first drain electrode.During being etched back to, owing to the upper surface of remaining semi-conducting material layer segment is equal to the distance of Semiconductor substrate upper surface, therefore the etch rate of various piece is essentially identical, therefore treating that the semi-conducting material layer segment full etching above side wall falls, only residue covers the semi-conducting material layer segment of Semiconductor substrate.Owing to the semi-conducting material layer segment on side wall is etched away, reduce the parasitic capacitance even eliminated between first grid and the first source electrode, drain electrode, the signal cross-talk even eliminated between first grid and the first source electrode, drain electrode can be reduced, it is ensured that device is properly functioning, and performance is preferable.
Accompanying drawing explanation
Fig. 1～Fig. 4 is the semiconductor device of prior art in the forming process profile in each stage；
Fig. 5～Figure 17 is the semiconductor device of the specific embodiment of the invention in the forming process profile in each stage.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
With reference to Fig. 5, it is provided that Semiconductor substrate 100.Semiconductor substrate 100 has the region for the region and high voltage transistor forming low voltage transistor, and wherein the layout of regional can be designed according to concrete device architecture.
In the present embodiment, Semiconductor substrate 100 can be silicon substrate, it is also possible to be germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate.Those skilled in the art can select the type of Semiconductor substrate as required, and therefore the type of Semiconductor substrate 100 should not become the feature limited the scope of the invention.Semiconductor substrate 100 in the present embodiment is silicon substrate, because implementing the technical program on a silicon substrate to implement the technical program low cost than on other types substrate.
With reference to Fig. 6, Semiconductor substrate 100 carries out the first type ion implanting form the first well region 110 and carry out Second-Type ion implanting formation the 3rd well region 130, wherein the first type ion and the type transoid of Second-Type ion, the first well region 110 is compared Semiconductor substrate 100 and is had transoid doping.In the present embodiment, the first well region 110 and the 3rd well region 130 are adjacent well region, and its position relationship only plays example effect, does not constitute limiting the scope of the invention.First well region 110 is the region forming high voltage transistor, and the 3rd well region 130 is the region forming low voltage transistor.
In the present embodiment, Semiconductor substrate 100 has p-type doping, and correspondingly the first type ion is N-type ion, and Second-Type ion is p-type ion.First well region 110 is the region forming the device with high voltage transistor, and the 3rd well region 130 is the device area being formed and having low voltage transistor.Therefore, having high resistance for making the first well region 110 be capable of withstanding high voltage, in the first well region 110, the doping content of the first type ion is less than the doping content of Second-Type ion in the 3rd well region 130.
In other embodiments, it is also possible to be: Semiconductor substrate is n-type doping, the first type ion is p-type ion, and Second-Type ion is N-type ion, and the first well region is high pressure resistant p-well region compared to Semiconductor substrate and the 3rd well region.
In the present embodiment, the first type ion and the type transoid of Second-Type ion, but it is not limited to this.In other examples, it is also possible to be: the first type ion and Second-Type ion homotype.Type for the first type ion and Second-Type ion can select as required.
In the present embodiment, due to the first type ion and Second-Type ion transoid, therefore the first well region 110 and the 3rd well region 130 to be carried out respectively the process of twice ion implanting.Namely: form the first mask pattern the most on a semiconductor substrate 100, define the fenestra of the first well region, afterwards with the first mask pattern as mask, Semiconductor substrate is carried out the first type ion implanting and forms the first well region 110, finally remove the first mask pattern；Then, form the second mask pattern on a semiconductor substrate 100, define the window of the 3rd well region, afterwards with the second mask pattern as mask, Semiconductor substrate is carried out Second-Type ion implanting and forms the 3rd well region 130.
With reference to Fig. 7, the first well region 110 carrying out Second-Type ion implanting to form the second well region 120, the second well region 120 is high-pressure trap area, and Second-Type ion doping concentration is relatively low；
With reference to Fig. 8, the second well region 120 is carried out the first type ion implanting to form first drift region 121 at two intervals；With,
First well region 110 is carried out Second-Type ion implanting to form second drift regions 111 at two intervals, between two second drift regions 111, spaced apart between the second drift region 111 and the second well region 120.
For making the first drift region 121 and the second drift region 111 be capable of withstanding high pressure and have high resistance, the ion doping concentration in the first drift region 121 and the second drift region 111 is relatively low.
With reference to Fig. 9, formed in Semiconductor substrate 100: isolate the first well region 110 and the 3rd well region 130, lay respectively in two first drift regions 121, isolate the second well region 120 and the second adjacent drift region 111, the fleet plough groove isolation structure that lays respectively in two second drift regions 111.Wherein the fleet plough groove isolation structure in the first drift region 121 is the first fleet plough groove isolation structure 141, fleet plough groove isolation structure in second drift region 111, and the fleet plough groove isolation structure of isolation the second well region 120 and the second adjacent drift region 111 is the second fleet plough groove isolation structure 142, the fleet plough groove isolation structure isolating the first well region 110 and the 3rd well region 130 is the 3rd fleet plough groove isolation structure 143.
In the present embodiment, first, second and third fleet plough groove isolation structure is formed in same step.Specifically, the forming method of first, second and third fleet plough groove isolation structure includes:
Semiconductor substrate 100 is patterned, form the groove of corresponding first, second and third fleet plough groove isolation structure respectively, when first, second and third fleet plough groove isolation structure desired depth is homogeneous while, all grooves can be formed in one step, when first, second and third fleet plough groove isolation structure desired depth differs, the groove of different depth can be formed respectively；
Forming laying 140 at trenched side-wall, the material of laying 140 is silicon oxide, it is possible to improve the interfacial characteristics between fleet plough groove isolation structure and Semiconductor substrate in follow-up groove；
Using chemical gaseous phase formation of deposits shallow trench isolated material, shallow trench isolated material is filled full groove and covers Semiconductor substrate 100；
Using chemical mechanical milling tech, remove the shallow trench isolated material higher than Semiconductor substrate 100, remaining shallow trench isolated material is as fleet plough groove isolation structure.
With reference to Figure 10, the hard mask layer 170 form first grid 151 in Semiconductor substrate between two first fleet plough groove isolation structures 141, being positioned on first grid 151, wherein it is formed with gate dielectric layer (non-label in figure) between first grid 151 and the second well region 120, first grid 151 extend out on two first fleet plough groove isolation structures 141, first grid 151, by gate dielectric layer and the first fleet plough groove isolation structure 141, is isolated with the second well region 120 and two first drift regions 121；With,
The hard mask layer 170 form second grid 152 in the Semiconductor substrate between two second fleet plough groove isolation structures 142 in two second drift regions 111, being positioned on second grid 152, wherein it is formed with gate dielectric layer (non-label in figure) between second grid 152 and the first well region 110, second grid 152 extend out to be positioned on two second fleet plough groove isolation structures 142, second grid 152, by gate dielectric layer and the second fleet plough groove isolation structure 142, is isolated with the first well region 110 and two second drift regions 111；With,
The hard mask layer 170 form, at the 3rd well region 130, two the 3rd grids 153 being spaced being positioned in Semiconductor substrate 100, being positioned on the 3rd grid 153, is formed with gate dielectric layer (non-label in figure) between the 3rd grid 153 and Semiconductor substrate 100.
In the present embodiment, first grid 151, second grid 152 and the 3rd grid 153 can be formed in same step.The forming method of first, second and third grid and hard mask layer 170 includes: form gate material layers, the layer of hard mask material being positioned in gate material layers on a semiconductor substrate 100；It is patterned layer of hard mask material and gate material layers to form hard mask layer 170 and first, second and third grid.
With reference to Figure 11, forming side wall 180 at hard mask layer 170 sidewall, first grid 151 sidewall, second grid 152 sidewall and the 3rd grid 153 sidewall, the material of side wall 180 is insulating dielectric materials, such as silicon oxide.
In the present embodiment, the forming method of side wall 180 includes:
On a semiconductor substrate with on hard mask layer, and hard mask layer sidewall and first, second and third gate lateral wall deposition spacer material layer；
The offside walling bed of material is etched back to, owing to the spacer material layer segment of hard mask layer sidewall and first, second and third gate lateral wall is more than at the thickness being perpendicular on Semiconductor substrate 100 upper surface direction, spacer material layer segment in Semiconductor substrate 100 and hard mask layer 170, therefore during being etched back to, after spacer material layer segment in Semiconductor substrate 100 and hard mask layer 170 is all etched away, hard mask layer 170 sidewall and first, second and third gate lateral wall there remains spacer material layer segment using as side wall 180.
With reference to Figure 12, on a semiconductor substrate 100, forming semiconductor material layer 190 on hard mask layer 170 and side wall 180, semiconductor material layer 190 is higher than hard mask layer 170, and semiconductor material layer 190 is for forming connection source electrode and the stub-out of drain electrode.Owing to hard mask layer 170 is higher than Semiconductor substrate 100, therefore the semi-conducting material layer segment on hard mask layer 170 is higher than the semi-conducting material layer segment in Semiconductor substrate 100.
The material of semiconductor material layer is un-doped polysilicon, and chemical vapor deposition method specifically can be used to be formed.
With reference to Figure 13, use chemical mechanical milling tech, semiconductor material layer 190 upper surface is carried out planarization process, remain basically stable with hard mask layer 170 upper surface to residue semiconductor material layer 190 upper surface.
Chemical mechanical milling tech includes two steps: the first grinding steps, the semi-conducting material layer segment to hard mask layer 170 is contour with the semi-conducting material layer segment in Semiconductor substrate 100；Second grinding steps, remains basically stable to residue semiconductor material layer portion of upper surface with hard mask layer 170 upper surface.
With reference to Figure 14, with hard mask layer 170 and side wall 180 as mask, remaining semiconductor material layer 190 part is etched back to, is removed to the semi-conducting material layer segment covered on side wall 180 and obtains the thickness of required stub-out.In conjunction with reference to Figure 13, owing to semiconductor material layer 190 upper surface is smooth, semiconductor material layer 190 various piece is identical at the etch rate being perpendicular on semiconductor material layer 190 upper surface direction, after required stub-out thickness to be obtained, the semi-conducting material layer segment of side wall 180 sloped sidewall is also etched away, only the semi-conducting material layer segment in residue Semiconductor substrate 100.
With reference to Figure 15, using photoetching, etching technics, be patterned remaining semi-conducting material layer segment, form two stub-outs in each grid both sides correspondence source electrode, the position of drain electrode, stub-out is for picking out corresponding source electrode, drain electrode.
Wherein, the stub-out being positioned on the first drift region 121 of first grid 151 both sides is the first stub-out 191, the stub-out being positioned on the second drift region 111 of second grid 152 both sides is the second stub-out 192, and two stub-outs being positioned on the 3rd well region 130 of the 3rd grid 153 both sides are the 3rd stub-out 193；
With reference to Figure 16, with hard mask layer 170 and side wall 180 as mask, to the first stub-out 191 and under the first drift region 121 carry out the first type ion implanting, forming the first source electrode 161 and the first drain electrode 162 in two first drift regions 121 respectively, the first source electrode 161 and the first drain electrode 162 are dielectrically separated from by the first fleet plough groove isolation structure 141 respectively；With,
To the second stub-out 192 and under the second drift region 111 carry out Second-Type ion implanting, forming second source electrode the 163, second drain electrode 164 in two second drift regions 111 respectively, the second source electrode 163 and the second drain electrode 164 are dielectrically separated from by the second fleet plough groove isolation structure 142 respectively；With,
To the 3rd stub-out 193 and under the 3rd well region 130 carry out the first type ion implanting, with formed the 3rd source electrode and the 3rd drain electrode (non-label in figure), wherein two the 3rd grids 153 share a polar region 165.
Additionally, before carrying out the first type ion implanting in the 3rd well region to the 3rd grid 153 both sides, also include: use lightly doped drain injection technology, it is lightly doped in the 3rd well region to the 3rd grid 153 both sides and district 160 is lightly doped to be formed, district 160 is lightly doped and contributes to reducing the channel leakage effect between source and drain.3rd source electrode and the 3rd drain electrode are compared with being lightly doped district 160, for medium or high isodose ion implanting.
Owing to the first source electrode, drain electrode and the 3rd source electrode, drain electrode are adulterated for homotype, therefore can be formed in same step；
With reference to Figure 17, remove hard mask layer 170 (with reference to Figure 16).
By first, second and third stub-out is carried out ion implanting so that stub-out is conducted electricity, stub-out is connected with the source electrode under it or drain electrode point.
First stub-out 191 covers the first source electrode 161 and the fleet plough groove isolation structure part adjacent with described first source electrode 161, and another first stub-out 191 covers the first drain electrode 162 and the 162 adjacent fleet plough groove isolation structure parts that drain with first；Second stub-out 192 covers the second source electrode 163 and the fleet plough groove isolation structure part adjacent with the second source electrode 163, and another second stub-out 192 covers the second drain electrode 164 and the 164 adjacent fleet plough groove isolation structure parts that drain with second；3rd stub-out 193 covers the 3rd source electrode and the fleet plough groove isolation structure part adjacent with the 3rd source electrode, and another the 3rd stub-out 193 covers the 3rd drain electrode and the fleet plough groove isolation structure part adjacent with the 3rd drain electrode.
So, stub-out relatively increases the surface area of source electrode and drain electrode, it is to avoid source electrode and drain surface amass problem that is less and that cause source electrode and drain electrode cannot electrically connect with other devices.Owing to stub-out, the source electrode being pre-designed and drain surface are long-pending without too big, further, active area region area in Semiconductor substrate can be reduced, to increase device integration.
Compared with prior art, the sloped sidewall of side wall 180 does not have semiconductor material layer to remain, the only stub-out in the Semiconductor substrate of residue side wall 180 side, reduce the parasitic capacitance even eliminated between first grid 151 and the first source electrode 161 and the first drain electrode 162, between second grid 152 and the second source electrode 164 and the second drain electrode 165, between the 3rd grid and the 3rd source electrode and the 3rd drain electrode, can reduce and even eliminate the signal cross-talk between grid with adjacent source electrode and drain electrode, guarantee that device is properly functioning, and performance is preferable.
So far, with reference to Figure 17, same semi-conductive substrate 100 is formed: be positioned at the high voltage transistor of two transoids of the first well region 110, and be positioned at two low voltage transistors of the 3rd well region 130, embody high voltage transistor and have preferably compatible with low voltage transistor formation process.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. the forming method of a semiconductor device, it is characterised in that including:
Semiconductor substrate is provided；
Form first grid on the semiconductor substrate；
Side wall is formed at described first grid sidewall；
On the semiconductor substrate, forming semiconductor material layer on first grid and on side wall, the upper surface of described semiconductor material layer is higher than first grid upper surface；
Remove the semi-conducting material layer segment higher than described first grid upper surface；
After removing the semi-conducting material layer segment higher than described first grid upper surface, remaining semi-conducting material layer segment is etched back to, to removing the semi-conducting material layer segment covered on described side wall；
After residue semi-conducting material layer segment is etched back to, residue semi-conducting material layer segment is patterned, the Semiconductor substrate of described first grid both sides is formed two first stub-outs；
To two first stub-outs and under Semiconductor substrate carry out ion implanting, the Semiconductor substrate below two first stub-outs is formed the first source electrode and first drain electrode.
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that use chemical mechanical milling tech, remove the semi-conducting material layer segment higher than described first grid upper surface.
3. the forming method of semiconductor device as claimed in claim 2, it is characterised in that the material of described semiconductor material layer is polysilicon.
4. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described spacer material is silicon oxide.
5. the forming method of semiconductor device as claimed in claim 1, it is characterised in that the method forming side wall at described first grid sidewall includes:
Spacer material layer is formed on the semiconductor substrate with on first grid；
Described spacer material layer is etched back to, to the upper surface exposing described first grid.
6. the forming method of semiconductor device as claimed in claim 1, it is characterised in that on the semiconductor substrate, on first grid and form semiconductor material layer on side wall before, described first grid is formed hard mask layer；
Described side wall is also located at described hard mask layer sidewall.
7. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described first grid is the grid in high voltage transistor or the grid in low voltage transistor.
8. the forming method of semiconductor device as claimed in claim 7, it is characterized in that, when forming described first grid, the first source electrode and the first drain electrode, form the 3rd grid, the 3rd source electrode of described 3rd grid both sides and the 3rd drain electrode the most on the semiconductor substrate；
Described first grid and the 3rd grid one of them be the grid in high voltage transistor, another is the grid in low voltage transistor.
9. the forming method of semiconductor device as claimed in claim 8, it is characterised in that described first grid is the grid of high voltage transistor, before forming described first grid, also includes:
Described Semiconductor substrate is carried out the first type ion implanting to form the first well region, the doping type transoid of described first type ion and Semiconductor substrate；
First well region is carried out Second-Type ion implanting to form the second well region, described first type ion and the type transoid of Second-Type ion；
Described second well region is carried out the first type ion implanting, forms two first drift regions in first grid both sides respectively；
First fleet plough groove isolation structure is formed in each described first drift region；
In described first grid Semiconductor substrate between two first fleet plough groove isolation structures；
Described first source electrode and the first drain electrode lay respectively in two first drift regions of first grid both sides, and are isolated with first grid by the first fleet plough groove isolation structure.
10. the forming method of semiconductor device as claimed in claim 8, it is characterised in that described first grid is the grid of high voltage transistor, before forming described first grid, also includes:
Described Semiconductor substrate is carried out the first type ion implanting to form the first well region, the doping type transoid of described first type ion and Semiconductor substrate；
Described first well region is carried out Second-Type ion implanting, forms two second drift regions in first grid both sides respectively；
Second fleet plough groove isolation structure is formed in each described second drift region；
On the described first grid the first well region between two second fleet plough groove isolation structures；
Described first source electrode and the first drain electrode lay respectively in two second drift regions of first grid both sides, and are isolated with first grid by the second fleet plough groove isolation structure.
The forming method of 11. semiconductor device as claimed in claim 9, it is characterized in that, described second grid is the grid of low voltage transistor, described Semiconductor substrate is carried out the first type ion implanting to form the first well region before or after, also carrying out ion implanting in described Semiconductor substrate to form the 3rd well region, described 3rd well region and the first well region are spaced apart；
When forming the first fleet plough groove isolation structure in described first drift region, between described 3rd well region and the first well region, also form the 3rd fleet plough groove isolation structure；
When forming described first grid, also form the 3rd grid at described 3rd well region；
When described first grid sidewall forms described side wall, also form side wall at described 3rd gate lateral wall, and expose the 3rd source electrode and the 3rd drain electrode；
When the position of corresponding described first source electrode and the first drain electrode forms two first stub-outs respectively, the also position at corresponding described 3rd source electrode and the 3rd drain electrode forms two the 3rd stub-outs；
When described 3rd well region and the first drift region have homotype doping, when forming the first source electrode and the first drain electrode, also two the 3rd stub-outs and the 3rd well region below are carried out ion implanting, under two the 3rd stub-outs, form the 3rd source electrode and the 3rd drain electrode respectively.
The forming method of 12. semiconductor device as claimed in claim 11, it is characterized in that, described first stub-out covers described first source electrode and the fleet plough groove isolation structure part adjacent with described first source electrode, and another first stub-out described covers described first drain electrode and the fleet plough groove isolation structure part adjacent with described first drain electrode；
Described 3rd stub-out covers described 3rd source electrode and the fleet plough groove isolation structure part adjacent with described 3rd source electrode, and another the 3rd stub-out described covers described 3rd drain electrode and the fleet plough groove isolation structure part adjacent with described 3rd drain electrode.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613532A (en) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of field effect transistor and field effect transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083798A (en) * | 1998-05-26 | 2000-07-04 | Advanced Micro Devices, Inc. | Method of producing a metal oxide semiconductor device with raised source/drain |
| US6368927B1 (en) * | 1999-06-29 | 2002-04-09 | Hyunadi Electronics Industries, Ltd. | Method of manufacturing transistor having elevated source and drain regions |
| CN1841706A (en) * | 2005-03-29 | 2006-10-04 | 冲电气工业株式会社 | Method of manufacturing semiconductor device |
| CN104241354A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof |
-
2015
- 2015-01-09 CN CN201510012092.XA patent/CN105826201A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083798A (en) * | 1998-05-26 | 2000-07-04 | Advanced Micro Devices, Inc. | Method of producing a metal oxide semiconductor device with raised source/drain |
| US6368927B1 (en) * | 1999-06-29 | 2002-04-09 | Hyunadi Electronics Industries, Ltd. | Method of manufacturing transistor having elevated source and drain regions |
| CN1841706A (en) * | 2005-03-29 | 2006-10-04 | 冲电气工业株式会社 | Method of manufacturing semiconductor device |
| CN104241354A (en) * | 2013-06-09 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and forming method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613532A (en) * | 2019-02-25 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of field effect transistor and field effect transistor |
| CN111613532B (en) * | 2019-02-25 | 2023-08-22 | 中芯国际集成电路制造(上海)有限公司 | Forming method of field effect transistor and field effect transistor |
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