CN105810744A - Film transistor and manufacture method for the same - Google Patents
Film transistor and manufacture method for the same Download PDFInfo
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- CN105810744A CN105810744A CN201410843335.XA CN201410843335A CN105810744A CN 105810744 A CN105810744 A CN 105810744A CN 201410843335 A CN201410843335 A CN 201410843335A CN 105810744 A CN105810744 A CN 105810744A
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Abstract
The invention provides a film transistor and a manufacture method for the same. The manufacture method comprises steps of providing a substrate, forming a buffering layer on the substrate, forming a first gate electrode layer and a first insulation layer on the buffering layer, forming a first semiconductor layer, a source drain electrode and a second semiconductor layer on the first insulation layer, wherein the second semiconductor layer is superposed with the first semiconductor layer and the doped types of the first semiconductor layer and the second semiconductor layer are opposite, and forming a second insulation layer and a second gate electrode layer on the surface of the structure; the working voltage of the first gate electrode layer is a high potential and the working voltage of the second gate electrode layer is the low potential; big working current can be obtained under relatively low gate voltage; the high potential and the low potential between the first gate electrode layer and the second gate electrode layer can form an electric field, which increases the concentration of the effective carrier so as to improve the electric performance of the film transistor; and working current of the gate electrode is reduced, which reduces the possibility of breakdown of the gate insulation layer.
Description
Technical field
The present invention relates to technical field of semiconductors, be specifically related to a kind of thin film transistor (TFT) and preparation method thereof.
Background technology
Thin film transistor (TFT) (ThinFilmTransistor, TFT) device and Organic Light Emitting Diode (OrganicLight-EmittingDiode, OLED) active matrix driving Organic Light Emitting Diode (ActivematrixOrganicLight-EmittingDiode, the AMOLED) Display Technique that technology combines is the important development direction of current and following flat pannel display.
Common film transistor device specifically includes that active layer, it is provided that channel region, source region, drain region；Gate electrode, is formed over the channel region, and by gate insulator and active layer isolation.Usual active area quasiconductor generally adopts N-type semiconductor or P-type semiconductor as the active layer of film transistor device, is controlled the concentration of active area carrier (electronics or hole) by gate electrode voltage input.OLED belongs to current mode device, controls thin film transistor switch by inputting gate electrode voltage.The voltage that channel region size of current inputs with gate electrode is relevant, then needs to increase grid voltage as increased electric current, and gate electrode voltage is higher, occurs the probability that gate insulation layer punctures to increase.
Generally utilizing silicon oxide (SiOx) as gate insulation layer in prior art, comprehensive TFT characteristic and capacitive region capacitance size consider, by the thickness of change SiOx to improve device performance；Or by changing film layer structure, as adopted silicon oxide/silicon nitride (SiOx/SiNx) overlaying structure, to improve device performance.
Normal conditions expectation capacitive region capacitance is relatively big,Need rete d less, rete dielectric constantValue is big；And gate insulation layer thickness reduces in thin film transistor (TFT), leakage current can be increased and increase the probability that gate insulation layer punctures at higher voltages.
Summary of the invention
It is an object of the invention to provide a kind of thin film transistor (TFT) and preparation method thereof, under less gate voltage, can obtain bigger operating current, the reduction of gate operational voltages, decreases the probability that gate insulation layer punctures simultaneously.
For achieving the above object, the present invention provides the manufacture method of a kind of thin film transistor (TFT), including:
S01 a: substrate is provided, is formed on cushion；
S02: form first gate electrode layer and the first insulating barrier on described cushion；
S03: form the first semiconductor layer, source-drain electrode and the second semiconductor layer on described first insulating barrier, wherein, described second semiconductor layer is superimposed with described first semiconductor layer, and both doping types are contrary；
S04: form the second insulating barrier and second gate electrode layer at the S03 body structure surface formed；
S05: form the 3rd insulating barrier and metal level at the S04 body structure surface formed.
Optionally, described first semiconductor layer is n type semiconductor layer, and described second semiconductor layer is p type semiconductor layer.
Optionally, described first semiconductor layer is the polysilicon of Doping Phosphorus, and described second semiconductor layer is the polysilicon of doped with boron, and wherein, the concentration of described Doping Phosphorus is different from the concentration of described doped with boron.
Optionally, described first semiconductor layer is p type semiconductor layer, and described second semiconductor layer is n type semiconductor layer.
Optionally, described first semiconductor layer is the polysilicon of doped with boron, and described second semiconductor layer is the polysilicon of Doping Phosphorus, and wherein, the concentration of described Doping Phosphorus is different from the concentration of described doped with boron.
Optionally, described cushion comprises two-layer, and the first cushion is silicon nitride layer, and the second cushion is silicon oxide layer, and equal using plasma strengthens chemical vapor deposition and forms.
Optionally, described first gate electrode layer and second gate electrode layer all adopt sputtering technology to spatter to cross and form.
Optionally, described first insulating barrier forms with the described second equal using plasma enhancing chemical vapor deposition of insulating barrier.
Optionally, also include after forming described metal level: form planarization layer, anode and pixel confining layers.
Accordingly, the present invention also provides for a kind of thin film transistor (TFT), adopts the manufacture method of above-mentioned thin film transistor (TFT) to make.
Compared with prior art, thin film transistor (TFT) provided by the invention and preparation method thereof, by forming the first different semiconductor layer of the doping type being overlapped mutually and the second semiconductor layer on the first insulating barrier, and bottom the first semiconductor layer, form first gate electrode layer, second gate electrode layer is formed at the second semiconductor layer, the semiconductor layer superposition of two kinds of different doping types, first gate electrode layer running voltage is high potential, second gate electrode layer is electronegative potential, can under relatively low gate voltage, obtain bigger operating current, high electronegative potential between first gate electrode layer and second gate electrode layer can form electric field simultaneously, increase the concentration of efficient carrier, thus improving the electric property of thin film transistor (TFT), and the reduction of grid operating current, decrease the probability that gate insulation layer punctures.
Accompanying drawing explanation
The flow chart of the manufacture method of the thin film transistor (TFT) that Fig. 1 provides for one embodiment of the invention.
Each step structural representation of the manufacture method of the thin film transistor (TFT) that Fig. 2～6 provide for one embodiment of the invention.
Detailed description of the invention
For making present disclosure clearly understandable, below in conjunction with Figure of description, present disclosure is described further.Certainly the invention is not limited in this specific embodiment, the general replacement known by those skilled in the art is also covered by protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when describing present example in detail, for the ease of illustrating, schematic diagram, should to this restriction as the present invention not according to general ratio partial enlargement.
The core concept of the present invention is in that, by forming the first different semiconductor layer of the doping type being overlapped mutually and the second semiconductor layer on the first insulating barrier, and bottom the first semiconductor layer, form first gate electrode layer, second gate electrode layer is formed at the second semiconductor layer, the semiconductor layer superposition of two kinds of different doping types, first gate electrode layer running voltage is high potential, second gate electrode layer is electronegative potential, can under relatively low gate voltage, obtain bigger operating current, high electronegative potential between first gate electrode layer and second gate electrode layer can form electric field simultaneously, increase the concentration of efficient carrier, thus improving the electric property of thin film transistor (TFT), and the reduction of grid operating current, decrease the probability that gate insulation layer punctures.
Refer to Fig. 1, the flow chart of the manufacture method of its thin film transistor (TFT) provided for one embodiment of the invention.As it is shown in figure 1, the manufacture method of described thin film transistor (TFT) includes:
Step S01 a: substrate is provided, is formed on cushion；
Step S02: form first gate electrode layer and the first insulating barrier on described cushion；
Step S03: form the first semiconductor layer, source-drain electrode and the second semiconductor layer on described first insulating barrier, wherein, described second semiconductor layer is superimposed with described first semiconductor layer, and both doping types are contrary；
Step S04: form the second insulating barrier and second gate electrode layer at the S03 body structure surface formed；
Step S05: form the 3rd insulating barrier and metal level at the S04 body structure surface formed.
Fig. 2～6 are each step structural representation of the manufacture method of thin film transistor (TFT) in one embodiment of the invention, refer to shown in Fig. 1, and in conjunction with Fig. 2～Fig. 6, describe the present invention in detail and propose the manufacture method of thin film transistor (TFT):
Step S01: provide a substrate 100, is formed on cushion 110, forms structure as shown in Figure 2.
In the present embodiment, described substrate 100 is transparency carrier, and it can be glass substrate or plastic substrate, it is preferable that glass substrate, and its light transmission is good, to ensure the intensity of illumination of the display floater ultimately formed.
Described cushion 110 comprises two-layer, and the first cushion is silicon nitride layer, and the second cushion is silicon oxide layer；Described cushion 110 using plasma strengthens chemical vapour deposition technique (PECVD) deposition and forms；The effect of described cushion 110 is in that the metal ion stopped in substrate 100 diffuses in the raceway groove being subsequently formed.
Step S02: form first gate electrode layer 120 and the first insulating barrier 130 on described cushion 110, form structure as shown in Figure 3.
In the present embodiment, on described cushion 110, metal level is formed by sputtering (sputtering) technique, then pass through mask plate processing procedure and form first gate electrode layer 120, last on described first gate electrode layer 120 and the surface of cushion 110 that do not covered by described first gate electrode layer 120, form the first insulating barrier 130, form described first insulating barrier 130 by plasma enhanced chemical vapor deposition method (PECVD).
Step S03: form the first semiconductor layer 140, source-drain electrode 150 and the second semiconductor layer 160 on described first insulating barrier 130, wherein, described second semiconductor layer 160 is superimposed with described first semiconductor layer 140, and both doping types are contrary, form structure as shown in Figure 4.
In the present embodiment, described first semiconductor layer 140 is n type semiconductor layer, described second semiconductor layer 160 is p type semiconductor layer, and described first semiconductor layer 140 is the polysilicon of Doping Phosphorus, described second semiconductor layer 160 is the polysilicon of doped with boron, and wherein, the concentration of described Doping Phosphorus is different from the concentration of described doped with boron, namely there is certain concentration difference in the concentration of doped with boron and the concentration of Doping Phosphorus, to reduce the compound of two kinds of carriers.
Form described first semiconductor layer 140 method particularly includes: on described first insulating barrier 130, first form low-temperature polycrystalline silicon layer, cover lid layer sensitive material thereon, use mask plate to be exposed, duplicated to described sensitive material by the pattern on mask plate；Then suitable developer solution is utilized to remove part sensitive material so that sensitive material manifests required pattern；Then, by etching technics by part low temperature polycrystalline silicon remove, the technique at this can be selected for wet etching, dry etching or both with the use of；Finally, the sensitive material of remaining patterning is all removed, and then complete the patterning process of low-temperature polycrystalline silicon layer.Low temperature polycrystalline silicon after patterning, in addition it is also necessary to it is carried out doping process, as: inject phosphonium ion, to form N-type semiconductor.
After forming the first semiconductor layer 140, utilize sputtering (sputtering) technique, and form source-drain electrode 150 by etching.
The concrete grammar forming described second quasiconductor 160 is identical with the concrete grammar forming described first quasiconductor 140, but injects boron ion in the low temperature polycrystalline silicon of patterning, to form P-type semiconductor.It should be noted that in the present embodiment, respectively through injecting phosphonium ion with boron ion to form N-type semiconductor and P-type semiconductor, other known ions of those skilled in the art can also be injected to form N-type semiconductor and P-type semiconductor simultaneously.
In an alternative embodiment of the invention, described first semiconductor layer 140 is p type semiconductor layer, described second semiconductor layer 160 is n type semiconductor layer, and described first semiconductor layer 140 is the polysilicon of doped with boron, described second semiconductor layer 160 is the polysilicon of Doping Phosphorus, and wherein, the concentration of described Doping Phosphorus is different from the concentration of described doped with boron, namely there is certain concentration difference in the concentration of doped with boron and the concentration of Doping Phosphorus, to reduce the compound of two kinds of carriers.
Step S04: form the second insulating barrier 170 and second gate electrode layer 180 in the step S03 body structure surface formed, form structure as shown in Figure 5.
In the present embodiment, described second semiconductor layer 160, source-drain electrode 150 and the first uncovered insulating barrier 130 surface form the second insulating barrier 170, forms described second insulating barrier 170 by plasma enhanced chemical vapor deposition method (PECVD)；On described second insulating barrier 170, form metal level by sputtering technology, then pass through mask plate processing procedure and form second gate electrode layer 180.
Described first semiconductor layer 140 is overlapped mutually from described second semiconductor layer 160 and doping type is different, and it is formed with first gate electrode layer 120 in the bottom of described first semiconductor layer 140, it is formed with second gate electrode layer 180 at the top of described second semiconductor layer 160, first gate electrode layer 120 running voltage is high potential, second gate electrode layer 180 is electronegative potential, can under relatively low gate voltage, obtain bigger operating current, high electronegative potential between first gate electrode layer 120 and second gate electrode layer 180 can form electric field simultaneously, increase the concentration of efficient carrier, thus improving the electric property of thin film transistor (TFT), and the reduction of grid operating current, decrease the probability that gate insulation layer punctures.
Step S05: form the 3rd insulating barrier 190 and metal level 200 in the step S04 body structure surface formed, form structure as shown in Figure 6.
In the present embodiment, after forming the 3rd insulating barrier 190 and metal level 200, also include: forming planarization layer 210, anode 220 and pixel confining layers 230, the manufacturing process of this step is identical with the manufacturing process of prior art, therefore repeats no more.
Accordingly, the present invention also provides for a kind of thin film transistor (TFT), adopts the manufacture method of above-mentioned thin film transistor (TFT) to be made, specifically refer to shown in Fig. 6.
In sum, thin film transistor (TFT) provided by the invention and preparation method thereof, by forming the first different semiconductor layer of the doping type being overlapped mutually and the second semiconductor layer on the first insulating barrier, and bottom the first semiconductor layer, form first gate electrode layer, second gate electrode layer is formed at the second semiconductor layer, the semiconductor layer superposition of two kinds of different doping types, first gate electrode layer running voltage is high potential, second gate electrode layer is electronegative potential, can under relatively low gate voltage, obtain bigger operating current, high electronegative potential between first gate electrode layer and second gate electrode layer can form electric field simultaneously, increase the concentration of efficient carrier, thus improving the electric property of thin film transistor (TFT), and the reduction of grid operating current, decrease the probability that gate insulation layer punctures.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, any change that the those of ordinary skill in field of the present invention does according to the disclosure above content, modification, belongs to the protection domain of claims.
Claims (10)
1. the manufacture method of a thin film transistor (TFT), it is characterised in that including:
S01 a: substrate is provided, is formed on cushion；
S02: form first gate electrode layer and the first insulating barrier on described cushion；
S03: form the first semiconductor layer, source-drain electrode and the second semiconductor layer on described first insulating barrier, wherein, described second semiconductor layer is superimposed with described first semiconductor layer, and both doping types are contrary；
S04: form the second insulating barrier and second gate electrode layer at the S03 body structure surface formed；
S05: form the 3rd insulating barrier and metal level at the S04 body structure surface formed.
2. the manufacture method of thin film transistor (TFT) as claimed in claim 1, it is characterised in that described first semiconductor layer is n type semiconductor layer, and described second semiconductor layer is p type semiconductor layer.
3. the manufacture method of thin film transistor (TFT) as claimed in claim 2, it is characterized in that, described first semiconductor layer is the polysilicon of Doping Phosphorus, and described second semiconductor layer is the polysilicon of doped with boron, wherein, the concentration of described Doping Phosphorus is different from the concentration of described doped with boron.
4. the manufacture method of thin film transistor (TFT) as claimed in claim 1, it is characterised in that described first semiconductor layer is p type semiconductor layer, and described second semiconductor layer is n type semiconductor layer.
5. the manufacture method of thin film transistor (TFT) as claimed in claim 4, it is characterized in that, described first semiconductor layer is the polysilicon of doped with boron, and described second semiconductor layer is the polysilicon of Doping Phosphorus, wherein, the concentration of described Doping Phosphorus is different from the concentration of described doped with boron.
6. the manufacture method of thin film transistor (TFT) as claimed in claim 1, it is characterised in that described cushion comprises two-layer, and the first cushion is silicon nitride layer, and the second cushion is silicon oxide layer, equal using plasma strengthens chemical vapor deposition and forms.
7. the manufacture method of thin film transistor (TFT) as claimed in claim 1, it is characterised in that described first gate electrode layer and second gate electrode layer all adopt sputtering technology to spatter to cross and form.
8. the manufacture method of thin film transistor (TFT) as claimed in claim 1, it is characterised in that described first insulating barrier strengthens chemical vapor deposition with the described second equal using plasma of insulating barrier and forms.
9. the manufacture method of thin film transistor (TFT) as claimed in claim 1, it is characterised in that also include after forming described metal level: form planarization layer, anode and pixel confining layers.
10. a thin film transistor (TFT), it is characterised in that adopt the manufacture method of the thin film transistor (TFT) according to any one of claim 1～9 to be made.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110429139A (en) * | 2019-06-19 | 2019-11-08 | 福建华佳彩有限公司 | Binary channels LTPS thin film transistor (TFT) |
| CN113130513A (en) * | 2016-11-01 | 2021-07-16 | 群创光电股份有限公司 | Display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201918431U (en) * | 2010-12-24 | 2011-08-03 | 福建华映显示科技有限公司 | Thin film transistor with Schottky barrier |
| US20120146713A1 (en) * | 2010-12-10 | 2012-06-14 | Samsung Electronics Co., Ltd. | Transistors And Electronic Devices Including The Same |
| CN103178117A (en) * | 2011-12-20 | 2013-06-26 | 上海中科联和显示技术有限公司 | Bipolar type thin film transistor and production method thereof |
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- 2014-12-30 CN CN201410843335.XA patent/CN105810744B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120146713A1 (en) * | 2010-12-10 | 2012-06-14 | Samsung Electronics Co., Ltd. | Transistors And Electronic Devices Including The Same |
| CN201918431U (en) * | 2010-12-24 | 2011-08-03 | 福建华映显示科技有限公司 | Thin film transistor with Schottky barrier |
| CN103178117A (en) * | 2011-12-20 | 2013-06-26 | 上海中科联和显示技术有限公司 | Bipolar type thin film transistor and production method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113130513A (en) * | 2016-11-01 | 2021-07-16 | 群创光电股份有限公司 | Display device |
| CN110429139A (en) * | 2019-06-19 | 2019-11-08 | 福建华佳彩有限公司 | Binary channels LTPS thin film transistor (TFT) |
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Denomination of invention: Thin film transistor and its fabrication method Effective date of registration: 20201221 Granted publication date: 20191025 Pledgee: Xin Xin Finance Leasing Co.,Ltd. Pledgor: KunShan Go-Visionox Opto-Electronics Co.,Ltd. Registration number: Y2020980009652 |
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