CN105808489A - LVDS receiver suitable for SRAM type FPGA - Google Patents
LVDS receiver suitable for SRAM type FPGA Download PDFInfo
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- CN105808489A CN105808489A CN201610103943.6A CN201610103943A CN105808489A CN 105808489 A CN105808489 A CN 105808489A CN 201610103943 A CN201610103943 A CN 201610103943A CN 105808489 A CN105808489 A CN 105808489A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
Abstract
The invention provides an LVDS (Low Voltage Differential Signal) receiver suitable for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array). The receiver consists of a differential input stage, a differential assistance stage, a differential gain stage and an output buffer stage. The differential input stage converts an input differential voltage signal into a differential input current signal; a differential output stage outputs in-phase and inverted voltage signals relative to the input signal of the differential input stage; the differential assistance stage receives the inverted output signal and converts the inverted output signal into a differential assistance current signal; the differential input current and the differential assistance current are combined and output to the differential gain stage; the differential gain stage converts the received current signal into a voltage signal and amplifies the voltage signal, and then the amplified voltage signal is output through the output buffer stage; and the differential assistance stage, the differential gain stage and the output buffer stage form a feedback loop. When the polarity of the differential input voltage is changed, the state switching of the receiver is accelerated by utilizing a feedback effect, so that the receiver has higher working speed. In addition, due to the use of a self-bias structure, no additional bias circuit is required, so that the circuit cost is reduced.
Description
Technical field
The present invention relates to a kind of LVDS receiver suitable in SRAM type FPGA, belong to technical field of integrated circuits.
Background technology
Field programmable gate array (hereinafter referred to as FPGA) can realize different logic functions according to configuration information.The configuration information of the configurable memory array storage user being made up of sram cell is used in SRAM type FPGA, the configuration frame being made up of sram cell can unlimited programming repeatedly, the application making FPGA has great motility, it is particularly suitable for the aerospace engineering characteristic requirement to highly reliable, multi items, the small lot of aerospace device, is widely used in aerospace engineering and is widely used in aerospace engineering.
Along with the progress of processing technique, the density of integrated circuit, performance improve constantly, and protocol type and the speed of the interface support of FPGA are proposed higher requirement by system.Accordingly, it would be desirable to the circuit structure of traditional LVDS receiver is improved, LVDS receiver is made to have higher operating rate.On the other hand; traditional LVDS receiver typically requires use biasing circuit; this does not have any problem in simulation or hybrid digital-analog integrated circuit design environment, but can increase the holistic cost of system under the design environment of the such pure digi-tal of FPGA, it is necessary to be optimized design.
Summary of the invention
Present invention solves the technical problem that for: overcome the deficiencies in the prior art, it is provided that a kind of LVDS receiver suitable in SRAM type FPGA, utilize difference compole feedback effect accelerate receptor state switching, make LVDS receiver have higher operating rate.
The technical scheme that this invention address that is: a kind of LVDS receiver suitable in SRAM type FPGA, this LVDS receiver includes differential input stage, difference compole, differential gain stage and output buffer stage, difference compole, differential gain stage and output buffer stage composition feedback circuit；Input difference voltage signal is converted to Differential input current signal by differential input stage, output buffer stage has the function simultaneously providing input signal homophase and reverse voltage signal with differential input stage, difference compole receives the voltage signal of the input signal inversion with differential input stage, it is converted into difference auxiliary current signal, Differential input current merges output and arrives differential gain stage with difference auxiliary current, the current signal received is converted to voltage signal and is amplified by differential gain stage, then passes through output buffer stage output；When differential input voltage polarity is constant, Differential input current signal and difference auxiliary circuit signal inversion, reduce the differential gain stage output voltage signal amplitude of oscillation, when differential input voltage reversing, feedback circuit hesitation due to difference compole, differential gain stage and output buffer stage composition, Differential input current signal and difference auxiliary current signal homophase, increase output-voltage levels, accelerating output voltage dipole inversion, the biasing of difference auxiliary current signal is less than the biasing of Differential input current signal.
Described differential input stage and difference compole use differential pair that input difference voltage signal is converted to current signal, and the bias current of described difference compole differential pair is less than the bias current of differential input stage differential pair.
Preferably, the bias current of described difference compole is 4:5 with the ratio of the bias current of differential input stage.
nullDescribed difference compole circuit includes PMOS MP3、PMOS MP4a、PMOS MP4b，NMOS tube MN4a、NMOS tube MN4b、NMOS tube MN3，Described PMOS MP3 is made up of identical two PMOS，NMOS tube MN3 is made up of identical two NMOS tube，PMOS MP4a and PMOS MP4b forms PMOS auxiliary differential pair，NMOS tube MN4a and NMOS tube MN4b forms NMOS auxiliary differential pair，The source class of PMOS MP3 is connected to power vd D，The drain electrode of PMOS MP3 is connected to the source electrode of PMOS MP4a and PMOS MP4b，The grid level of PMOS MP3 is connected to PMOS reference voltage，The source class of NMOS tube MN3 is connected to the ground GND，The drain electrode of NMOS tube MN3 is connected to the source electrode of NMOS tube MN4a and NMOS tube MN4b，The grid level of NMOS tube MN3 is connected to NMOS reference voltage，PMOS MP3 and NMOS tube MN3 is as tail current source，Respectively PMOS auxiliary differential to NMOS auxiliary differential to provide bias current，The grid level of PMOS MP4a is connected to the grid of NMOS tube MN4a，Input as difference compole receives the voltage signal VO from output buffer stage，The grid level of PMOS MP4b is connected to the grid of NMOS tube MN4b，Receive the voltage signal VON from output buffer stage simultaneously，PMOS MP4a、PMOS MP4b、NMOS tube MN4a、The drain of NMOS tube MN4b is connected with the output-parallel of Differential Input as the output of difference compole circuit and is input to differential gain stage.
nullDescribed difference compole circuit also includes PMOS MP5、PMOS MP6 and NMOS tube MN5、NMOS tube MN6，Described PMOS reference voltage is provided by PMOS MP5，Described NMOS reference voltage is provided by NMOS tube MN5，The source electrode of PMOS MP5 is connected to power vd D,The grid of PMOS MP5 and the drain electrode of PMOS MP5 link together，It is simultaneously connected with the grid of PMOS MP3、The drain electrode of NMOS tube MN6，The source electrode of NMOS tube MN5 is connected to the ground GND，The grid of NMOS tube MN5 and the drain electrode of NMOS tube MN5 link together，It is simultaneously connected with the grid of NMOS tube MN3、The drain electrode of PMOS MP6，The source electrode of PMOS MP6 is connected to power vd D，The source electrode of NMOS tube MN6 is connected to the ground GND，The grid of PMOS MP6 and the grid of NMOS tube MN6 are commonly connected to bias voltage，Described bias voltage is provided by differential gain stage.
nullDescribed differential gain stage includes PMOS MP7a、PMOS MP7b、PMOS MP8a、PMOS MP8b、NMOS tube MN7a、NMOS tube MN7b、NMOS tube MN8a、NMOS tube MN8b，The source electrode of PMOS MP7a and PMOS MP7b is all connected with power vd D，The source electrode of NMOS tube MP7a and NMOS tube MP7b is all connected with power supply GND，PMOS MP7a、PMOS MP7b、PMOS MP8a、PMOS MP8b、NMOS tube MN7a、NMOS tube MN7b、NMOS tube MN8a、The grid level of NMOS tube MN8b is commonly connected to node PB，The drain electrode of PMOS MP7a and the source electrode of PMOS MP8a are connected to node P1、The drain electrode of PMOS MP7b and the source electrode of PMOS MP8b are connected to node P3、The source electrode of NMOS tube MN8a and the drain electrode of NMOS tube MN7a are connected to node P3、The source electrode of NMOS tube MN8b and the drain electrode of NMOS tube MN7b are connected to node P4,P1、P2、P3、P4 node is the input of differential gain stage，Receive the signal input of differential input stage and differential feedback level，The drain electrode of PMOS MP8a and the drain electrode of NMOS tube MN8a are commonly connected to node PB，The drain electrode of PMOS MP8b and the drain electrode of NMOS tube MN8b are commonly connected to node PO，Output as differential gain stage，Output is to exporting buffer stage.
Described node PB is split as two node PBP and PBN, the grid of the PMOS that all and former node PB is connected is defined as node PBP, the grid of the NMOS tube that all and former node PB is connected is defined as node PBN, when node PBP connects power vd D, node PBN connection ground GND, disabling receptor, when node PBP and node PBN links together, enable receptor.
The present invention having the beneficial effects that compared with prior art:
(1) LVDS receiver of the present invention uses difference compole, differential gain stage and output buffer stage composition feedback control loop, uses feedback to accelerate the state switching of receptor, makes LVDS receiver have higher operating rate.
(2) LVDS receiver of the present invention uses automatic biasing structure, use the bias voltage that differential gain stage provides differential input stage and difference compole to be biased simultaneously, do not need any type of extra biasing circuit, save circuit area, reduce the holistic cost realizing LVDS receiver.
(3) in LVDS receiver of the present invention, difference compole circuit also includes reference voltage auxiliary circuit, this reference voltage auxiliary circuit provides controlled PMOS reference voltage and NMOS reference voltage for difference compole, the grid width that can pass through PMOS MP5, PMOS MP6 in adjusting reference voltage auxiliary circuit and NMOS tube MN5, NMOS tube MN6 regulates the ratio of the bias current of difference compole and the bias current of differential input stage, and the state switch speed making receptor is best.
(4) LVDS receiver of the present invention can carry out enabling control very easily.Time disabled, LVDS receiver of the present invention is in zero current condition.
Accompanying drawing explanation
Fig. 1 is the LVDS receiver circuit diagram of the present invention；
Fig. 2 is the LVDS receiver circuit operation principle schematic diagram of the present invention；
Fig. 3 is that end adds key event V diagram during difference compole；
Fig. 4 is key event V diagram after addition difference compole.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
The LVDS receiver circuit structure of the present invention is as shown in Figure 1.This LVDS receiver includes differential input stage, difference compole, differential gain stage and four parts of output buffer stage.Input difference voltage signal is converted to current signal by differential input stage, the current signal that differential input stage exports is converted to voltage signal and is amplified by differential gain stage, voltage signal after amplification is by exporting buffer stage output, output buffer stage is used for driving capacitive load, the output signal of output buffer stage is converted to current signal by difference compole, and by the current signal Parallel opertation of this current signal and differential input stage output to differential gain stage, difference compole, differential gain stage and output buffer stage composition feedback circuit.This LVDS receiver has two inputs: in-phase input end INN and inverting input INP；One outfan, for VO.
Differential input stage includes: PMOS MP1, PMOS MP2a, PMOS MP2b, NMOS tube MN1, NMOS tube MN2a, NMOS tube MN2b.For realizing good coupling, described PMOS MP1 is made up of identical two PMOS, and NMOS tube MN1 is made up of identical two NMOS tube.PMOS MP2a and PMOS MP2b forms PMOS auxiliary differential pair, NMOS tube MN2a and NMOS tube MN2b and forms NMOS auxiliary differential pair.The source class of PMOS MP1 is connected to the drain electrode of power vd D, PMOS MP1 and is connected to the source electrode of PMOS MP2a and PMOS MP2b, and the grid level of PMOS MP1 is connected to bias voltage, and this bias voltage is provided by differential gain stage；The source class of NMOS tube MN1 is connected to the ground the drain electrode of GND, NMOS tube MN1 and is connected to the source electrode of NMOS tube MN2a and NMOS tube MN2b, and the grid level of NMOS tube MN1 is connected to bias voltage, and this bias voltage is also provided by differential gain stage；PMOS MP1 and NMOS tube MN1 is as tail current source, and respectively PMOS auxiliary differential biases providing with NMOS auxiliary differential.The grid of PMOS MP2a and NMOS tube MN2a is commonly connected to the input INP of LVDS receiver；The grid of PMOS MP2b and NMOS tube MN2b is commonly connected to the input INN of LVDS receiver；PMOS MP2a, PMOS MP2b, NMOS tube MN2a, NMOS tube MN2b drain electrode be connected to differential gain stage as the output of differential input stage.
Difference compole includes: PMOS MP3, PMOS MP4a, PMOS MP4b, NMOS tube MN4a, NMOS tube MN4b, NMOS tube MN3 and the reference voltage auxiliary circuit being made up of PMOS MP5, PMOS MP6, NMOS tube MN5, NMOS tube MN6.For realizing good coupling, described PMOS MP3 is made up of identical two PMOS, and NMOS tube MN3 is made up of identical two NMOS tube.PMOS MP4a and PMOS MP4b forms PMOS auxiliary differential pair, NMOS tube MN4a and NMOS tube MN4b and forms NMOS auxiliary differential pair.The source class of PMOS MP3 is connected to the drain electrode of power vd D, PMOS MP3 and is connected to the source electrode of PMOS MP4a and PMOS MP4b, and the grid level of PMOS MP3 is connected to PMOS reference voltage；The source class of NMOS tube MN3 is connected to the ground the drain electrode of GND, NMOS tube MN3 and is connected to the source electrode of NMOS tube MN4a and NMOS tube MN4b, and the grid level of NMOS tube MN3 is connected to NMOS reference voltage；PMOS MP3 and NMOS tube MN3 is as tail current source, and respectively PMOS auxiliary differential biases providing with NMOS auxiliary differential.The grid level of PMOS MP4a is connected to the grid of NMOS tube MN4a, input as difference compole receives the voltage signal VO from output buffer stage, the grid level of PMOS MP4b is connected to the grid of NMOS tube MN4b, receives the voltage signal VON from output buffer stage simultaneously；PMOS MP4a, PMOS MP4b, NMOS tube MN4a, NMOS tube MN4b drain be connected with the output-parallel of Differential Input as the output of difference compole circuit and be input to differential gain stage.Reference voltage auxiliary circuit provides controlled PMOS reference voltage and NMOS reference voltage for difference compole, and described PMOS reference voltage is provided by PMOS MP5, and described NMOS reference voltage is provided by NMOS tube MN5.The drain electrode of grid and PMOS MP5 that the source electrode of PMOS MP5 is connected to power vd D, PMOS MP5 links together, and is simultaneously connected with the drain electrode of the grid of PMOS MP3, NMOS tube MN6；The drain electrode of grid and NMOS tube MN5 that the source electrode of NMOS tube MN5 is connected to the ground GND, NMOS tube MN5 links together, and is simultaneously connected with the drain electrode of the grid of NMOS tube MN3, PMOS MP6；The source electrode of PMOS MP6 is connected to the grid of power vd D, PMOS MP6 and is connected to bias voltage, and this bias voltage is also provided by differential gain stage；The source electrode of NMOS tube MN6 is connected to the ground the grid of GND, NMOS tube MN6 and is connected to bias voltage, and this bias voltage is also provided by differential gain stage.
Differential gain stage includes: differential gain stage includes PMOS MP7a, PMOS MP7b, PMOS MP8a, PMOS MP8b, NMOS tube MN7a, NMOS tube MN7b, NMOS tube MN8a, NMOS tube MN8b.The source electrode of PMOS MP7a and PMOS MP7b is all connected with the source electrode of power vd D, NMOS tube MP7a and NMOS tube MP7b and is all connected with ground GND；PMOS MP7a, PMOS MP7b, PMOS MP8a, PMOS MP8b, NMOS tube MN7a, NMOS tube MN7b, NMOS tube MN8a, NMOS tube MN8b grid level be commonly connected to node PB；The drain electrode of PMOS MP7a and the source electrode of PMOS MP8a are connected to node P1, the drain electrode of PMOS MP7b is connected to node P3 with the source electrode of PMOS MP8b, the source electrode of NMOS tube MN8a is connected to node P3 with the drain electrode of NMOS tube MN7a, the source electrode of NMOS tube MN8b is connected to node P4 with the drain electrode of NMOS tube MN7b, tetra-nodes of P1, P2, P3, P4 are the input of differential gain stage, receive the signal parallel connection input of differential input stage and differential feedback level；The drain electrode of PMOS MP8a and the drain electrode of NMOS tube MN8a are commonly connected to node PB；The drain electrode of PMOS MP8b and the drain electrode of NMOS tube MN8b are commonly connected to node PO, and as the output of differential gain stage, output is to exporting buffer stage.
Output buffer stage includes: PMOS MP9, PMOS MP10, PMOS MP11, NMOS tube MN9, NMOS tube MN10, NMOS tube MN11.The grid of PMOS MP9 connects the grid of NMOS tube MN9, is simultaneously connected with the output PO of differential gain；The source electrode of PMOS MP9 connects power vd D；The drain electrode of PMOS MP9 connects the grid of the grid of PMOS MP10, the drain electrode of NMOS tube MN9, NMOS tube MN10.The source electrode of PMOS MP10 connects power vd D；The drain electrode of PMOS MP10 connects the grid of the grid of PMOS MP11, the drain electrode of NMOS tube MN10, NMOS tube MN11, and this node is simultaneously as reversed-phase output signal VON.The source electrode of PMOS MP11 connects power vd D.The source electrode of NMOS tube MN9 connects ground GND.The source electrode of NMOS tube MN10 connects ground GND.The source electrode of NMOS tube MN11 connects ground GND.
The operation principle of LVDS receiver differential input stage of the present invention and differential gain stage can be illustrated with Fig. 2.The fully differential folded-cascode operational amplifier of Fig. 2 upper left-hand uses nmos differential to as input stage, and the fully differential folded-cascode operational amplifier of upper right uses PMOS differential pair as input stage.PMOS MP2a and PMOS MP2b composition input PMOS differential pair；NMOS tube MN2a and NMOS tube MN2b composition input nmos differential pair；PMOS MP1 and NMOS tube MN1 is tail current source.PMOS MP7a and PMOS MP8a, PMOS MP7b and PMOS MP8b, NMOS tube MN7a and NMOS tube MN8a, NMOS tube MN7b and NMOS tube MN8b separately constitute current source, and 4 current sources collectively constitute differential gain stage.In order to realize the function of circuit, it is desirable to provide 4 extra bias voltages: VBias1, VBias2, VBias3, VBias4.Use the nmos differential input signal to cannot process closely level as input stage, use PMOS differential pair cannot process the input signal close to power level as input stage.In order to make receptor can process input signal all situations between ground level and power level, it is possible to two amplifiers in Fig. 2 top are merged, it is clear that gain stage can share, as shown in the middle part of Fig. 2 after merging.In order to realize the function of circuit, it is still desirable to provide these 4 extra bias voltages of VBias1, VBias2, VBias3, VBias4.After using automatic biasing structure, circuit does not need any extra biasing circuit, and the concrete practice for being all connected to PB node by VBias1, VBias2, VBias3, VBias4.After application automatic biasing structure, circuit structure is as shown in the lower part of Figure 2.
Output buffer stage is used for driving capacitive load, is made up of multistage reverser.Optimum reverser progression N is determined by following formula: N=ln (load capacitance/input capacitance)；Optimum reverser dimension scale relation is e (end of natural logrithm) times.The output buffer stage that the LVDS receiver of the present invention uses is made up of three grades of phase inverters: the phase inverter that PMOS MP9, NMOS tube MN9 form；The phase inverter of PMOS MP10, NMOS tube MN10 composition；The phase inverter of PMOS MP11, NMOS tube MN11 composition.The output buffer stage of the present invention also has the function providing reversed-phase output signal VON.
Differential input stage, differential gain stage and output buffer stage can realize the function of LVDS receiver, and difference compole is for improving the operating rate of LVDS receiver of the present invention.Difference compole is similar to the circuit structure of differential input stage, and difference has be input signal that difference compole receive with the input signal of differential input stage have contrary phase place at two: one；Two is the bias current bias current less than differential input stage of difference compole.Difference compole, differential gain stage and output buffer stage collectively form feedback circuit, utilize feedback effect to accelerate the state switching of receptor, in its effect concentrated reflection control to node PO voltage.On the one hand, when input difference voltage stabilization, the input signal received due to difference compole is contrary with the input signal phase of differential input stage, and the duty of difference compole is contrary with differential input stage, avoid device to enter deep linear zone, reduce the voltage swing of node PO；On the other hand, when input difference voltage changes, owing to difference compole duty exists delayed, make difference compole and differential input stage jointly change the voltage of node PO, accelerate the change of the voltage of node PO.Add front and back node PO below by contrast difference compole, the voltage of node VO illustrates operation principle.
When end increases difference compole, key event signal level is as it is shown on figure 3, illustrate for input signal INN voltage time initial more than INP voltage.When input signal INN voltage is more than INP voltage, node PO voltage is close to power vd D, node VO voltage closely GND.When inputting signal INP and changing with INN voltage, node PO is corresponding to node VO voltage to be changed.In the t1 moment, input signal INP voltage starts more than INN voltage, and now node PO voltage begins to decline.In the t2 moment, node PO voltage is down to the half of power vd D voltage.Now, node VO voltage begins to ramp up.In the t3 moment, node VO voltage rises to the voltage close to power vd D, and LVDS receiver completion status is changed.After input signal is again stable, node PO and node VO voltage stabilization.After stable, node PO voltage closely GND, node VO voltage are close to power vd D.
After increasing difference compole, key event signal level as shown in Figure 4, illustrates for input signal INN voltage time initial more than INP voltage equally.When input signal INN voltage is more than INP voltage, the voltage of node PO can more than the half of power supply vdd voltage, VO voltage still closely GND.Now, owing to VO is ground GND, in PMOS MP4a, electric current increases, and counteracts the effect of PMOS MP2a to a certain extent.In like manner, in PMOS MP4b, electric current increases, and counteracts the effect of PMOS MP2b to a certain extent；In NMOS tube MN4a, electric current increases, and counteracts the effect of NMOS tube MN2a to a certain extent；In NMOS tube MP4b, electric current increases, and counteracts the effect of NMOS tube MN2b to a certain extent.Final result be node PO voltage can the stable position on power vd D half is slightly biased, each device will not enter deep linear zone.When INP and INN voltage changes, node PO is corresponding to node VO voltage to be changed.In the t1 moment, input signal INP voltage starts more than INN voltage, and now node PO voltage begins to decline.In the t2 moment, node PO voltage and the half being down to power vd D, now, node VO voltage begins to ramp up.On the one hand, the half of the burning voltage of PO closely power supply vdd voltage；On the other hand, due to VO still end change state, difference compole changes the voltage of PO with differential input stage combined effect.After the two factor causes addition difference compole, the t2 moment shifts to an earlier date significantly.In the t3 moment, node VO voltage rises to close to power vd D, and LVDS receiver completion status is changed.When input signal is stablized again, the voltage of node PO and node VO recovers stable.The voltage of node PO can stable position on power vd D half is slightly biased again, node VO voltage is close to power vd D.
PMOS MP5, NMOS tube MN6, NMOS tube MN5, PMOS MP6 are for determining the bias current of difference compole.If the bias current of difference compole is excessive, feedback circuit will make receptor be in oscillatory regime, it is impossible to realizes the function of receptor；If the bias current of difference compole is too small, feedback circuit declines, receiver operation speed declines.Preferably, the ratio of the bias current of difference compole Yu the bias current of input difference pair is set as 4:5 by the present invention.
To increase ena-bung function in circuit, then node PB can be split as two node PBP and PBN: the grid of the PMOS that all and former node PB is connected is defined as node PBP, and the grid of the NMOS tube that all and former node PB is connected is defined as node PBN.During disabling receptor, node PBP is connected power vd D, node PBN is connected ground GND；When enabling receptor, node PBP and node PBN is linked together.
The content not being described in detail in this specification belongs to the known technology of professional and technical personnel in the field.
Claims (7)
1. the LVDS receiver being applicable to SRAM type FPGA, it is characterised in that include differential input stage, difference compole, differential gain stage and output buffer stage, difference compole, differential gain stage and output buffer stage composition feedback circuit；Input difference voltage signal is converted to Differential input current signal by differential input stage, output buffer stage has the function simultaneously providing input signal homophase and reverse voltage signal with differential input stage, difference compole receives the voltage signal of the input signal inversion with differential input stage, it is converted into difference auxiliary current signal, Differential input current merges output and arrives differential gain stage with difference auxiliary current, the current signal received is converted to voltage signal and is amplified by differential gain stage, then passes through output buffer stage output；When differential input voltage polarity is constant, Differential input current signal and difference auxiliary circuit signal inversion, reduce the differential gain stage output voltage signal amplitude of oscillation, when differential input voltage reversing, feedback circuit hesitation due to difference compole, differential gain stage and output buffer stage composition, Differential input current signal and difference auxiliary current signal homophase, increase output-voltage levels, accelerating output voltage dipole inversion, the biasing of difference auxiliary current signal is less than the biasing of Differential input current signal.
2. a kind of LVDS receiver suitable in SRAM type FPGA according to claim 1, it is characterized in that described differential input stage and difference compole use differential pair that input difference voltage signal is converted to current signal, the bias current of described difference compole differential pair is less than the bias current of differential input stage differential pair.
3. a kind of LVDS receiver suitable in SRAM type FPGA according to claim 2, it is characterised in that the ratio of the bias current of described difference compole and the bias current of differential input stage is 4:5.
null4. a kind of LVDS receiver suitable in SRAM type FPGA according to claim 2，It is characterized in that described difference compole circuit includes PMOS MP3、PMOS MP4a、PMOS MP4b，NMOS tube MN4a、NMOS tube MN4b、NMOS tube MN3，Described PMOS MP3 is made up of identical two PMOS，NMOS tube MN3 is made up of identical two NMOS tube，PMOS MP4a and PMOS MP4b forms PMOS auxiliary differential pair，NMOS tube MN4a and NMOS tube MN4b forms NMOS auxiliary differential pair，The source class of PMOS MP3 is connected to power vd D，The drain electrode of PMOS MP3 is connected to the source electrode of PMOS MP4a and PMOS MP4b，The grid level of PMOS MP3 is connected to PMOS reference voltage，The source class of NMOS tube MN3 is connected to the ground GND，The drain electrode of NMOS tube MN3 is connected to the source electrode of NMOS tube MN4a and NMOS tube MN4b，The grid level of NMOS tube MN3 is connected to NMOS reference voltage，PMOS MP3 and NMOS tube MN3 is as tail current source，Respectively PMOS auxiliary differential to NMOS auxiliary differential to provide bias current，The grid level of PMOS MP4a is connected to the grid of NMOS tube MN4a，Input as difference compole receives the voltage signal VO from output buffer stage，The grid level of PMOS MP4b is connected to the grid of NMOS tube MN4b，Receive the voltage signal VON from output buffer stage simultaneously，PMOS MP4a、PMOS MP4b、NMOS tube MN4a、The drain of NMOS tube MN4b is connected with the output-parallel of Differential Input as the output of difference compole circuit and is input to differential gain stage.
null5. a kind of LVDS receiver suitable in SRAM type FPGA according to claim 4，It is characterized in that described difference compole circuit also includes PMOS MP5、PMOS MP6 and NMOS tube MN5、NMOS tube MN6，Described PMOS reference voltage is provided by PMOS MP5，Described NMOS reference voltage is provided by NMOS tube MN5，The source electrode of PMOS MP5 is connected to power vd D,The grid of PMOS MP5 and the drain electrode of PMOS MP5 link together，It is simultaneously connected with the grid of PMOS MP3、The drain electrode of NMOS tube MN6，The source electrode of NMOS tube MN5 is connected to the ground GND，The grid of NMOS tube MN5 and the drain electrode of NMOS tube MN5 link together，It is simultaneously connected with the grid of NMOS tube MN3、The drain electrode of PMOS MP6，The source electrode of PMOS MP6 is connected to power vd D，The source electrode of NMOS tube MN6 is connected to the ground GND，The grid of PMOS MP6 and the grid of NMOS tube MN6 are commonly connected to bias voltage，Described bias voltage is provided by differential gain stage.
null6. a kind of LVDS receiver suitable in SRAM type FPGA according to any one of claim 1 to 5，It is characterized in that described differential gain stage includes PMOS MP7a、PMOS MP7b、PMOS MP8a、PMOS MP8b、NMOS tube MN7a、NMOS tube MN7b、NMOS tube MN8a、NMOS tube MN8b，The source electrode of PMOS MP7a and PMOS MP7b is all connected with power vd D，The source electrode of NMOS tube MP7a and NMOS tube MP7b is all connected with power supply GND，PMOS MP7a、PMOS MP7b、PMOS MP8a、PMOS MP8b、NMOS tube MN7a、NMOS tube MN7b、NMOS tube MN8a、The grid level of NMOS tube MN8b is commonly connected to node PB，The drain electrode of PMOS MP7a and the source electrode of PMOS MP8a are connected to node P1、The drain electrode of PMOS MP7b and the source electrode of PMOS MP8b are connected to node P3、The source electrode of NMOS tube MN8a and the drain electrode of NMOS tube MN7a are connected to node P3、The source electrode of NMOS tube MN8b and the drain electrode of NMOS tube MN7b are connected to node P4,P1、P2、P3、P4 node is the input of differential gain stage，Receive the signal input of differential input stage and differential feedback level，The drain electrode of PMOS MP8a and the drain electrode of NMOS tube MN8a are commonly connected to node PB，The drain electrode of PMOS MP8b and the drain electrode of NMOS tube MN8b are commonly connected to node PO，Output as differential gain stage，Output is to exporting buffer stage.
7. a kind of LVDS receiver suitable in SRAM type FPGA according to claim 6, it is characterized in that described node PB is split as two node PBP and PBN, the grid of the PMOS that all and former node PB is connected is defined as node PBP, the grid of the NMOS tube that all and former node PB is connected is defined as node PBN, when node PBP connects power vd D, node PBN connection ground GND, disabling receptor, when node PBP and node PBN links together, enables receptor.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373278B1 (en) * | 1999-01-08 | 2002-04-16 | Altera Corporation | LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device |
| US20120286873A1 (en) * | 2011-05-13 | 2012-11-15 | Skyworks Solutions, Inc. | Apparatus and methods for biasing power amplifiers |
| CN103019994A (en) * | 2012-12-21 | 2013-04-03 | 北京电子工程总体研究所 | Variable Baud rate serial communication interface circuit based on FPGA (field programmable gate array) |
| CN103607337A (en) * | 2013-12-04 | 2014-02-26 | 中国科学院上海微系统与信息技术研究所 | Bus signal receiver |
-
2016
- 2016-02-26 CN CN201610103943.6A patent/CN105808489B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373278B1 (en) * | 1999-01-08 | 2002-04-16 | Altera Corporation | LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device |
| US20120286873A1 (en) * | 2011-05-13 | 2012-11-15 | Skyworks Solutions, Inc. | Apparatus and methods for biasing power amplifiers |
| CN103019994A (en) * | 2012-12-21 | 2013-04-03 | 北京电子工程总体研究所 | Variable Baud rate serial communication interface circuit based on FPGA (field programmable gate array) |
| CN103607337A (en) * | 2013-12-04 | 2014-02-26 | 中国科学院上海微系统与信息技术研究所 | Bus signal receiver |
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