CN105808471A - FPGA (Field Programmable Gate Array) chip time delay information storage method and device, and FPGA chip time delay information access method and device - Google Patents

FPGA (Field Programmable Gate Array) chip time delay information storage method and device, and FPGA chip time delay information access method and device Download PDF

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CN105808471A
CN105808471A CN201410855821.3A CN201410855821A CN105808471A CN 105808471 A CN105808471 A CN 105808471A CN 201410855821 A CN201410855821 A CN 201410855821A CN 105808471 A CN105808471 A CN 105808471A
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point
elementary cell
fpga chip
destination
distance
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CN105808471B (en
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靳松
蒋中华
吴鑫
黄攀
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Capital Microelectronics Beijing Technology Co Ltd
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Capital Microelectronics Beijing Technology Co Ltd
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Abstract

The embodiment of the invention discloses a FPGA (Field Programmable Gate Array) chip time delay information storage method and device, and a FPGA chip time delay information access method and device, and is applied to the technical field of hardware design. The storage expenditure of time delay information is reduced. Correspondingly, the access speed of the time delay information can be improved. The FPGA chip time delay information storage method of the embodiment of the invention comprises the following steps: judging whether each row on a FPGA chip only contains one type of basic unit or not or whether each line on the FPGA chip only contains one type of basic unit or not; if each row only contains the same type of basic unit, independently storing time delay information between the basic unit on the line of the top end and all basic units on the FPGA chip as well as time delay information between the basic unit on the line of the bottom end and all basic units on the FPGA chip; and if each line on the FPGA chip only contains the same type of basic unit, independently storing time delay information between the basic unit on the row of the leftmost end on the FPGA chip and all basic units on the FPGA chip as well as time delay information between the basic unit on the row of the rightmost end on the FPGA chip and all basic units on the FPGA chip.

Description

The storage of fpga chip delayed data, access method and device
Technical field
The present invention relates to hardware design technique field, particularly relate to the storage of fpga chip delayed data, access method and device.
Background technology
FPGA (Field-ProgrammableGateArray), i.e. field programmable gate array, is the product of development further on the basis of the programming devices such as PAL, GAL, CPLD.It is to occur as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the shortcoming that original programming device gate circuit number is limited, thus has been widely applied.
Fpga chip is utilized to realize certain circuit function, the function to realize is needed to be converted first into RTL (RegisterTransferLevel, register transfer level circuit) design, then re-map in the resource of fpga chip, the resources such as such as LUT (Look-Up-Table shows look-up table).The placement-and-routing of chip makes physical resource (elementary cell) is carried out, it is achieved the circuit of design finally according to placement algorithm.
The placement-and-routing of FGPA chip except the circuit counting speed requiring design is fast, save resource except, also to follow the design principle that time delay is little, so to take into full account the time delay of system when carrying out the placement-and-routing of fpga chip.
Summary of the invention
But, the present inventor finds in research process, in existing application, the delayed data (including two elementary cells coordinate on fpga chip and the delay value between two elementary cells) of any two elementary cell (such as EMB (embedded system) or PLB (pipeline burst type buffer memory) etc.) on fpga chip meeting storage chip itself, when utilizing fpga chip to design, the system delay of correspondence just can be obtained according to the delayed data prestored, to select the signal route of optimum when doing placement-and-routing according to placement algorithm.Owing to the elementary cell quantity of fpga chip is relatively big, storing the delayed data of any two elementary cell (such as EMB or PLB etc.) on fpga chip in prior art needs very big memory space, and storage overhead is bigger.
For this, it is also very desirable to the storage method of the fpga chip delayed data of a kind of improvement, access method and device.To solve the technical problem that in prior art, fpga chip delayed data storage overhead is big.
In the first aspect of embodiment of the present invention, it is provided that a kind of fpga chip delayed data storage method, for instance may include that
Judge whether the every string on fpga chip only comprises a type of elementary cell, or whether the every a line on fpga chip only comprises a type of elementary cell；
If every string only comprises same type of elementary cell, then elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip respectively；
If every a line only comprises same type of elementary cell, then store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange respectively.
Preferably, described method also includes:
When every string on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical above and below；
If symmetrical above and below, chip the top or bottom a line are designated as reference line, the elementary cell on storage reference line and the delayed data of all elementary cells on fpga chip.
Preferably, when the every a line on fpga chip only comprising a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical；
If symmetrical, chip high order end or low order end string are designated as reference columns, store the delayed data of the elementary cell on reference columns and all elementary cells.
In the second aspect of embodiment of the present invention, it is provided that the access method of fpga chip delayed data, including:
Will be located in signal to flow to two elementary cells to be checked of initiating terminal and be designated as source point and point of destination respectively；
When every string on fpga chip only comprises a type of elementary cell, perform the first reading flow process；
Described first reads flow process includes:
If the row coordinate of point of destination is more than the row coordinate of source point, then by point of destination distance to direction, the bottom translation source point row coordinate size of row in column；Read the delay value between the elementary cell at place after the elementary cell of source point column bottom and point of destination translation；
Otherwise then to the top orientation of row, point of destination being translated the first distance in column, described first distance is the distance of source point to fpga chip a line topmost；Read the delay value between the elementary cell at place after the elementary cell on source point column top prestored and point of destination translation；
When the every a line of fpga chip only comprises a type of elementary cell, perform the second reading flow process；
Described second reads flow process includes:
If the row-coordinate of point of destination is more than the row-coordinate of source point, then by point of destination distance to the left end direction translation source point row-coordinate size of row on being expert at；Read the elementary cell of the be expert at left end of described source point prestored and point of destination translate after place elementary cell between delay value；
Otherwise then to the right-hand member direction of row, point of destination being translated second distance on being expert at, described second distance is the source point distance to fpga chip low order end string；Read the elementary cell of the be expert at right-hand member of described source point prestored and point of destination translate after place elementary cell between delay value.
Preferably, described method also includes:
When the every string of fpga chip only comprises a type of elementary cell, if all of elementary cell is symmetrical above and below on fpga chip, performs third reading and take flow process；
Described third reading takes flow process and includes:
If point of destination less than the distance of point of destination to reference line, is then translated the 3rd distance, the distance that described 3rd distance is source point to reference line to the distance of reference line by source point in column to reference line direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference line point of intersection and point of destination translation；
Otherwise then determine respectively source point and point of destination relative to fpga chip row to the symmetrical point of destination of the first of line of symmetry the symmetrical source point and first；First symmetrical point of destination is translated to reference line direction the 4th distance in column, and described 4th distance is the first symmetrical source point distance to reference line；Read the delay value between the elementary cell at place after the elementary cell of the prestore first symmetrical source point column and reference line point of intersection and the first symmetrical point of destination translation；
Wherein, described with reference to behavior fpga chip the top or bottom a line.
Preferably, described method also includes:
When the every a line of fpga chip only comprises a type of elementary cell, if all of elementary cell is symmetrical on fpga chip, perform the 4th reading flow process；
Described 4th reads flow process includes:
If point of destination less than the distance of point of destination to reference columns, is translated the 5th distance, the distance that described 5th distance is source point to reference columns to the distance of reference columns by source point on being expert to reference columns direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference columns point of intersection and point of destination translation；
Otherwise then determine that source point and point of destination arrange to the second of line of symmetry the symmetrical source point and the second symmetrical point of destination relative to fpga chip respectively；To reference columns, the second symmetrical point of destination is translated the 6th distance on being expert at, and described 6th distance is the second symmetrical source point distance to reference columns；Read the delay value between the elementary cell at place after the elementary cell of the prestore second symmetrical source point and reference columns point of intersection and the second symmetrical point of destination translation；
Wherein, described reference is classified as fpga chip high order end or low order end string.
In the third aspect of embodiment of the present invention, it is provided that the storage device of a kind of fpga chip delayed data, described device includes:
Whether the first judge module, for judging whether only to comprise on the every string on fpga chip a type of elementary cell, or only comprise a type of elementary cell in the every a line on fpga chip；
First memory module, when every string only comprising same type of elementary cell in fpga chip, elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip respectively；
When every a line only comprises same type of elementary cell, store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange respectively.
Preferably, described device also includes: the second judge module, when the every string on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical above and below；
Second memory module, when all elementary cells on fpga chip are distributed symmetrical above and below, is designated as reference line, the elementary cell on storage reference line and the delayed data of all elementary cells on fpga chip by chip the top or bottom a line.
Preferably, described device also includes:
3rd judge module, when the every a line on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical；
3rd memory module, when all elementary cells on fpga chip are distributed symmetrical, is designated as chip high order end or low order end string reference columns, stores the delayed data of the elementary cell on reference columns and all elementary cells.
In the fourth aspect of embodiment of the present invention, it is provided that the access device of a kind of fpga chip delayed data, including:
Mark module, two elementary cells to be checked flowing to initiating terminal for will be located in signal are designated as source point and point of destination respectively；
First performs module, is used for performing the first reading flow process；Described first reads flow process includes:
If the row coordinate of point of destination is more than the row coordinate of source point, then by point of destination distance to direction, the bottom translation source point row coordinate size of row in column；Read the delay value between the elementary cell at place after the elementary cell of source point column bottom and point of destination translation；
Otherwise then to the top orientation of row, point of destination being translated the first distance in column, described first distance is the distance of source point to fpga chip a line topmost；Read the delay value between the elementary cell at place after the elementary cell on source point column top prestored and point of destination translation；
First trigger module, when the every string on fpga chip only comprises a type of elementary cell, triggers the first execution module and performs the first reading flow process；
Second performs module, is used for performing the second reading flow process, and described second reads flow process includes:
If the row-coordinate of point of destination is more than the row-coordinate of source point, then by point of destination distance to the left end direction translation source point row-coordinate size of row on being expert at；Read the elementary cell of the be expert at left end of described source point prestored and point of destination translate after place elementary cell between delay value；
Otherwise then to the right-hand member direction of row, point of destination being translated second distance on being expert at, described second distance is the source point distance to fpga chip low order end string；Read the elementary cell of the be expert at right-hand member of described source point prestored and point of destination translate after place elementary cell between delay value；
Second trigger module, when only comprising a type of elementary cell in the every a line of fpga chip, triggers the second execution module and performs the second reading flow process.
Preferably, described device also includes:
3rd performs module, is used for performing third reading and takes flow process；Described third reading takes flow process and includes:
If point of destination less than the distance of point of destination to reference line, is then translated the 3rd distance, the distance that described 3rd distance is source point to reference line to the distance of reference line by source point in column to reference line direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference line point of intersection and point of destination translation；
Otherwise then determine respectively source point and point of destination relative to fpga chip row to the symmetrical point of destination of the first of line of symmetry the symmetrical source point and first；First symmetrical point of destination is translated to reference line direction the 4th distance in column, and described 4th distance is the first symmetrical source point distance to reference line；Read the delay value between the elementary cell at place after the elementary cell of the prestore first symmetrical source point column and reference line point of intersection and the first symmetrical point of destination translation；
Wherein, described with reference to behavior fpga chip the top or bottom a line；
3rd trigger module, when only comprising a type of elementary cell on the every string of fpga chip, if all of elementary cell is symmetrical above and below on fpga chip, triggers the 3rd execution module execution third reading and takes flow process.
Preferably, described device also includes:
4th performs module, is used for performing the 4th reading flow process；Described 4th reads flow process includes:
If point of destination less than the distance of point of destination to reference columns, is translated the 5th distance, the distance that described 5th distance is source point to reference columns to the distance of reference columns by source point on being expert to reference columns direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference columns point of intersection and point of destination translation；
Otherwise then determine that source point and point of destination arrange to the second of line of symmetry the symmetrical source point and the second symmetrical point of destination relative to fpga chip respectively；To reference columns, the second symmetrical point of destination is translated the 6th distance on being expert at, and described 6th distance is the second symmetrical source point distance to reference columns；Read the delay value between the elementary cell at place after the elementary cell of the prestore second symmetrical source point and reference columns point of intersection and the second symmetrical point of destination translation；
Wherein, described reference is classified as fpga chip high order end or low order end string；
4th trigger module, when only comprising a type of elementary cell in the every a line of fpga chip, if all of elementary cell is symmetrical on fpga chip, triggers the 4th execution module and performs the 4th reading flow process.
As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that
In embodiments of the present invention, the delay value of same kind of elementary cell is identical, so the storage of delayed data can be optimized, concrete, when the every string of fpga chip only comprises a type of elementary cell, elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip；When every a line only comprises a type of elementary cell, store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange.Compared with prior art, the expense of the delayed data of elementary cell on the region outside storage fpga chip marginal portion is decreased.
Accompanying drawing explanation
Reading detailed description below by reference accompanying drawing, above-mentioned and other purposes of exemplary embodiment of the invention, feature and advantage will become prone to understand.In the accompanying drawings, illustrate some embodiments of the present invention by way of example, and not by way of limitation, wherein:
Fig. 1 is the flow chart of fpga chip delayed data storage embodiment of the method 1 in the embodiment of the present invention；
Fig. 2 is the flow chart of fpga chip delayed data storage embodiment of the method 2 in the embodiment of the present invention；
Fig. 3 is the flow chart of fpga chip delayed data access method embodiment 1 in the embodiment of the present invention；
Fig. 4 is the flow chart of fpga chip delayed data access method embodiment 2 in the embodiment of the present invention；
Fig. 5-Fig. 6 is FPGA delayed data storage method example schematic；
Fig. 7-Fig. 8 is FPGA delayed data access method example schematic.
Detailed description of the invention
This describes principles of the invention and spirit below with reference to some illustrative embodiments.Should be appreciated that providing these embodiments is only used to make those skilled in the art better understood when and then realize the present invention, and the scope being not intended to limit the present invention in any manner.On the contrary, it is provided that these embodiments are to make the disclosure more thorough and complete, and the scope of the present disclosure can intactly convey to those skilled in the art.
Method flow diagram and equipment (or system) block diagram below with reference to embodiment of the present invention describe embodiments of the present invention.
With reference to shown in Fig. 1, for the flow chart of the FPGA delayed data storage embodiment of the method 1 that the embodiment of the present invention provides, the present embodiment may include steps of:
Whether S101, the every string judged on fpga chip only comprise a type of elementary cell, or whether the every a line on FPA chip only comprises a type of elementary cell；
Elementary cell type is identical refers to that the attribute of elementary cell is identical.Only comprising a type of elementary cell on every string (OK) on fpga chip, namely all elementary cells on string (OK) have identical attribute, and delay value is identical.Giving an example, such as first row (OK) is PLB, and secondary series (OK) is EMB, and the 3rd row (OK) are MAC etc..Here it is not especially limited as to whether all row (OK) are same type of elementary cell.If every string only comprises a type of elementary cell, enter step S102, if every a line only comprises a type of elementary cell, enter step S103.
Elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on S102, respectively storage fpga chip；
Described delayed data includes the delay value between two elementary cells being connected coordinate and two elementary cells on fpga chip.
This step only need to store delayed data between elementary cell and other elementary cells in fpga chip a line topmost and bottom a line respectively, and the delayed data of the full linking number stored in prior art between all elementary cells to lack many.
Elementary cell on high order end and low order end two row and delayed data between all elementary cells on described fpga chip on S103, respectively storage fpga chip.
When the every string in fpga chip not only comprises a type of elementary cell, or when the every a line on FPA chip also not only comprises a type of elementary cell, prior art storage delayed data can be adopted, i.e. delayed data between storage any two elementary cell.
In the technical scheme that the present embodiment provides, the delay value of same kind of elementary cell is identical, so the storage of delayed data can be optimized, concrete, first determine whether whether the every string of fpga chip only comprises a type of elementary cell, if the then elementary cell on storage fpga chip highest and lowest two row and delayed data between all elementary cells on described fpga chip respectively；If it is not, then judge whether the every a line of fpga chip only comprises a type of elementary cell, if the then elementary cell on storage the most left and the rightest two row of fpga chip and delayed data between all elementary cells on described fpga chip respectively.Compared with prior art, the storage overhead of the delayed data of elementary cell on the region outside fpga chip marginal portion is decreased.
Next, with reference to shown in Fig. 2, Fig. 2 is the flow chart of exemplary delayed data disclosed by the invention storage embodiment of the method 2, and the present embodiment can be regarded as another embodiment on the basis of embodiment 1, on the basis of embodiment 1, specifically can also comprise the steps:
When the every string of S201, fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical above and below；
If so, step S202 is performed, if it is not, then perform step S102.
S202, by chip topmost or bottom a line be designated as reference line, the elementary cell on storage reference line and the delayed data of all elementary cells on fpga chip.
When the every a line of S203, fpga chip only comprises same type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical；
If so, step S204 is then entered, if it is not, then perform step S103.
S204, chip high order end or low order end string are designated as reference columns, the delayed data of the elementary cell on storage reference columns and all elementary cells.
In the present embodiment, the sequencing that step S201 and step S203 is unfixing, whether it implements to depend on the result of implementation of step S101 in embodiment 1.
The technical scheme that the embodiment of the present invention provides, the beneficial effect of embodiment 1 can not only be realized, further, for fpga chip in up and down or symmetrical time, only the elementary cell on storage reference line or reference columns is to the delayed data between elementary cells all on chip, on the basis of embodiment 1, the memory space of half can be reduced again.
On the basis of above-described embodiment, carrying out openly to illustrate delayed data access method embodiment below, the access method embodiment of delayed data can be regarded as enforcement on the storage embodiment of the method basis of above-mentioned delayed data.With reference to shown in Fig. 3, for the flow chart of delayed data access method embodiment 1 provided by the invention, the present embodiment specifically may include steps of:
S301, will be located in signal and flow to two elementary cells to be checked of initiating terminal and be designated as source point and point of destination respectively；
When the every string of S302, fpga chip only comprises a type of elementary cell, perform the first reading flow process；
First reads flow process specifically includes that when the row coordinate of point of destination is more than the row coordinate of source point, first, by point of destination distance to direction, the bottom translation source point row coordinate size of row in column；Then, the delayed data between the elementary cell at place after the elementary cell of source point column bottom and point of destination translation is read.Otherwise then to the top orientation of row, point of destination being translated the first distance in column, described first distance is the distance of source point to fpga chip a line topmost；Read the delayed data between the elementary cell at place after the elementary cell on source point column top prestored and point of destination translation.
First principle reading flow process enters as follows: point of destination can be equivalent to source point to the distance of the direction, bottom of row translation source point row coordinate size in column and translate with point of destination simultaneously, owing to the row coordinate of point of destination is more than the row coordinate of source point, when source point moves to the bottom of column, point of destination is shifted the distance of source point row coordinate size, owing to the delay value of same kind of elementary cell is identical, so the delay value between the elementary cell at place is the delay value between source point and point of destination after the source point elementary cell in column bottom and point of destination translation.The principle that to the top orientation of row, point of destination is translated the first distance in column is similar with above-mentioned principle, repeats no more here.
When the every a line of S303, fpga chip only comprises a type of elementary cell, perform the second reading flow process.
Second reads flow process includes: when the row-coordinate of point of destination is more than the row-coordinate of source point, first, by point of destination distance to the left end direction translation source point row-coordinate size of row on being expert at；Then, read the elementary cell of the be expert at left end of described source point prestored and point of destination translate after place elementary cell between delayed data；Otherwise then to the right-hand member direction of row, point of destination being translated second distance on being expert at, described second distance is the source point distance to fpga chip low order end string；Read the elementary cell of the be expert at right-hand member of described source point prestored and point of destination translate after place elementary cell between delayed data.
Second principle reading flow process enters as follows: point of destination translates the distance of source point row-coordinate size on being expert to the left end direction of row, source point can be equivalent to translate with point of destination simultaneously, owing to the row-coordinate of point of destination is more than the row-coordinate of source point, when source point moves to the left end being expert at, point of destination is shifted the distance of source point row-coordinate size, but does not arrive the left end being expert at.Owing to the delay value of same kind of elementary cell is identical, so source point delay value between the elementary cell at place after the elementary cell of be expert at left end and point of destination translation is the delay value between source point and point of destination.The principle that to the right-hand member of row, point of destination is translated second distance on being expert at is similar with above-mentioned principle, repeats no more here.
Owing to prior art needs to store the delayed data under all elementary cells complete connects, data volume is bigger, thus the access speed of delayed data is also slower, the delayed data storage method that the embodiment of the present invention provides is relative to prior art, can the storage overhead of significantly less delayed data, owing to the information of storage is few, the access speed of delayed data relatively can be improved.
With reference to shown in Fig. 4, Fig. 4 is the flow chart of delayed data access method embodiment 2 provided by the invention, on the basis of delayed data access method embodiment 1, specifically can also comprise the steps:
When the every string of S401, fpga chip only comprises a type of elementary cell, if all of elementary cell is symmetrical above and below on fpga chip, then performs third reading and take flow process；
Third reading takes flow process and includes: source point to the distance of reference line less than the distance of point of destination to reference line time, first, point of destination is translated to reference line direction in column the 3rd distance, the distance that described 3rd distance is source point to reference line；Then, the delayed data between the elementary cell at place after the elementary cell of the source point column that prestores and reference line point of intersection and point of destination translation is read；
When the elementary cell on fpga chip is distributed in time symmetrical above and below, system storage is the elementary cell on reference line and the delayed data between all elementary cells, so when the distance of source point to reference line is more than the distance of point of destination to reference line, need source point and point of destination are processed, so as to be applicable to the source point distance to reference line less than the situation of the distance of point of destination to reference line.Firstly, it is necessary to determine respectively source point and point of destination relative to fpga chip row to the point of symmetry of line of symmetry, the point of symmetry of source point are designated as the first symmetrical source point, and the point of symmetry of point of destination are designated as the first symmetrical point of destination；Then, the first symmetrical point of destination is translated the 4th distance in column to reference line direction, described 4th distance is the first symmetrical source point distance to reference line；Read the delayed data between the elementary cell at place after the elementary cell of the prestore first symmetrical source point column and reference line point of intersection and the first symmetrical point of destination translation.
Wherein, described with reference to behavior chip the top or bottom a line.The principle that third reading takes flow process is similar with the first reading principle, repeats no more here.
When the every a line of S402, chip only comprises a type of elementary cell, if all of elementary cell is symmetrical on fpga chip, then perform the 4th reading flow process.
4th reads flow process includes: if source point to the distance of reference columns less than the distance of point of destination to reference columns, first, by point of destination on being expert to reference columns direction translation the 5th distance, the distance that described 5th distance is source point to reference columns；Read the delayed data between the elementary cell at place after the elementary cell of the source point column that prestores and reference columns point of intersection and point of destination translation.
When the elementary cell on fpga chip is distributed symmetrical, system storage is the elementary cell on reference columns and the delayed data between all elementary cells, so when the distance of source point to reference line is more than the distance of point of destination to reference line, need source point and point of destination are processed, so as to be applicable to the source point distance to reference columns less than the situation of the distance of point of destination to reference columns.First, determine that source point and point of destination arrange to the second of line of symmetry the symmetrical source point and the second symmetrical point of destination relative to fpga chip respectively；To reference columns, the second symmetrical point of destination is translated the 6th distance on being expert at, and described 6th distance is the second symmetrical source point distance to reference columns；Read the delayed data between the elementary cell at place after the elementary cell of the prestore second symmetrical source point and reference columns point of intersection and the second symmetrical point of destination translation；
Wherein, described reference is classified as chip high order end or low order end string.It is similar that 4th principle reading flow process reads principle with second, repeats no more here.
The technical scheme that the embodiment of the present invention provides, for fpga chip in up and down or symmetrical time, elementary cell on reference line or reference columns is only stored to the delayed data between elementary cells all on chip during due to storage, compared with the embodiment corresponding with the flow chart shown in Fig. 3, it is possible to improve the speed of the access of delayed data further.
Accordingly, on the basis of said method embodiment, the present invention also provides for the storage device embodiment 1 of a kind of fpga chip delayed data, and this device mainly may include that
Whether the first judge module, for judging whether only to comprise on the every string on fpga chip a type of elementary cell, or only comprise a type of elementary cell in the every a line on fpga chip；
First memory module, when every string only comprising same type of elementary cell in fpga chip, elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip respectively；
When every a line only comprises same type of elementary cell, store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange respectively.
Preferably, the present invention also provides for the storage device embodiment 2 of a kind of fpga chip delayed data, and in the present embodiment, described device is except the module described in said apparatus embodiment 1, it is also possible to including:
Second judge module, when the every string on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical above and below；
Second memory module, when all elementary cells on fpga chip are distributed symmetrical above and below, is designated as reference line, the elementary cell on storage reference line and the delayed data of all elementary cells on fpga chip by chip the top or bottom a line.
And/or, the 3rd judge module, when the every a line on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical；
3rd memory module, when all elementary cells on fpga chip are distributed symmetrical, is designated as chip high order end or low order end string reference columns, stores the delayed data of the elementary cell on reference columns and all elementary cells.
Accordingly, the present invention also provides for the access device embodiment 1 of a kind of fpga chip delayed data, and this device mainly may include that
Mark module, two elementary cells to be checked flowing to initiating terminal for will be located in signal are designated as source point and point of destination respectively；
First performs module, is used for performing the first reading flow process；Described first reads flow process includes:
If the row coordinate of point of destination is more than the row coordinate of source point, then by point of destination distance to direction, the bottom translation source point row coordinate size of row in column；Read the delay value between the elementary cell at place after the elementary cell of source point column bottom and point of destination translation；
Otherwise then to the top orientation of row, point of destination being translated the first distance in column, described first distance is the distance of source point to fpga chip a line topmost；Read the delay value between the elementary cell at place after the elementary cell on source point column top prestored and point of destination translation；
First trigger module, when the every string on fpga chip only comprises a type of elementary cell, triggers the first execution module and performs the first reading flow process；
Second performs module, is used for performing the second reading flow process, and described second reads flow process includes:
If the row-coordinate of point of destination is more than the row-coordinate of source point, then by point of destination distance to the left end direction translation source point row-coordinate size of row on being expert at；Read the elementary cell of the be expert at left end of described source point prestored and point of destination translate after place elementary cell between delay value；
Otherwise then to the right-hand member direction of row, point of destination being translated second distance on being expert at, described second distance is the source point distance to fpga chip low order end string；Read the elementary cell of the be expert at right-hand member of described source point prestored and point of destination translate after place elementary cell between delay value；
Second trigger module, when only comprising a type of elementary cell in the every a line of fpga chip, triggers the second execution module and performs the second reading flow process.
Preferably, accessing on the basis of device embodiment 1, the present invention also provides for the access device embodiment 2 of a kind of fpga chip delayed data, and except accessing the module that device embodiment 1 includes, the access device in the present embodiment can also include:
3rd performs module, is used for performing third reading and takes flow process；Described third reading takes flow process and includes:
If point of destination less than the distance of point of destination to reference line, is then translated the 3rd distance, the distance that described 3rd distance is source point to reference line to the distance of reference line by source point in column to reference line direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference line point of intersection and point of destination translation；
Otherwise then determine respectively source point and point of destination relative to fpga chip row to the symmetrical point of destination of the first of line of symmetry the symmetrical source point and first；First symmetrical point of destination is translated to reference line direction the 4th distance in column, and described 4th distance is the first symmetrical source point distance to reference line；Read the delay value between the elementary cell at place after the elementary cell of the prestore first symmetrical source point column and reference line point of intersection and the first symmetrical point of destination translation；
Wherein, described with reference to behavior fpga chip the top or bottom a line；
3rd trigger module, when only comprising a type of elementary cell on the every string of fpga chip, if all of elementary cell is symmetrical above and below on fpga chip, triggers the 3rd execution module execution third reading and takes flow process.
And/or, the 4th performs module, is used for performing the 4th reading flow process；Described 4th reads flow process includes:
If point of destination less than the distance of point of destination to reference columns, is translated the 5th distance, the distance that described 5th distance is source point to reference columns to the distance of reference columns by source point on being expert to reference columns direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference columns point of intersection and point of destination translation；
Otherwise then determine that source point and point of destination arrange to the second of line of symmetry the symmetrical source point and the second symmetrical point of destination relative to fpga chip respectively；To reference columns, the second symmetrical point of destination is translated the 6th distance on being expert at, and described 6th distance is the second symmetrical source point distance to reference columns；Read the delay value between the elementary cell at place after the elementary cell of the prestore second symmetrical source point and reference columns point of intersection and the second symmetrical point of destination translation；
Wherein, described reference is classified as fpga chip high order end or low order end string；
4th trigger module, when only comprising a type of elementary cell in the every a line of fpga chip, if all of elementary cell is symmetrical on fpga chip, triggers the 4th execution module and performs the 4th reading flow process.
In above-mentioned each device embodiment, the delay value of same kind of elementary cell is identical, so the storage of delayed data can be optimized, concrete, when the every string of fpga chip only comprises a type of elementary cell, elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip；When every a line only comprises a type of elementary cell, store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange.Compared with prior art, the expense of the delayed data of elementary cell on the region outside storage fpga chip marginal portion is decreased.
Further, when fpga chip in up and down or symmetrical time, only the elementary cell on storage reference line or reference columns is to the delayed data between elementary cells all on chip, can save the memory space of half further.
For the ease of the various embodiments described above are had deeper into understanding, now citing illustrates, with reference to shown in Fig. 5-8, wherein SRC to DST represents that signal flows to, so SRC represents source point, DST represents point of destination, NEWSRC represents the new source point after translating, NEWDST represents the new point of destination after translation, the coordinate of fpga chip storage any two elementary cell and delay value therebetween, and delay value mentioned here refers to signal transmission time used by shortest path therebetween.Wherein SRC and DST is any point in chip, is only used as schematically illustrate use here, is not to be taken as fixing a bit on chip.
The coordinate assuming source point is SRC (X1, Y1), and the coordinate of point of destination is DST (X2, Y2), illustrates for the ultimate unit of chip for PLB (duct type burst buffer).In the prior art, it is necessary to preserving the delayed data of each two PLB in advance, placement algorithm will read it and calculate cost value.Assume SRC (X1, Y1) X1 and the DST (X2 in, the scope of the X2 in Y2) is from 0 to (Width_M-1), the scope of Y1 and Y2 is from 0 to (Height_M-1), wherein, Width_M and Height_M represents the length and width of fpga chip respectively.Then the full number that connects of SRC and DST is: (Width_M) * (Height_M) * (Width_M) * (Height_M), and wherein the full number that connects of SRC to DST refers to SRC for starting point to all possible connection number of DST.If chip length and width are 100, the full quantity that connects that can be obtained SRC to DST by formula above is: 100*100*100*100=109.Namely chip needs to prestore 109Part delayed data.
According to the technical scheme that the embodiment of the present invention provides, when string every in chip all only has a type of elementary cell, with reference to shown in Fig. 5, for SRC (X1, Y1), the value of Y1 only has two, i.e. the Y value of chip bottom a line ultimate unit, Y value with the top a line ultimate unit, the value of Y1 can save as two amounts arbitrarily, and the Y1 in SRC (X1, Y1) is only preserved 0 and 1 two value by us here, 0 represents nethermost row, and 1 represents uppermost row.For source point, its coordinate has reformed into SRC (X1,0) and SRC (X1,1).With reference to above-mentioned example, the scope of X1 is still from 0 to (Width_M-1), and the scope of the X2 in DST (X2, Y2) is from 0 to (Width_M-1), and the scope of Y2 is from 0 to (Height_M-1).If chip length and width are 100, then the quantity of the delayed data of chip-stored is 100*2*100*100=2000000, compared with prior art, has saved the memory space of 98%.
It is exemplified below, the delayed data access method on the storage method basis of the delayed data provided in the embodiment of the present invention, shown in reference Fig. 5, illustrates optimizing Y-direction.nullWhen needing to read the delay value between source point SRC to DST，Fpga chip can be known the actual coordinate of SRC，It is designated as SRC (X1，Y1)，In practical operation，If the row coordinate that the row coordinate of SRC is less than DST，Then by SRC along a line moving to bottom under Y-axis，It is designated as new source point NEWSRC，NEWSRC is the elementary cell of SRC column and bottom a line point of intersection，New source point NEWSRC coordinate be (X1，0)，By the DST distance along Y-axis pan-down Y1，It is designated as NEWDST，Due to store in chip new source point NEWSRC to chip delay value between any elementary cell，Therefore after DST and SRC synchronous translational is obtained a NEWDST，Search the delay value of the new source point NEWSRC to new point of destination NEWDST prestored.
If the row coordinate that the actual row coordinate of SRC is more than DST, with reference to the schematic diagram in dotted ellipse in Fig. 5, SRC and DST is to topmost translating, respectively obtain NEWSRC and NEWDST, it should be noted that, the distance that DST translates up is not Y1, but SRC is to the distance of a line topmost, searches the delay value of the new source point NEWSRC to new point of destination NEWDST prestored.
When a line every in chip all only has a type of elementary cell, it is possible to store at the delayed data of X-direction and do optimization with reference to shown in Fig. 6.The value of X1 only has two, the i.e. X value of chip leftmost string elementary cell, X value with rightmost a line elementary cell, the value of X1 can save as two amounts arbitrarily, same, the X1 in SRC (X1, Y1) is only preserved 0 and 1 two value by us here, 0 row representing leftmost, 1 represents rightmost row.For source point, its coordinate has reformed into SRC (0, Y1) and SRC (1, Y1).With reference to above-mentioned example, the scope of Y1 is still from 0 to (Height_M-1).The scope of the X2 in DST (X2, Y2) is from 0 to (Width_M-1), and the scope of Y2 is from 0 to (Height_M-1).If chip length and width are 100, then the quantity of the delay data of chip-stored is 100*2*100*100=2000000, compared with prior art, has saved the memory space of 98%.
Owing to the principle of optimality of X-direction is similar with Y-direction, it is also similar that delayed data accesses principle, the access process of delay value when can above-mentioned Y-direction be optimized for information access method when optimizing X-direction, and the explanation of delayed data access method embodiment, no longer illustrate it here.
For the laterally zygomorphic situation of fpga chip, it is referred to the schematic diagram shown in Fig. 7, symmetrical situation, it is referred to shown in Fig. 8, due to symmetrical above and below similar with the access principle of delay value time symmetrical, here no longer introduce one by one, only illustrate with the laterally zygomorphic situation shown in Fig. 7.
When chip is symmetrical above and below, it is possible to using most for chip lastrow or most next line as reference line, on storage reference line, all elementary cells are to the delayed data of other all elementary cells.Here explain with next behavior reference line.When needing to read the delay data between source point SRC to DST, what can know is the actual coordinate of SRC and DST, it is designated as SRC (X1, Y1), if SRC is to distance less than DST to reference line of the distance of reference line, the i.e. coordinate Y2 of the DST coordinate Y1 more than SRC, then by SRC along a line moving to bottom under Y-axis, it is designated as new source point NEWSRC, NEWSRC and is the elementary cell of SRC column and bottom a line point of intersection, new source point NEWSRC coordinate be (X1,0).By the DST distance along Y-axis pan-down Y1, it is designated as NEWDST, new source point NEWSRC delay value between any elementary cell to chip is stored in chip, therefore, after DST and SRC synchronous translational is obtained a NEWDST, the delay value of the new source point NEWSRC to new point of destination NEWDST prestored is accessed.
When distance more than DST to reference line of the distance of SRC to reference line, need SRC and DST is processed, first, obtain SRC and DST relative to the point of symmetry of fpga chip row line of symmetry, i.e. SRC and the one DST shown in Fig. 7, then by a SRC along a line moving to bottom under Y-axis, it is designated as new source point NEWSRC, NEWSRC is the elementary cell of SRC column and bottom a line point of intersection, new source point NEWSRC coordinate be (X1,0).By the DST distance along the row coordinate size of Y-axis pan-down the oneth SRC, it is designated as NEWDST, accesses the delay value of the new source point NEWSRC to new point of destination NEWDST prestored.
When choosing most lastrow and being reference line, digital independent principle is similar with it, repeats no more here.Simultaneously, when the symmetrical distribution of elementary cell on fpga chip, the delayed data access method of its correspondence is similar with the explanation of Fig. 7, with reference to the explanation of Fig. 7 and the above-mentioned description to delayed data access method embodiment on the basis of the schematic diagram shown in Fig. 8, no longer can illustrate here
It should be noted that, in this article, the relational terms of such as first and second or the like is used merely to separate an entity or operation with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.Verb " including ", " comprising " and the paradigmatic use thereof mentioned in application documents be not excluded for those elements except recording in application documents or step except element or the existence of step.Article "a" or "an" before element is not excluded for the existence of multiple this element.
Although describe spirit and the principle of the present invention by reference to some detailed description of the invention, however, it should be understood that, the present invention is not limited to disclosed detailed description of the invention, the division of each side is not meant that the feature in these aspects can not combine to be benefited yet, this division merely to statement convenience.It is contemplated that contain various amendments included in the spirit and scope of claims and equivalent arrangements.Scope of the following claims meets broadest explanation, thus comprising all such amendments and equivalent structure and function.

Claims (12)

  1. The storage method of 1.FPGA chip delayed data, it is characterised in that including:
    Judge whether the every string on fpga chip only comprises a type of elementary cell, or whether the every a line on fpga chip only comprises a type of elementary cell；
    If every string only comprises same type of elementary cell, then elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip respectively；
    If every a line only comprises same type of elementary cell, then store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange respectively.
  2. 2. method according to claim 1, it is characterised in that described method also includes:
    When every string on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical above and below；
    If symmetrical above and below, chip the top or bottom a line are designated as reference line, the elementary cell on storage reference line and the delayed data of all elementary cells on fpga chip.
  3. 3. method according to claim 1, it is characterised in that when only comprising a type of elementary cell in the every a line on fpga chip, it is judged that whether all elementary cells distribution on fpga chip is symmetrical；
    If symmetrical, chip high order end or low order end string are designated as reference columns, store the delayed data of the elementary cell on reference columns and all elementary cells.
  4. The access method of 4.FPGA chip delayed data, it is characterised in that including:
    Will be located in signal to flow to two elementary cells to be checked of initiating terminal and be designated as source point and point of destination respectively；
    When every string on fpga chip only comprises a type of elementary cell, perform the first reading flow process；
    Described first reads flow process includes:
    If the row coordinate of point of destination is more than the row coordinate of source point, then by point of destination distance to direction, the bottom translation source point row coordinate size of row in column；Read the delay value between the elementary cell at place after the elementary cell of source point column bottom and point of destination translation；
    Otherwise then to the top orientation of row, point of destination being translated the first distance in column, described first distance is the distance of source point to fpga chip a line topmost；Read the delay value between the elementary cell at place after the elementary cell on source point column top prestored and point of destination translation；
    When the every a line of fpga chip only comprises a type of elementary cell, perform the second reading flow process；
    Described second reads flow process includes:
    If the row-coordinate of point of destination is more than the row-coordinate of source point, then by point of destination distance to the left end direction translation source point row-coordinate size of row on being expert at；Read the elementary cell of the be expert at left end of described source point prestored and point of destination translate after place elementary cell between delay value；
    Otherwise then to the right-hand member direction of row, point of destination being translated second distance on being expert at, described second distance is the source point distance to fpga chip low order end string；Read the elementary cell of the be expert at right-hand member of described source point prestored and point of destination translate after place elementary cell between delay value.
  5. 5. method according to claim 4, it is characterised in that described method also includes:
    When the every string of fpga chip only comprises a type of elementary cell, if all of elementary cell is symmetrical above and below on fpga chip, performs third reading and take flow process；
    Described third reading takes flow process and includes:
    If point of destination less than the distance of point of destination to reference line, is then translated the 3rd distance, the distance that described 3rd distance is source point to reference line to the distance of reference line by source point in column to reference line direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference line point of intersection and point of destination translation；
    Otherwise then determine respectively source point and point of destination relative to fpga chip row to the symmetrical point of destination of the first of line of symmetry the symmetrical source point and first；First symmetrical point of destination is translated to reference line direction the 4th distance in column, and described 4th distance is the first symmetrical source point distance to reference line；Read the delay value between the elementary cell at place after the elementary cell of the prestore first symmetrical source point column and reference line point of intersection and the first symmetrical point of destination translation；
    Wherein, described with reference to behavior fpga chip the top or bottom a line.
  6. 6. method according to claim 4, it is characterised in that described method also includes:
    When the every a line of fpga chip only comprises a type of elementary cell, if all of elementary cell is symmetrical on fpga chip, perform the 4th reading flow process；
    Described 4th reads flow process includes:
    If point of destination less than the distance of point of destination to reference columns, is translated the 5th distance, the distance that described 5th distance is source point to reference columns to the distance of reference columns by source point on being expert to reference columns direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference columns point of intersection and point of destination translation；
    Otherwise then determine that source point and point of destination arrange to the second of line of symmetry the symmetrical source point and the second symmetrical point of destination relative to fpga chip respectively；To reference columns, the second symmetrical point of destination is translated the 6th distance on being expert at, and described 6th distance is the second symmetrical source point distance to reference columns；Read the delay value between the elementary cell at place after the elementary cell of the prestore second symmetrical source point and reference columns point of intersection and the second symmetrical point of destination translation；
    Wherein, described reference is classified as fpga chip high order end or low order end string.
  7. 7. the storage device of a fpga chip delayed data, it is characterised in that described device includes:
    Whether the first judge module, for judging whether only to comprise on the every string on fpga chip a type of elementary cell, or only comprise a type of elementary cell in the every a line on fpga chip；
    First memory module, when every string only comprising same type of elementary cell in fpga chip, elementary cell topmost and on the row of bottom two and delayed data between all elementary cells on described fpga chip on storage fpga chip respectively；
    When every a line only comprises same type of elementary cell, store the delayed data between all elementary cells in the elementary cell and described fpga chip that on fpga chip, high order end and low order end two arrange respectively.
  8. 8. device according to claim 7, it is characterized in that, described device also includes: the second judge module, when the every string on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical above and below；
    Second memory module, when all elementary cells on fpga chip are distributed symmetrical above and below, is designated as reference line, the elementary cell on storage reference line and the delayed data of all elementary cells on fpga chip by chip the top or bottom a line.
  9. 9. device according to claim 7, it is characterised in that described device also includes:
    3rd judge module, when the every a line on fpga chip only comprises a type of elementary cell, it is judged that whether all elementary cells distribution on fpga chip is symmetrical；
    3rd memory module, when all elementary cells on fpga chip are distributed symmetrical, is designated as chip high order end or low order end string reference columns, stores the delayed data of the elementary cell on reference columns and all elementary cells.
  10. 10.FPGA the access device of chip delayed data, it is characterised in that including:
    Mark module, two elementary cells to be checked flowing to initiating terminal for will be located in signal are designated as source point and point of destination respectively；
    First performs module, is used for performing the first reading flow process；Described first reads flow process includes:
    If the row coordinate of point of destination is more than the row coordinate of source point, then by point of destination distance to direction, the bottom translation source point row coordinate size of row in column；Read the delay value between the elementary cell at place after the elementary cell of source point column bottom and point of destination translation；
    Otherwise then to the top orientation of row, point of destination being translated the first distance in column, described first distance is the distance of source point to fpga chip a line topmost；Read the delay value between the elementary cell at place after the elementary cell on source point column top prestored and point of destination translation；
    First trigger module, when the every string on fpga chip only comprises a type of elementary cell, triggers the first execution module and performs the first reading flow process；
    Second performs module, is used for performing the second reading flow process, and described second reads flow process includes:
    If the row-coordinate of point of destination is more than the row-coordinate of source point, then by point of destination distance to the left end direction translation source point row-coordinate size of row on being expert at；Read the elementary cell of the be expert at left end of described source point prestored and point of destination translate after place elementary cell between delay value；
    Otherwise then to the right-hand member direction of row, point of destination being translated second distance on being expert at, described second distance is the source point distance to fpga chip low order end string；Read the elementary cell of the be expert at right-hand member of described source point prestored and point of destination translate after place elementary cell between delay value；
    Second trigger module, when only comprising a type of elementary cell in the every a line of fpga chip, triggers the second execution module and performs the second reading flow process.
  11. 11. device according to claim 10, it is characterised in that described device also includes:
    3rd performs module, is used for performing third reading and takes flow process；Described third reading takes flow process and includes:
    If point of destination less than the distance of point of destination to reference line, is then translated the 3rd distance, the distance that described 3rd distance is source point to reference line to the distance of reference line by source point in column to reference line direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference line point of intersection and point of destination translation；
    Otherwise then determine respectively source point and point of destination relative to fpga chip row to the symmetrical point of destination of the first of line of symmetry the symmetrical source point and first；First symmetrical point of destination is translated to reference line direction the 4th distance in column, and described 4th distance is the first symmetrical source point distance to reference line；Read the delay value between the elementary cell at place after the elementary cell of the prestore first symmetrical source point column and reference line point of intersection and the first symmetrical point of destination translation；
    Wherein, described with reference to behavior fpga chip the top or bottom a line；
    3rd trigger module, when only comprising a type of elementary cell on the every string of fpga chip, if all of elementary cell is symmetrical above and below on fpga chip, triggers the 3rd execution module execution third reading and takes flow process.
  12. 12. device according to claim 10, it is characterised in that described device also includes:
    4th performs module, is used for performing the 4th reading flow process；Described 4th reads flow process includes:
    If point of destination less than the distance of point of destination to reference columns, is translated the 5th distance, the distance that described 5th distance is source point to reference columns to the distance of reference columns by source point on being expert to reference columns direction；Read the delay value between the elementary cell at place after the elementary cell of the source point column that prestores and reference columns point of intersection and point of destination translation；
    Otherwise then determine that source point and point of destination arrange to the second of line of symmetry the symmetrical source point and the second symmetrical point of destination relative to fpga chip respectively；To reference columns, the second symmetrical point of destination is translated the 6th distance on being expert at, and described 6th distance is the second symmetrical source point distance to reference columns；Read the delay value between the elementary cell at place after the elementary cell of the prestore second symmetrical source point and reference columns point of intersection and the second symmetrical point of destination translation；
    Wherein, described reference is classified as fpga chip high order end or low order end string；
    4th trigger module, when only comprising a type of elementary cell in the every a line of fpga chip, if all of elementary cell is symmetrical on fpga chip, triggers the 4th execution module and performs the 4th reading flow process.
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