CN105793983A - Method for producing an electronic chip support, chip support and set of such supports - Google Patents
Method for producing an electronic chip support, chip support and set of such supports Download PDFInfo
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- CN105793983A CN105793983A CN201480062932.7A CN201480062932A CN105793983A CN 105793983 A CN105793983 A CN 105793983A CN 201480062932 A CN201480062932 A CN 201480062932A CN 105793983 A CN105793983 A CN 105793983A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Particle Formation And Scattering Control In Inkjet Printers (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
In this method for producing at least one electronic chip support (12), the support is produced from a plate (26) that comprises, a first face (16) intended to be in contact with a chip reader, a second face (20), covered with a first layer (A) of electrically conductive material and intended to be linked to a radio antenna, and a core (35) made from an electrically insulating material separating the first face (16) from the second face (20). This method comprises steps of drilling at least one through hole (36) through the plate (26), depositing a layer (C) of electrically conductive material on the first face (16) and chemically etching a first electric circuit (32) and a second electric circuit (34) on the first face (16) and the second face (20) respectively. According to the invention, the method comprises, prior to the chemical etching step, a step of depositing a third layer (D) of electrically conductive material in the hole or holes (36), which covers the electrically insulating material in the corresponding hole or holes (36) and which, after the chemical etching step, electrically links the first electric circuit (32) and the second electric circuit (34).
Description
Technical field
The present invention relates to the manufacture method of a kind of electronic chip supporting member.The invention still further relates to this electronic chip supporting member and the assembly of this electronic chip supporting member.
Background technology
In electronic chip supporting member field, a kind of supporting member with two surfaces of known production, described supporting member includes the first surface for contacting and the second surface contrary with described first surface with chip reader, and described second surface is for coupling with wireless aerial.When chip is connected with this supporting member, terminal or can set up the communication with chip by the contact on first surface or the wireless aerial contactlessly by being connected with second surface.
Figure 11 and Figure 12 local illustrates the assembly 500 of the chip supporting member 502 meeting prior art.More properly, Figure 11 illustrates the surface 504 that the first surface 506 with each chip supporting member 502 of assembly 500 is corresponding.As for Figure 12, the figure shows the surface 508 that the second surface 510 with each chip supporting member 502 of assembly 500 is corresponding.
The assembly 500 of chip supporting member includes along two longitudinal edges 512,514 of its width W500 and two chip supporting members 502 between the two edge 512,514.It addition, assembly 500 includes multiple chip supporting members 502 of L500 along its length, wherein to arrange supporting member visible on these figure for three row two.
Each chip supporting member 502 extends along the length L500 of assembly 500 upper equal to the length L502 (" step-length (pas) " also referred to as supporting member 502) of 14.25mm.
On each surface 504,508, edge 512,514 each includes supply line 516a, 516b, 518a, 518b (also referred to as " for current source ") of being made of an electrically conducting material.Supply line 516a, 516b, 518a, 518b extend and can be surface 504,508 power supply of correspondence on the whole length L500 of assembly 500.
Each first surface 506 includes the first circuit 520, and described first circuit is for contacting with chip reader and being connected with for current source 516a, 516b.Each second surface 510 includes second circuit 522, and described second circuit is for being connected with wireless aerial and being connected with for current source 518a, 518b.Chain 516a, 516b can be that each first circuit 520 supplies induced current, to implement the material (such as gold) electrolytic deposition (é lectrod é position) on each first circuit 520.Chain 518a, 518b can be that each second circuit 522 supplies induced current, to implement the material (such as gold) electrolytic deposition on each second circuit 522.
Each first circuit 520 includes the contact area 524 contacted with chip reader.Contact area 524 is covered by conducting metal (such as copper) and includes the hole 526 leading to each second surface 510 below this conductive material.
Each second circuit 522 includes two junction points 528,530 being connected with wireless aerial.
During when chip being fixed on each supporting member 502 (more properly on corresponding second surface 510), in order to allow the connection between chip reader and chip, wire is connected between this chip with contact area 524 and through corresponding hole 526.
When manufacturing assembly 500 (more specifically one of them supporting member 502), in order to implement such as gold electrolytic deposition on the first circuit 520 being generally made of copper and second circuit 522, it is necessary to respectively through first surface 506 and second surface 510 (i.e. the first circuit 520 and the second circuit 522) power supply of the supporting member that chain 516a, 516b and 518a, 518b are correspondence.And, when manufacturing supporting member 502, the diameter in hole 526 needs sufficiently large, passes through for allowing the connection wire between contact area 524 and electronic chip.Additionally, every wire is implemented in the inside in corresponding hole 526 with the connection of related contact areas 524, this requirement uses relatively long wire between chip and contact area 524.In modification, wire is connected the inside in hole between contact area and conductive material ring, and described conductive material loop mapping on second surface 510 and collar around hole 526, is then implemented to be connected between chip with this ring.But, in this supporting member, it is possible to make wire that each contact area 524 couples with chip and hole 526 occupy bigger volume.Owing to second surface includes the junction point 528,530 that is connected with wireless aerial, the size of second circuit 522 is such as: the length L502 of each chip supporting member 502 is approximately 14.25mm or more than 14.25mm.In fact, according to the working standard (such as standard ISO/IEC7816-2:2007) for chip supporting member, the length of chip supporting member is required to be the multiple of 4.75mm, this require chip supporting member be likely to be of a size of 4.75mm, 9.5mm, 14.25mm etc..Additionally, chip supporting member 502 include on both surfaces for current source, this requires the gold each By Electrolysis deposition in chain 516a, 516b, 518a, 518b when the electrolytic deposition step of gold.Which results in the increase of manufacturing cost.
Summary of the invention
It is an object of the invention to provide a kind of chip supporting member, described chip supporting member includes the first surface contacted with chip reader and the second surface being connected with wireless aerial, wherein electronic chip is easy to connect, and therefore the manufacturing cost of this chip supporting member reduces.
For this, it is desirable to provide the manufacture method of at least one electronic chip supporting member a kind of, this supporting member is made up of plate, and described plate includes: for the first surface contacted with chip reader；The second surface contrary with described first surface, described second surface is covered by the first conductive material layer and for coupling with wireless aerial；And the core making described first surface separate with described second surface being made up of electrically insulating material, said method comprising the steps of:
-a) at least one through hole of described plate it is drilled through along the direction vertical with described plate,
-b) the second conductive material layer to be placed on the first surface, described second conductive material layer can cover one or more hole, and
-c) difference chemical etching over the first and second surface (gravure) first circuit and second circuit.
According to the present invention, described method includes the following steps before chemical etching step:
-b1) the 3rd conductive material layer is placed in one or more hole, described 3rd conductive material layer is made up of the conductive material suitable in the electrically insulating material corresponding one or more holes covering core, after chemical etching step c), the 3rd conductive material layer makes the first circuit electrically couple with second circuit.
Due to the present invention, the 3rd conductive material layer can make one or more hole (more properly the insulant in hole) electrically susceptibleization, so that the first circuit couples with second circuit.Additionally, due to the present invention, each hole produces to associate between first surface with second surface, and when being connected on a second surface by chip, only need to chip and second circuit with the wire welding very small dimensions between the electrically connected part in hole.Therefore, chip and the first circuit and and second circuit between the size in connection region be miniaturized, this can produce the step-length chip supporting member equal to 9.5mm.
Other favourable aspect according to the present invention, described manufacture method also includes the one or more following characteristics separately adopting or adopting according to technically feasible all combinations:
-after placement step b) and before chemical etching step c), said method comprising the steps of b2): make the 4th conductive material layer inside electrolytic deposition on a second surface and in each hole by only making one in two surfaces to be connected with power supply source.
-after chemical etching step, said method comprising the steps of d) and e): make the 5th conductive material layer electrolytic deposition on the first surface, and make the 6th conductive material layer electrolytic deposition on a second surface, now the electrolytic deposition step of the 5th conductive material layer and the 6th conductive material layer is by making the first circuit and second circuit implement with being only connected at the power supply source of described first circuit 32 side.
-the first one side electrolysis (é lectroiysemonoface) is implemented when the electrolytic deposition step of the 5th conductive material layer, second surface is hidden component by first and hides, and implement the second one side electrolysis when the electrolytic deposition step of the 6th conductive material layer, first surface is hidden component by second and hides.
-before the electrolytic deposition of the 5th conductive material layer and the 6th conductive material layer, the nickel dam at least one By Electrolysis deposition in the 3rd conductive material layer and the 4th conductive material layer.
-three conductive material layer is made up of the material based on carbon.
-five conductive material layer and the 6th conductive material layer are made up of the material based on gold.
-the first hole and the second hole is bored when drill process, described first hole is drilled near one or more contact areas of chip reader and first surface, and described second hole is drilled in outside the one or more contact area, and after an etching step, second circuit includes two junction points being connected with wireless aerial, and electrical continuity is maintained between each second hole and corresponding junction point.
-after an etching step, second circuit includes and one or more connection regions of chip connection, and each connection region is electrically coupled with the second corresponding hole by the 4th conductive material layer.
The present invention is also directed to a kind of electronic chip supporting member, and this supporting member includes plate, and described plate includes: through at least one through hole of described plate, at least one through hole described is along the direction vertical with described plate；Including the first circuit and the first surface for contacting with chip reader, described first circuit covers one or more holes in described first surface side；The second surface contrary with described first surface, described second surface includes second circuit and for coupling with wireless aerial；And the core making described first surface separate with described second surface being made up of electrically insulating material.According to the present invention, conductive material layer is arranged in one or more hole, and described conductive material layer covers the electrically insulating material in corresponding one or more holes and makes described first circuit electrically couple with described second circuit.
Other favourable aspect according to the present invention, described supporting member also includes the one or more following characteristics separately adopting or adopting according to technically feasible all combinations:
-first surface forms tetragon, and the length of the most minor face of described tetragon is equal to 9.5mm, and error span is 2%.
-second circuit includes and one or more connection regions of chip connection, and each connection region electrically couples with corresponding hole.
The present invention is also directed to the assembly of a kind of chip supporting member, and this assembly includes along two edges of its width and at least two chip supporting member between said two edge, and described chip supporting member is described above.
Advantageously, described assembly include only from the teeth outwards with first surface or at least one supply line corresponding with second surface, described at least one supply line extends along the length of described assembly and or couples with each corresponding circuit electrical by means of branch road or by means of at least one conductive material layer being arranged in one or more hole.
Accompanying drawing explanation
Following it is only used as detailed description that non-limiting example provides and accompanying drawing better understood when the present invention by reading, and the further advantage of the present invention will be apparent from, in the accompanying drawings:
-Fig. 1 is consistent with the partial top view of the first surface of the chip supporting member assembly of first embodiment of the invention；
-Fig. 2 is the partial top view of the second surface contrary with first surface of the chip supporting member assembly of Fig. 1；
-Fig. 3 is the partial sectional view that the plane III along Fig. 1 of in the chip supporting member being connected with chip of Fig. 1 intercepts；
-Fig. 4 is the flow chart of the manufacture method of the assembly of Fig. 1 and Fig. 2；
-Fig. 5 is the sectional view of the plate that when the manufacture of the chip supporting member of Fig. 3 use similar with Fig. 3；
-Fig. 6 is the sectional view the placement step of drill process and second conductive material layer and threeth conductive material layer after similar with Fig. 5；
-Fig. 7 is the sectional view the electrolytic deposition step of fourth conductive material layer after similar with Fig. 6；
-Fig. 8 is the top view of the monolayer electrolysis installation used when the electrolytic deposition step of the 5th conductive material layer and the 6th conductive material layer；
-Fig. 9 is the partial top view of the first surface of the chip supporting member assembly that meet second embodiment of the invention similar with Fig. 1；
-Figure 10 is the partial top view of the second surface contrary with first surface of the chip supporting member assembly of Fig. 9 similar with Fig. 2；
-Figure 11 is consistent with the partial top view of the first surface of the chip supporting member assembly of prior art；
-Figure 12 is the partial top view of the second surface contrary with first surface of the chip supporting member assembly of Figure 11.
Detailed description of the invention
On Fig. 1 and Fig. 2, chip supporting member assembly 10 includes six chip supporting members 12.More properly, Fig. 1 illustrates the surface 14 that the first surface 16 with each chip supporting member 12 of assembly 10 is corresponding.The surface 18 that the second surface 20 contrary with first surface 16 with each chip supporting member 12 that Fig. 2 illustrates assembly 10 is corresponding.
Chip supporting member assembly 10 is formed and includes plurality of rows of two of lateral dimension (namely along width W10) along assembly 10 and be disbursed from the cost and expenses the band (bande) of bearing member 12, and this two string being disbursed from the cost and expenses in bearing member is arranged in another row rear along the longitudinal size (namely along length L10) of assembly 10.It practice, as on Fig. 1 and Fig. 2 by making shown in the axis lines that assembly 10 extends, assembly 10 includes tens or two being disbursed from the cost and expenses bearing member 12 of some rows, and this two string being disbursed from the cost and expenses in bearing member is arranged in another and arranges rear along the length L10 of assembly 10.Assembly 10 includes two edges 22 and 24 along its width W10, and two are disbursed from the cost and expenses often the coming between two edges 22 and 24 of bearing member.
This specification below relate on Fig. 1 and Fig. 2 visible two intermediate row being disbursed from the cost and expenses bearing member 12, but can be applicable to two other rows being disbursed from the cost and expenses bearing member 12.
Each chip supporting member 12 extends upper equal to the length L12 (step-length also referred to as supporting member 12) of 9.5mm.
Each chip supporting member 12 includes plate 26, and described plate forms first surface 16 and second surface 20.
It practice, the plate 26 of each supporting member 12 forms single continuous band, described single continuous band extends on width between edge 22 and 24, and extends (more properly in the length of the length L10 corresponding to assembly 10) on many meters in length.
On surface 14 and therefore, wherein on each first surface 16, edge 22 and 24 each includes the supply line being made up of conductive material (such as copper) or " for current source " 28a, 28b.Supply line 28a, 28b extend on the whole length L10 of assembly 10 and can power for surface 14.Supply line 28a, 28b are positioned around the through hole 29 through chip supporting member 12 and plate 26.Hole 29 is applicable to make assembly 10 be parallel to the length L10 of this assembly component moved along the manufacture line (such as driving contact (doigts)) of this assembly 10 for receiving.
Each first surface 16 includes the first circuit 32, and described first circuit is for contacting with chip reader and being connected with corresponding supply line 28a, 28b by branch road 32a and 32b.
Each second surface 20 includes second circuit 34, and described second circuit is for being connected with unshowned wireless aerial.
As shown on Fig. 5, before manufacturing corresponding supporting member 12, each plate 26 includes the first conductive material layer A on the second surface 20 and layer B being pasted onto on first surface 16, and includes the core 35 making first surface 16 separate being made up of electrically insulating material with corresponding second surface 20.Described electrically insulating material is preferably expoxy glass.
Each plate 26 includes six the first holes 36 and two the second holes 38, and this some holes is along the direction vertical with described plate through described plate.More properly, six the first holes 36 and two the second hole 38 1 aspects lead to second surface 20, are covered by the second conductive material layer C at first surface 16 place on the other hand.As shown in Figure 3, for one of them the first hole 36, each first hole 36 includes the 3rd conductive material layer D on the sidewall at core 35 and adhered layer place, and described 3rd conductive material layer is covered by the 4th conductive material layer E.
Each first circuit 32 includes the contact area 40 contacted with chip reader.As shown in Figure 3, contact area 40 is positioned on first surface 16 and covers the first hole 36.Contact area 40 includes the second layer C in isolation (s' é loignerde) first hole 36, and includes the 4th conductive material layer E and the five conductive material layer F.As a supplement, second layer C and third layer D and contacting at the first hole 36 place with the 4th layer of E.
More generally, the first circuit 32 includes second layer C, and includes the 4th layer of E and layer 5 F.
Second circuit 34 includes two junction points 44 and 46 being connected with two wireless aerials.Second circuit 34 includes ground floor A, and includes the 4th layer of E and the layer 6 G being made of an electrically conducting material.Inside that layer 6 G is further placed in each first hole 36 and the 4th layer of E covering in each hole 36.
Second hole 38 includes the layer identical with the first hole 36.Second hole 38 is arranged to through each plate 26 outside contact area 40, and is covered by the first circuit 32 at first surface 16 place.
Advantageously, second circuit the 34, first hole 36 and the second hole 38 include at the 4th layer of unshowned nickel dam between E and layer 6 G.Equally advantageous, the first circuit 32 includes at the 4th layer of unshowned nickel dam between E and layer 5 F.Nickel is it can be avoided that material is respectively at the 4th layer between E and layer 5 F and the 4th layer of all diffusion between E and layer 6 G.
Such as when the 4th layer of E deposits at first surface 16 By Electrolysis, supply line 28a, 28b can power for each first circuit 32.
3rd conductive material layer D is such as based on the electrically insulating material in the first hole 36 and the second hole 38 of carbon and covering and core 35, so that the first circuit 32 electrically couples with second circuit 34.More properly, carbon can make the first hole 36 and the second hole 38 electrically susceptibleization.And, the first circuit 32 couples with second circuit 34, and therefore contact area 40 couples with second circuit 34.Supply line 28a, 28b can also pass circuit 32 and third layer D powers for each second circuit 34 outside each first circuit 32.
Electric with in the second corresponding hole 38 by corresponding electric line 48,49 with two junction points 44,46 that corresponding wireless aerial connects couple.Therefore, electrical continuity is maintained between each second hole 38 and associated contact 44,46.Connection between junction point the 44,46 and second hole 38 can be junction point 44,46 power supply by electric line 28a, 28b and the third layer being present in the second hole 38 and the 4th layer, so that layer 6 G deposits at junction point 44,46 By Electrolysis.
Additionally, each second circuit 34 includes the connection region 50 with chip 51 connection near each first hole 36 on corresponding second surface 20.Each connection region 50 by the 4th layer of E be arranged in the face of one of them first corresponding hole 36 of corresponding contact area 40 electrically couples.Therefore, each contact area 40 electrically couples with corresponding connection region 50.
When being fixed therein on a supporting member 12 by chip 51, this chip is fixed on second surface 20, and junction point 44,46 is connected with this chip by tie-point 52.More properly, unshowned wire is connected between each tie-point 52 and chip 51.And, wireless aerial electrically couples with chip 51, this chip can contactlessly with applicable chip reader communication.
When being fixed on supporting member 12 by chip 51, this chip is connected with connection region 50 also by electric line, and wherein an electric line is visible on Fig. 3, and accompanying drawing is labeled as 54.Chip 51 therefore, it is possible to by with contacting of first surface 16 (more properly with contact area 40) and through hole 36 and chip reader communication.
Ground floor A, four layers of E of second layer C and the are made up of the material based on copper.
Layer 5 F is for protecting the first circuit 32 with antioxidative layer gold, and the thickness being perpendicular to plate measurement (namely along the central axis in the first hole 36) of this layer is approximately 0.1 micron (μm).
Layer 6 G can protect the first circuit 32 to allow on the other hand with antioxidation to connect wire with chip in the layer gold welded connect on region 50 and tie-point 52 on the one hand.The thickness being perpendicular to plate measurement of layer 6 G is approximately 0.35 micron.On second circuit 34, more properly in connection region 50 and tie-point 52 place, the thickness of gold need to for wire in chip and connection region 50 and sufficiently large with welding between tie-point 52.
On Fig. 4, it is shown that the flow chart of the manufacture method of assembly 10.As explained above, in order to manufacture chip supporting member 12, plate 26 is for each supporting member, and different plates 26 actually form continuous band.As shown on Fig. 5, time initial, plate 26 includes the first surface 16 being completely covered by adhered layer B and the second surface 20 covered by ground floor A.Plate 26 also includes making ground floor A and adhered layer B (i.e. first surface 16 and the second surface 20) core 35 separated.Adhered layer B such as includes epoxy alite paste.
When the first drill process 100, being drilled through the first hole 36 and the second hole 38 of plate 26 along the direction vertical with the principal plane P26 of plate 26, this principal plane is equidistant with surface 16 and 20.First hole 36 and the second hole 38 are run through relative to plate 26.The central axis X 36 vertical with plane P26 in hole 36 is visible on Fig. 3, Fig. 6 and Fig. 7.
Then, when next step 102, second layer C is arranged on first surface 16.More properly, copper coin paste (collamin é e) on first surface 16 (namely on adhered layer B).Therefore second layer C covers the first hole 36 and the second hole 38.
Subsequently, when step 104, the 3rd conductive material layer D is arranged in the first hole 36 and the second hole 38.Third layer D is made up of carbon and suitable in the electrically insulating material the first hole 36 and the second hole 38 covered with core 35.Therefore third layer D makes first surface 16 electrically couple with second surface 20.
The plate 26 (more properly each chip supporting member 12) structure after step 100 is to 104 is shown on Fig. 6.
In the process of next step 106, the 4th conductive material layer E inside electrolytic deposition on second surface 20 and in the first hole 36 and the second hole 38.As a supplement, the 4th layer of E also deposits at first surface 16 By Electrolysis.In order to implement this electrolytic deposition step 106 of the 4th layer of E, supply line 28a, 28b are connected with power supply source, and therefore this and can be powered for second surface 20 for first surface 16 power supply by the third layer D being placed in the first hole 36 and the second hole 38.
Plate 26 (more properly each chip supporting member 12) structure after step 106 is shown on Fig. 7.
Then, when step 108, chemical etching the first circuit 32 and second circuit 34 on first surface 18 and second surface 20 respectively.After etching step 108, the first circuit 32 includes contact area 40, and second circuit includes connection region 50 and tie-point 52, and includes junction point 44,46.First circuit 32 is connected with supply line 28a, 28b by branch road 32a and 32b.After an etching step, the first circuit 32 forms closed circuit, and namely all contact areas 44 are connected to each other, in order to when supply line 28a, 28b are connected with power supply source, and whole first circuit 32 and therefore second circuit 34 are passed by this electric current.
And, after etching step 108, connection region 50 is electrically insulated from each other on second surface 20, but is all connected with the first circuit 32 by the first hole 36, four layers of E of third layer D and the.Equally, junction point 44,46 is electrically coupled with the first circuit 32 by the second hole 38, four layers of E of third layer D and the.
Subsequently, in the process of optional step 110, unshowned nickel dam electrolytic deposition on the first circuit 32 and second circuit 34 and also in the first hole 36 and the second hole 38 on different accompanying drawings.The electrolytic deposition of nickel can copper and layer 5 F and and layer 6 G between implement diffusion barrier.Electrolytic deposition is implemented due to the power supply of supply line 28a, 28b.
In modification, nickel dam or the inside electrolytic deposition only on the first circuit 32 or only on second circuit 34 and in the first hole 36 and the second hole 38.
Subsequently, in the process of step 112, the 5th conductive material layer F deposits at the first circuit 32 By Electrolysis.Layer 5 F is made of gold, and gold is antioxidation and the material relative to copper friction resistant.In order to implement the electrolytic deposition of layer 5, implement the first one side electrolysis.Namely the first circuit 32 is powered by supply line 28a, 28b, and the covered component of second surface 20 hides.
Fig. 8 illustrates the equipment 200 that can implement this one side electrolysis.Equipment 200 includes the band 210 corresponding to multiple assemblies 10, described assembly along length in the distance of several meters one link with next.Band 210 also includes multiple supporting member 12 and therefore multiple plates 26, and the electrolytic deposition of layer 5 F no longer performs on the plurality of plate.Equipment 200 also includes current feedback circuit 212, and described current feedback circuit can be the first circuit 32, the mobile member 214 of assembly 10 and be powered by the chamber 216 of assembly 10 traverse.
Band 210 extends along a length thereof through chamber 216, and mobile member 214 can make to move with 210 length being parallel to this band.More properly, mobile member 214 includes to coordinate with hole 29 to drive the contact 218 with 210.
Chamber 216 includes the groove 217 being made up of the material corresponding with the material forming layer 5 F.
Equipment 200 also includes hiding component 220 (such as hiding belt), described covering component is positioned to face each second surface 20 and can hide each second surface 20 relative to groove 217, all contacts with what avoid between groove 217 with each second surface 20 (i.e. each second circuit 34).
Current feedback circuit (also referred to as power supply source 212) and covering belt 220 can make layer 5 F carry out whole electrolytic deposition on each first circuit 32, avoid being placed on second circuit 34 layer 5 F simultaneously.
The similar equipment next step 114 for making the 6th conductive material layer G on second circuit 34 and in the first hole 36 and the inside electrolytic deposition in the second hole 38.This equipment is configured to the covering component similar to hiding belt 220 to hide each first surface 16.
The electrolytic deposition step 112,114 of layer 5 F and layer 6 G is implemented by the connection of supply line 28a, 28b and power supply source 212, the four layers of E of third layer D and the being arranged in the first hole 36 and the second hole 38 guarantee electric current transmission on second circuit 34, for the electrolytic deposition of layer 6 G.Therefore, the electrolytic deposition step 112,114 of layer 5 F and layer 6 G by circuit 32 and 34 with only implement in the connection of the power supply source 212 of described circuit 32 side.
After the electrolytic deposition step 114 of layer 6 G, the first circuit 32 and second circuit 34 by the first hole 36 and the second hole 38 and are arranged in the third layer D in the first hole 36 and the second hole 38, the 4th layer of E and layer 6 G and connect.
More generally, supply line 28a, 28b mono-aspect electrically couple with each first circuit 32 by means of branch road 32a, 32b, on the other hand by means of the third layer D being arranged in the first hole 36 and the second hole 38, the 4th layer of E and layer 6 G, electrically couple with each second circuit 34 also by way of corresponding each first circuit 32 and branch road 32a, 32b.
When chip 51 is fixed on second surface 20 (more properly making chip 51 connect with corresponding connection region 50) time, the electric line that contact area 40 is coupled to each other that can make of the first circuit 32 is removed, so that territory, different contact zone 40 electric insulation, therefore make connection region 50 and junction point 44,46 electric insulation.
The use of third layer D can make the first hole 36 and the second hole 38 electrically susceptibleization and it can be avoided that be similar to the supply line of circuit 28a, 28b on surface 18 and the therefore use on each second surface 20.Such as, due to the electrolytic deposition of layer 6 G, the layer (such as the electric conductor between the first circuit 32 and second circuit 34) being present in the first hole 36 and the second hole 38 use it can be avoided that supply line 28a, 28b use on second surface 20.But, if second surface includes the supply line being similar to circuit 28a, 28b, then, when layer 6 G electrolytic deposition, layer 6 G will be arranged on this circuit, and this causes that the cost of golden this kind of material increases.
Therefore the manufacturing cost of chip supporting member 12 and therefore assembly 10 reduces, this is because the amount of the gold used reduces, it is known that the thickness of layer 6 G is more than the thickness F of layer 5.
Chip 52 and the connection connecting region 50 are easier to, this is because connection region 50 electrically couples with hole 32, and the shape in described connection region is optimised, so that chip is close as far as possible with the connection lug of second circuit 34 (namely with connection region 50).This can reduce the space connected between lug and connection region 50, and therefore reduces the space occupied by the wire 54 making described lug couple with corresponding connection region 50.Additionally, the size in the first hole 36 and the second hole 38 is reduced, because relative to supporting member 502 of the prior art, it does not have wire this some holes of traverse.And, the surface occupied by second circuit 34 is reduced, and this can manufacture chip supporting member 12, forms the first surface 16 of tetragon and second surface 20 for described chip supporting member, and the length of the most minor face of described tetragon is equal to 9.5mm, and error span is 2%.
In the second embodiment illustrated on Fig. 9 and Figure 10, what the element similar to first embodiment had has been increased the same reference numerals of 300.Chip supporting member assembly 310 also includes six chip supporting members 312.First embodiment and the second embodiment global similarity.Additionally, the band that assembly 310 is formed two being disbursed from the cost and expenses bearing member 312 of including some rows of the width W310 along assembly 310, this two string being disbursed from the cost and expenses in bearing member is arranged in another row rear along the length L310 of assembly 310.Each supporting member 312 includes first surface 316 and second surface 320, and includes the plate 326 forming first surface 316 and second surface 320.
Supply line 328a, 328b are arranged on the both sides of chip supporting member 312, longitudinal edge 322,324 place on surface 316.
Each first surface 316 includes the first circuit 332, and each second surface 320 includes second circuit 334.Supply line 328a, 328b and the first circuit 332 are electrically coupled and are electrically coupled with second circuit 234 by the conductive layer that is arranged in the first hole 336 and the second hole 338.
The length L312 along supply line's 328a, 328b measurement of each supporting member is equal to 14.25mm.In this embodiment, therefore similar from the size of chip supporting member 502 of the prior art and supporting member 12 with first embodiment the size of the size of supporting member is different.
Additionally, each first circuit 332 includes contact area 340.Each second circuit 334 includes two junction points 344,346 being connected with wireless aerial, and includes connection region 350 and tie-point 352.
The manufacture method global similarity of the manufacture method of chip supporting member 312 and chip supporting member 12.
As in the first embodiment, assembly 310 (more properly chip supporting member 312) can reduce the amount of the gold used when manufacturing supporting member 312.The reduction of the amount of this used gold can reduce manufacturing cost.
In modification, each second surface 20 or 320 includes the supply line similar with supply line 28a, 28b, 328a, 328b.
According to another modification, each first surface 16 or 316 does not include supply line, and only each second surface 20 or 320 includes the supply line similar with supply line 28a, 28b, 328a, 328b.
According to another modification, each first surface 16 includes the single supply line connected with the first corresponding circuit 32.
According to another modification, chip supporting member assembly 10 or 310 includes more than two chip supporting member along its length.
The embodiment being considered above and the feature of modification can combinations with one another.
Claims (14)
1. at least one electronic chip supporting member (12；312) manufacture method, described supporting member is by plate (26；326) making, described plate includes:
-for the first surface (16 that contacts with chip reader；316),
-the second surface (20 contrary with described first surface；320), described second surface is covered by the first conductive material layer (A) and for coupling with wireless aerial, and
-the core (35) making described first surface (16) and described second surface (20) separate be made up of electrically insulating material,
Said method comprising the steps of:
-a) along the direction (X36) brill (100) vertical with described plate through described plate (26；326) at least one through hole (36,38；336,338),
-b) the second conductive material layer (C) is placed (102) at described first surface (16；316), on, described second conductive material layer can cover one or more hole (36,38；336,338), and
-c) respectively at first surface (16；316) and second surface (20；320) upper chemical etching (108) first circuit (32；332) and second circuit (34；334),
It is characterized in that, described method includes the following steps before chemical etching (108) step:
-b1) the 3rd conductive material layer (D) is placed on one or more hole (36,38；336,338), in, described 3rd conductive material layer (D) is by being applicable to cover the one or more holes (36,38 in correspondence of described core (35)；336,338) conductive material of the electrically insulating material in is made, in chemical etching (108) step c) after, the 3rd conductive material layer makes the first circuit (32；332) with second circuit (34；334) electrically couple.
2. manufacture method according to claim 1, it is characterised in that place (104) step b) after and in chemical etching (108) step c) before, said method comprising the steps of:
-b2) by only making two surfaces (16,20；316,320) one in is connected with power supply source and makes the 4th conductive material layer (E) on second surface (20) and in each hole (36,38；336,338) inside electrolytic deposition (106).
3. manufacture method according to claim 1 and 2, it is characterised in that after chemical etching (108) step, said method comprising the steps of:
-d) make the 5th conductive material layer (F) at first surface (16；316) By Electrolysis deposition (112),
-e) make the 6th conductive material layer (G) at second surface (20；320) By Electrolysis deposition (114),
It is characterized in that, electrolytic deposition (112, the 114) step of the 5th conductive material layer and the 6th conductive material layer is by making the first circuit (32) and second circuit (34) implement with being only connected at the power supply source (212) of described first circuit (32) side.
4. manufacture method according to claim 3, it is characterised in that implement the first one side electrolysis, second surface (20 when electrolytic deposition (112) step of the 5th conductive material layer (F)；320) hidden component (220) by first to hide, and implement the second one side electrolysis, first surface (16 when the electrolytic deposition step of the 6th conductive material layer (G)；316) hidden component by second to hide.
5. the manufacture method according to any one of claim 2 to 4, it is characterized in that, electrolytic deposition (112 at the 5th conductive material layer (F) and the 6th conductive material layer (G), 114) before, the nickel dam at least one By Electrolysis deposition in the 3rd conductive material layer (D) and the 4th conductive material layer (E).
6. the manufacture method according to any one of the claims, it is characterised in that the 3rd conductive material layer (D) is made up of the material based on carbon.
7. the manufacture method according to any one of claim 3 to 5, it is characterised in that the 5th conductive material layer (F) and the 6th conductive material layer (G) are made up of the material based on gold.
8. the manufacture method according to any one of the claims, it is characterised in that bore the first hole (36 when holing (100) step；336) and the second hole (38；338), described first hole (36；336) chip reader and first surface (16 it are drilled in；316) one or more contact areas (40；340) near, and described second hole (38；338) the one or more contact area (40 it is drilled in；340) outside, and, after etching (108) step, second circuit (34；334) two junction points (44,46 being connected with wireless aerial are included；344,346), and electrical continuity (48,49) be maintained at each second hole (38；338) with corresponding junction point (44,46；344,346) between.
9. the manufacture method according to claim 2 or 8, it is characterised in that after etching (108) step, second circuit (34；334) include and one or more connection regions (50 of chip connection；350), each connection region (50；350) by the 4th conductive material layer (E) with the first corresponding hole (36；336) electrically couple.
10. an electronic chip supporting member (12；312), described supporting member includes plate (26), and described plate includes:
The described plate (26 of-traverse；326) at least one through hole (36,38；336,338), at least one through hole described along the direction (X36) vertical with described plate,
-include the first circuit (32；332) first surface (16 and for contacting with chip reader；316), described first circuit (32；332) at described first surface (16；316) side covers one or more holes (36,38；336,338),
-the second surface (20 contrary with described first surface；320), described second surface includes second circuit (34；334) and for coupling with wireless aerial,
-made described first surface (16 by what electrically insulating material was made；316) with described second surface (20；320) core (35) separately,
It is characterized in that, conductive material layer (C) is arranged in one or more hole (36,38；336,338), in, described conductive material layer (C) covers the electrically insulating material in corresponding one or more holes and makes described first circuit (32；332) with described second circuit (34；334) electrically couple.
11. supporting member according to claim 10, it is characterised in that first surface (16) forms tetragon, and the length (L12) of the most minor face of described tetragon is equal to 9.5mm, and error span is 2%.
12. the supporting member according to claim 10 or 11, it is characterised in that second circuit (34；334) include and one or more connection regions (50 of chip connection；350), each connection region (50；350) with corresponding hole (36；336) electrically couple.
13. the assembly (10 of a chip supporting member；310), described assembly includes two edges (22,24 along its width (W10)；322,324) with at said two edge (22,24；322,324) at least two chip supporting member (12 between；312), it is characterised in that described chip supporting member is for according to any one of claim 10 to 12.
14. assembly according to claim 13, it is characterised in that described assembly include only on surface (14,18) with first surface (16；316) or with second surface (20；320) at least one corresponding supply line (28a, 28b；328a, 328b), described at least one supply line extends and or by means of branch road (32a, 32b) or by means of being arranged in one or more hole (36,38 along the length of described assembly；336,338) at least one conductive material layer (D, E, G) in and with each corresponding circuit (32,34；322,324) electrically couple.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1361300A FR3013504B1 (en) | 2013-11-18 | 2013-11-18 | METHOD FOR MANUFACTURING AN ELECTRONIC CHIP HOLDER, CHIP HOLDER AND SET OF SUCH HOLDERS |
| FR1361300 | 2013-11-18 | ||
| PCT/FR2014/052955 WO2015071619A1 (en) | 2013-11-18 | 2014-11-18 | Method for producing an electronic chip support, chip support and set of such supports |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105793983A true CN105793983A (en) | 2016-07-20 |
| CN105793983B CN105793983B (en) | 2019-04-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480062932.7A Active CN105793983B (en) | 2013-11-18 | 2014-11-18 | The component of the manufacturing method of electronic chip supporting member, chip supporting member and this supporting member |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9799598B2 (en) |
| CN (1) | CN105793983B (en) |
| DE (1) | DE112014005250B4 (en) |
| FR (1) | FR3013504B1 (en) |
| WO (1) | WO2015071619A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107025481B (en) * | 2016-02-02 | 2021-08-20 | 上海伯乐电子有限公司 | Flexible printed circuit board, smart card module using same and smart card |
| FR3051063B1 (en) | 2016-05-06 | 2021-02-12 | Linxens Holding | PROCESS FOR MANUFACTURING CHIP CARDS AND CHIP CARD OBTAINED BY THIS PROCESS |
| WO2023052804A1 (en) | 2021-09-29 | 2023-04-06 | Linxens Holding | Printed circuit for integration into a smart card, smart card with such a printed circuit and reel-to-reel tape for use in a fabrication process of a smart card |
| FR3127578B1 (en) | 2021-09-30 | 2023-09-15 | Linxens Holding | Humidity sensor |
| FR3127577B1 (en) | 2021-09-30 | 2023-10-06 | Urgo Rech Innovation Et Developpement | Coupon for medical device with humidity sensor, corresponding medical device, system, and method. |
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| FR2880160B1 (en) | 2004-12-28 | 2007-03-30 | K Sa As | DOUBLE-SIDED ELECTRONIC MODULE FOR HYBRID CHIP CARD |
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- 2014-11-18 WO PCT/FR2014/052955 patent/WO2015071619A1/en active Application Filing
- 2014-11-18 CN CN201480062932.7A patent/CN105793983B/en active Active
- 2014-11-18 US US15/036,927 patent/US9799598B2/en active Active
- 2014-11-18 DE DE112014005250.7T patent/DE112014005250B4/en active Active
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| US6522014B1 (en) * | 2000-09-27 | 2003-02-18 | International Business Machines Corporation | Fabrication of a metalized blind via |
| US20070170564A1 (en) * | 2005-12-21 | 2007-07-26 | Infineon Technologies Ag | Chip card module |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20160293536A1 (en) | 2016-10-06 |
| CN105793983B (en) | 2019-04-02 |
| FR3013504B1 (en) | 2022-06-10 |
| FR3013504A1 (en) | 2015-05-22 |
| DE112014005250T5 (en) | 2016-10-06 |
| US9799598B2 (en) | 2017-10-24 |
| WO2015071619A1 (en) | 2015-05-21 |
| DE112014005250B4 (en) | 2020-04-02 |
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