CN105789209B - 3-D stacks semiconductor structure and its manufacturing method - Google Patents
3-D stacks semiconductor structure and its manufacturing method Download PDFInfo
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- CN105789209B CN105789209B CN201410808686.7A CN201410808686A CN105789209B CN 105789209 B CN105789209 B CN 105789209B CN 201410808686 A CN201410808686 A CN 201410808686A CN 105789209 B CN105789209 B CN 105789209B
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Abstract
The invention discloses a kind of 3-D stacks semiconductor structure and its manufacturing method, the 3-D stacks semiconductor structures, comprising: multiple laminations are vertically formed on a substrate and are parallel to each other, and a dielectric layer is formed on lamination；Multiple conductive plugs are individually formed at dielectric layer；It is formed on dielectric layer with a metal-oxide semiconductor (MOS) (MOS) layer.One of these laminations include multiple multilayer cylinders, and each multilayer cylinder includes that multilayer dielectric layer and plurality of conductive layers alternative stacked form.MOS layers include that multiple MOS structures are electrically connected with conductive plug respectively, to select and decode layer plane to be operated as layer selector.
Description
Technical field
The invention relates to a kind of 3-D stacks semiconductor structure and its manufacturing methods, and in particular to one kind three
Tieing up laminated semiconductor structure, it forms a metal oxide between stacked memory cells and metal wound wire (metal routes)
Semiconductor (MOS) layer (source contacts) is used and its manufacturing method of structure with selecting as layer choosing.
Background technique
Non-volatile memory device has a very big characteristic to be in design, when memory component loses or remove electricity
Remain to save the integrality of data mode behind source.There are many non-volatile memory devices of different shaped state to be mentioned for industry at present
Out.But related dealer still constantly researches and develops new design or combines the prior art, carries out the lamination of storage unit plane to reach
To the memory construction with more high storage capacity.Such as has some 3-D stacks NAND gate (NAND) type flash memory structures and mentioned
Out.However, traditional 3-D stacks memory construction still has some problem needs to be solved.
Fig. 1 is a kind of perspective view of 3D laminated semiconductor structure.It is to be painted a kind of 3DNAND memory array organization in Fig. 1
For explain.3D laminated semiconductor structure includes array region 11 and fan-out area (fan-out region) 13.Multilayer battle array
Column are formed on an insulating layer, and including a plurality of wordline 125-1WL ..., 125-N WL, with the tropisms such as multiple laminations
It is formed.Multiple laminations include semiconductor bar 112,113,114,115.Semiconductor bar in same level is to pass through hierarchic structure
(also known as bit line structure) and electric property coupling is together.(also known as bonding pad structure/the position hierarchic structure 102B, 103B, 104B, 105B
Line connection pad) termination semiconductor bar (such as semiconductor bar 102,103,104,105).As shown, these hierarchic structures
102B, 103B, 104B, 105B are electrically connected to different bit lines, for being connected to decoding circuit, for selecting within this array
Plane.The semiconductor bar 102,103,104,105 of lamination has source electrode line end to bit line extreme direction.The semiconductor bar of lamination
102, it 103,104,105 is terminated in one end by hierarchic structure (bonding pad structure/bit line connection pad) 102B, 103B, 104B, 105B,
Pass through serial selection line (SSL, string selection lines) gate structure 109, ground connection selection line GSL 127, wordline
125-N WL to 125-1WL, ground connection selection line GSL 126, and terminated by source line (by the other parts of figure in the other end
It covers).The semiconductor bar 112,113,114,115 of lamination is terminated in one end by hierarchic structure 112A, 113A, 114A, 115A,
By SSL gate structure 119, ground connection selection line GSL 126, wordline 125-1WL to 125-N WL, it is grounded selection line GSL 127,
And it is terminated in the other end by source electrode line 128.Source electrode line 128 includes the insulating layer (such as oxide layer) and conductive layer of cross laminates
(such as polysilicon is as grid material), and have perpendicular to the conductive material filled in the contact hole of laminated construction and hole so that each layer
Conductive layer it is external.
However, serial selection line (SSL) as shown in Figure 1 is not easy to manufacture in technique.When 3D laminated semiconductor structure
Size reduction and when needing to construct more numbers of plies and closer element spacing, process window (process window) then ten
Point narrow, production is more not easy.
In addition, dealer also proposes there is PNVG structure, it is the 3D lamination vertical gate semiconductor structure of another kenel, and PN
The reverse biased leakage current of diode, (reverse bias leakage) is most important to PNVG structure, logical to avoid increasing
The potential leakage current in road (boosted channel potential leakage).During decoding, PNVG structure needs complicated fine
Operation waveform to avoid PN junction leakage currents, also have a kind of three-phase programmed method (three-phase programming
Method it) has been proposed to carry out the decoding of PNVG structure.However, this programmed method is sufficiently complex, and also it is not easy shape
At P+/N.
Summary of the invention
The invention relates to a kind of 3-D stacks semiconductor structure and relevant manufacturing methods.According to embodiment, a gold medal
Belong to oxide semiconductor (metal-oxide-semiconductor, MOS) layer and is formed at metal wound wire (metal routes)
Between 3-D stacks storage unit.
It is to propose a kind of 3-D stacks semiconductor structure according to an embodiment, comprising: the vertical shape of multiple laminations (stacks)
It on Cheng Yuyi substrate and is parallel to each other, a dielectric layer is formed on these laminations；Multiple conductive plugs (conductive plugs)
It is individually formed at dielectric layer；It is formed on dielectric layer with a metal-oxide semiconductor (MOS) (MOS) layer.One of these laminations
Including multiple multilayer cylinders (multi-layered pillar), each multilayer cylinder includes that multilayer dielectric layer and plurality of conductive layers are handed over
It is formed for lamination.MOS layers include that multiple MOS structures are electrically connected with conductive plug respectively.
It is the manufacturing method for proposing a kind of 3-D stacks semiconductor structure according to embodiment, comprising: form multiple be stacked on
It on one substrate and is parallel to each other, wherein one of these laminations include that there is a multilayer cylinder multilayer dielectric layer and plurality of conductive layers to hand over
It is formed for lamination；A dielectric layer is formed on lamination；Multiple conductive plugs are formed to be separately located at dielectric layer；With form a metal
Oxide semiconductor (MOS) layer is on dielectric layer, and MOS layers include that multiple MOS structures are electrically connected with conductive plug respectively.
More preferably understand to have to above-mentioned and other aspect of the invention, special embodiment below, and cooperates institute's attached drawing
Formula is described in detail below.However, protection scope of the present invention is subject to be defined depending on appended claims range.
Detailed description of the invention
Fig. 1 is a kind of perspective view of 3D laminated semiconductor structure.
Fig. 2 is the schematic diagram of a 3-D stacks semiconductor structure of one embodiment of the invention.
Fig. 3~Fig. 6 is painted a MOS layers of manufacturing method of the 3-D stacks semiconductor structure of one embodiment of the invention.
Fig. 7~Fig. 9 is painted the manufacturing method for forming metal wound wire above the MOS layer of Fig. 6 according to embodiment.
Figure 10 and Figure 11 be painted respectively the 3-D stacks semiconductor structure of another embodiment of the present invention MOS layer and metal around
The schematic diagram of line.
[symbol description]
11: array region
13: fan-out area
102,103,104,105,112,113,114,115,25-1,25-2,25-3,25-4: semiconductor bar
102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A: hierarchic structure
125-1WL、...、125-N WL、WL、WL0、WL31: wordline
BL、BLN、BLN+1, BL-1, BL-2, BL-3, BL-4: bit line
109,119, SSL: serial selection line
126,127, GSL: ground connection selection line
128, SL: source electrode line
20: substrate
21,22,23,24: lamination
21-1,22-1,23-1,24-1,24-2: multilayer cylinder
211,221,231,241: insulating layer
213,223,233,243: conductive layer
215,225,235,245: electric charge capture layer
21G, 22G, 23G, 24G: grid
26,36: dielectric layer
27-1,27-2,27-3,27-4: conductive plug
28-1,28-2,28-3,28-4: patterned polysilicon layer
281a, 282a, 283a, 284a: undoped polycrystalline silicon
281b, 282b, 283b, 284b: heavily doped polysilicon
29-1,29-2,29-3,29-4: patterned oxide layer
29S-1: gate oxide
29G-1,29G-2,29G-3,29G-4: island grid
31,32,33,34:MOS structure
35: bit line connection pad selector
411,412,413,414: grid line contact
431,432,433,434: source line contact
451,452,453,454: bit line contact
471,472,473,474: the contact of bit line connection pad selector
51,52,53,54: layer selection line
MOS: metal oxide semiconductor layer
Layer-1, Layer-2, Layer-3, Layer-4: layer plane
BPl, BP2, BP3, BP4: bit line connection pad
A1: first area
A2: second area
ML1: the first metal layer
ML2: second metal layer
ML3: third metal layer
Specific embodiment
The embodiment of the content of present invention is to propose 3-D stacks semiconductor structure and relevant manufacturing method.In embodiment,
One metal-oxide semiconductor (MOS) (metal-oxide-semiconductor, MOS) layer is formed at metal wound wire (metal
Routes) between 3-D stacks storage unit.MOS layers of single layer of embodiment include multiple MOS structures as layer selector
(layer-selectors), to select and decode layer plane to be operated (to-be-operated plane/layer).Again
The 3-D stacks semiconductor structure of person, embodiment can be decoded via simple and reliable method.
The embodiment of the present invention can apply the 3-D stacks semiconductor structure in a variety of kenels.For example, embodiment can answer
With, but without limitation in the 3-D stacks semiconductor structure or conventional finger-type of a three-dimensional PNVG kenel are rectilinear
(finger VG type) 3-D stacks semiconductor structure.It is to propose related embodiment below, cooperation diagram is to be described in detail this
Invent proposed 3-D stacks semiconductor structure and its relevant manufacturing method.However the present invention is not limited to this.Implement
Narration in example, such as thin portion structure, processing step and material application, are used by way of example only, are not intended to the present invention
The range of protection limits.
Furthermore the present invention not shows all possible embodiment.It can be without departing from the spirit and scope of the present invention
Structure and technique are changed and modified, to meet the needs of practical application technique.Therefore, not in it is proposed by the present invention other
State sample implementation may also can be applied.Furthermore the dimension scale in schema is not drawn according to actual product equal proportion.Therefore,
Specification and diagramatic content are only described herein the use of embodiment, rather than are used as the scope of the present invention is limited.
Following embodiments are explained by taking a 3-D stacks semiconductor structure of similar PNVG kenel as an example, but the present invention
It is not limited to that.Fig. 2 is the schematic diagram of a 3-D stacks semiconductor structure of one embodiment of the invention.According to embodiment, one
3-D stacks semiconductor structure includes that multiple laminations (stacks) 21,22,23,24 are vertically formed on a substrate 20 and mutually put down
Row, and one of these laminations 21,22,23,24 include multiple multilayer cylinders (multi-layered pillar) such as Fig. 2
The 21-1 of middle illustration, 22-1,23-1,24-1,24-2.Each multilayer cylinder include multilayer dielectric layer 211,221,231,241 (such as
Oxide layer) and plurality of conductive layers 213,223,233,243 (such as polysilicon layer) alternative stacked form.It a pair of insulating layer and leads
Electric layer (such as insulating layer 211 and conductive layer 213) is an OP layers.
Furthermore one of these laminations 21,22,23,24 also include multiple electric charge capture layer (charging
Trapping layers) 215,225,235,245 it is respectively formed in multilayer cylinder (such as 21-1,22-1,23-1,24-1,24-
2) side wall and multiple grid 21G, 22G, 23G, 24G (wordline WL, serial selection line SSL and ground connection selection line GSL) shape
At on electric charge capture layer 215,225,235,245, and fill up positioned at multilayer cylinder (such as 21-1,22-1,23-1,24-1,
24-2) the gap of the adjacent charge trapping layer 215,225,235,245 on side wall.Lamination 21,22,23,24 and grid 21G,
22G, 23G, 24G are extended along first direction (direction i.e.y-).
Furthermore the 3-D stacks semiconductor structure of embodiment also includes multiple semiconductor bar (semiconductor
Strips) 25-1,25-2,25-3,25-4, semiconductor bar 25-1,25-2,25-3,25-4 are respectively along the second direction (side i.e.x-
To) extend.Wherein second direction is perpendicular to first direction.As shown in Fig. 2, each semiconductor bar (such as 25-1,25-2,25-3,
25-4) be the different laminations (such as 21,22,23,24) that connection is located at same level layer multilayer cylinder (such as 21-1,22-1,
23-1,24-1,24-2) conductive layer.For example, semiconductor bar 25-1 (extending along the direction x-) is the different laminations 21,22 of connection,
The conductive layer 213 for being located at same level layer and being denoted as layer-1 of 23,24 multilayer cylinder 21-1,22-1,23-1,24-1,
223,233,243.Similar, semiconductor bar 25-2 is multilayer cylinder 21-1, the 22-1 for connecting different laminations 21,22,23,24,
The conductive layer 213,223,233,243 for being located at same level layer and being denoted as layer-2 of 23-1,24-1.Semiconductor bar 25-3 is
The same level layer that is located at for connecting multilayer the cylinder 21-1,22-1,23-1,24-1 of different laminations 21,22,23,24 is denoted as
The conductive layer 213,223,233,243 of layer-3；Semiconductor bar 25-4 is the multicolumn for connecting different laminations 21,22,23,24
The conductive layer 213,223,233,243 for being located at same level layer and being denoted as layer-4 of body 21-1,22-1,23-1,24-1.Cause
Fig. 2 draws angular relationship, though other semiconductor bars of other multilayer cylinders and connection same level layer are in the presence of being not shown in
In figure.
Furthermore the 3-D stacks semiconductor structure of embodiment also includes multiple bonding pad structures, such as bit line connection pad (bit
Line pads) BP1, BP2, BP3, BP4, it is electrically connected to semiconductor bar 25-1,25-2,25-3,25-4, wherein being located at identical
The semiconductor bar 25-1,25-2,25-3,25-4 of plane layer are electrically connected with bonding pad structure BP1, BP2, BP3, one of BP4
It connects.It is coupled to bit line connection pad BP1 together for example, being generally aligned in the same plane and being denoted as the semiconductor bar 25-1 of Layer-1；Positioned at same
The semiconductor bar 25-2 that one plane is denoted as Layer-2 is coupled to bit line connection pad BP2 together；It is generally aligned in the same plane and is denoted as
The semiconductor bar 25-3 of Layer-3 is coupled to bit line connection pad BP3 together；It is generally aligned in the same plane and is denoted as partly leading for Layer-4
Body 25-4 is coupled to bit line connection pad BP4 together.
The 3-D stacks semiconductor structure of the similar PNVG kenel illustrated herein, a serial selection line (string
Selection line, SSL) (i.e. is folded for (i.e. lamination 21) and ground connection selection line (ground selection line, GSL)
24) layer is progressive forming (configured continuously), as the structure that wordline is successively opened.Furthermore it connects
Mat structure such as bit line connection pad BP1, BP2, BP3, BP4 respectively includes a first area A1 and a second area A2 connection first area
A1.It is noted that the present invention is not restricted to this similar to the state sample implementation of PNVG, the vertical gate of other kenels also can be applied to
Pole (VG) 3-D stacks semiconductor structure.First area A1/ second area A2 is, for example, the region N+/n-quadrant or the region P+/area N
Domain.It is to form the region N+/n-quadrant as first area A1/ second area A2 in one embodiment.
3-D stacks semiconductor structure further includes metal wound wire (the metal routes, such as the first metal layer of different layers
ML1, second metal layer ML2, third metal layer ML3) in such as 21,22,23,24 top of lamination.According to an embodiment of the invention, one
TFT metal-oxide semiconductor (MOS) (MOS) layer is formed at metal wound wire and (the tool 3-D stacks storage list of lamination 21,22,23,24
Member) between.In embodiment, the MOS layer for being formed in a dielectric layer includes multiple MOS structures, as layer selector
(1ayer-selectors) is to select and decode layer plane to be operated (to-be-operated plane/layer).It is thin
Section description is as after.
In embodiment, bit line connection pad BP1, BP2, BP3, the doping type of first area A1 and second area A2 that BP4 is respectively wrapped
Depending on state and doping concentration are the kenel according to the MOS structure of the top of lamination 21,22,23,24.For example, if MOS structure is
NMOS, then bit line connection pad BP1, BP2, BP3, the first area A1 and second area A2 of BP4 is respectively the region N+ and n-quadrant
(doping concentration that the dopant concentration of i.e. second area A2 is lower than first area A1).In another embodiment, if MOS structure
It is PMOS, then bit line connection pad BP1, BP2, BP3, the first area A1 and second area A2 of BP4 is respectively the region P+ and n-quadrant
(first area i.e. A1 be the dopant for adulterating different kenels with second area A2).
Fig. 3~Fig. 6 is painted a MOS layers of manufacturing method of the 3-D stacks semiconductor structure of one embodiment of the invention.It is real
The MOS layer for applying example is to be located at 21,22,23,24 top of lamination as layer selector (layer-selectors) to select and decode
Layer plane to be operated, and metal wound wire is then formed in MOS layers of top.Fig. 7~Fig. 9 is painted according to an embodiment in the MOS of Fig. 6
Layer top forms the manufacturing method of metal wound wire.Referring to Fig. 2, in reference implementation example 3-D stacks semiconductor structure
Related elements.
Firstly, providing a substrate 20 (tool buried oxide), multiple laminations such as 21,22,23,24 are formed perpendicular to substrate 20
On, each lamination 21,22,23,24 includes multiple multilayer cylinder such as 21-1,22-1,23-1,24-1,24-2.Each multilayer cylinder packet
Include multilayer dielectric layer 211,221,231,241 (such as oxide layer) and plurality of conductive layers 213,223,233,243 (such as polysilicon
Layer) alternative stacked form (Fig. 2).A pair of insulating layer and conductive layer (such as insulating layer 211 and conductive layer 213) is an OP layers.
Each multiple stacked memory cells of lamination (stacking cells), plurality of layer plane (such as Layer-1, Layer-2,
Layer-3, Layer-4) it is vertical stack, these storage units of lamination are to be arranged in cubical array.Furthermore charge-trapping
Layer (charging trapping layers) (such as 215,225,235,245) be respectively formed in multilayer cylinder (such as 21-1,
22-1,23-1,24-1,24-2) side wall and multiple grid 21G, 22G, 23G, 24G (wordline WL, serial selection line SSL
With ground connection selection line GSL), semiconductor bar (such as 25-1,25-2,25-3,25-4) and bonding pad structure (such as bit line connection pad BP1,
BP2, BP3, BP4) it is that mode as shown in Figure 2 is formed.
One MOS layers is formed above lamination (such as 21,22,23,24).As shown in figure 3, a such as oxide layer of dielectric layer 26
Lamination (such as 21,22,23,24) are formed at, as on a dielectric flatness layer (providing a planarization surface).Later, along
Third direction (direction i.e.z-) forms multiple conductive plug (conductive plugs) 27-1, and 27-2,27-3,27-4 is independently
At dielectric layer 26, and correspond to bit line connection pad (such as BP1, BP2, BP3, BP4) to reach different layer plane (such as Layer-
1, Layer-2, Layer-3, Layer-4).These conductive plugs such as 27-1,27-2,27-3,27-4 are also referred to as MiLC polysilicon
Plug (MiLC polysilicon plugs).In one embodiment, the production of conductive plug, which can be, is initially formed consent (plug
Holes) and filling N+ or P+ polysilicon is in consent, is then carried out with CMP (being parked on dielectric layer 26) or other suitable techniques
Planarization.According to embodiment, MOS layers include that multiple MOS structures electrically connect with conductive plug such as 27-1,27-2,27-3,27-4 respectively
It connects as layer selector.
Conductive plug can be N+ polysilicon plug or P+ polysilicon plug.In one embodiment, if MOS structure is NMOS,
Then conductive plug such as 27-1,27-2,27-3,27-4 be N+ polysilicon, wherein bonding pad structure (such as bit line connection pad BP1, BP2, BP3,
BP4 first area A1 and second area A2) is respectively that (dopant concentration of i.e. second area A2 is low for the region N+ and n-quadrant
In the doping concentration of first area A1).In one embodiment, if MOS structure is PMOS, conductive plug such as 27-1,27-2,27-
3,27-4 be P+ polysilicon, and the first area A1 and second area A2 of neutrality line connection pad BP1, BP2, BP3, BP4 are respectively P+
Region and n-quadrant.
Later, the production of MOS structure is carried out.Firstly, multiple patterned polysilicon layer 28-1,28-2,28-3,28-4 are formed
In on dielectric layer 26 and multiple patterned oxide layer 29-1,29-2,29-3,29-4 are formed in patterned polysilicon layer 28-1,
On 28-2,28-3,28-4, as shown in Figure 4 A and 4 B shown in FIG..Fig. 4 B is the patterned oxide layer drawn along the hatching 4B-4B of Fig. 4 A
With the sectional view of patterned polysilicon layer.In Fig. 4 A and Fig. 4 B, be with four groups of polysilicon strips (respectively include a patterned oxide layer and
One patterned polysilicon layer) it is separately connected and (thereon such as covering) explains for conductive plug 27-1,27-2,27-3,27-4.System
A undoped polycrystalline silicon can be first deposited when making, then covers an oxide deposition (being used for bigrid and hardmask), later
It is patterned and is obtained.
Later, multiple island grids (island gates) 29G-1,29G-2,29G-3,29G-4 is formed, such as Fig. 5 A institute
Show.Referring to Fig. 5 B, for the sectional view of the island grid 29G-1 drawn along the hatching 5B-5B of Fig. 5 A.Make island
Can be initially formed when grid a gate oxide (GOX) (such as 29S-1) overlay pattern polysilicon layer (such as 28-1,28-2,28-3,
Side wall 28-4) re-forms patterned oxide layer (such as 29-1,29-2,29-3,29-4) and one polysilicon layer of deposition in it later
On, then carry out island gate patterning process.Wherein, island grid 29G-1,29G-2,29G-3,29G-4 system overlay pattern
Oxide layer and gate oxide.Furthermore island grid 29G-1,29G-2,29G-3,29G-4 are insulated from each other, such as island grid
Pole 29G-1 electrically isolates from island grid 29G-2,29G-3 and 29G-4.
Then, self-aligned source/drain electrode injection (self-aligned S/D implantation) is carried out with dopant patterns
Change polysilicon layer, makes patterned polysilicon layer (such as 28- covered by island grid (such as 29G-1,29G-2,29G-3,29G-4)
1,28-2,28-3,28-4) part (such as 281a, 282a, 283a, 284a) be undoped polycrystalline silicon, and do not hidden by island grid
The patterned polysilicon layer rest part (such as 281b, 282b, 283b, 284b) covered is then heavily doped polysilicon, as shown in Figure 6.
Therefore the production of MOS structure 31,32,33,34 is completed, and MOS structure 31,32,33,34 is respectively via patterned polysilicon layer
The part 281b, 282b, 283b of heavily doped polysilicon, 284b are electrically connected to corresponding conductive plug 27-1,27-2,27-3,
27-4。
After the MOS layer for forming embodiment, several layers of metal wound wire are then formed in MOS layers of top.Fig. 7~Fig. 9 is please referred to,
It is painted the manufacturing method for forming metal wound wire above the MOS layer of Fig. 6 according to embodiment.As shown in fig. 7, one dielectric layer 36 of deposition
In on MOS layer, and carry out chemical mechanical grinding (CMP).It later, is to form island gate contact, source line contact and bit line to connect
Touching.As shown in figure 8, multiple grid line contact (gate line contacts) 411,412,413,414 are respectively formed in MOS knot
On island the grid 29G-1,29G-2,29G-3,29G-4 of structure 31,32,33,34；Multiple source line contact (source
Line contacts) 431,432,433,434 be respectively formed in heavily doped polysilicon part (such as 281b, 282b, 283b,
284b part) sentence connection source electrode line；And 451,452,453,454 shapes of multiple bit line contacts (bit line contacts)
At in dielectric layer 36.
Then, the production of multiple layer metal coiling is carried out above MOS structure.As shown in figure 9, several layer of selection line
(layer-selector lines, such as the first metal wire) 51,52,53,54 is respectively formed in grid line contact 411,412,
It is formed on source line contact 431,432,433,434 with source line SL to be electrically connected on 413,414.Wherein, these
Layer selection line 51,52,53,54 is parallel to each other and (direction i.e.y-) extends along a first direction, and source electrode line SL is then parallel to
Layer selection line 51,52,53,54.Later, several bit line (such as second metal wires) BL-1, BL-2, BL-3, the insulated formation of BL-4
In the top of layer selection line 51,52,53,54, as shown in Figure 9.Bit line BL-1, BL-2, BL-3, BL-4 are along second direction
(direction i.e.x-) extends and perpendicular to layer selection line 51,52,53,54 and source electrode line SL.
According to embodiment, and though OP layers of the number of plies have it is several layers of, it is only necessary to MOS layers of MOS structure is made with a single layer process
(such as 31,32,33,34), therefore technique can be simplified and expand process window.The present invention is well suited for three for making minification
Tie up laminated semiconductor structure.Furthermore the interpretation method of the 3-D stacks semiconductor structure of embodiment be through selection wordline (WL),
Bit line (BL) and the transistor (MOS structure in TFT, i.e. MOS layers is to select OP layers) of top and carry out, to decode three-dimensional perpendicular
The storage unit of grid.Whether therefore interpretation method is simple, without the concern for needing using special operation waveform.
In addition, the 3-D stacks semiconductor structure of embodiment is also optionally added the phase that can reduce MiLC connection pad capacitor
Close technique.Generally, MiLC connection pad capacitor is very high, and traditional decoded mode need to each MiLC connection pad of selection bit line into
Row is charged, therefore total bit line capacitance (total BL capacitance) will become because of numerous charged MiLC connection pad numbers
It is very high.But according to embodiment, each MiLC connection pad can be controlled via a MiLC connection pad selector, therefore total bit line capacitance
It can a sharp decline.A MiLC connection pad selector is opened when decoded, and only one MiLC connection pad is charged.Figure 10 and Figure 11
It is painted the schematic diagram of the MOS layer and metal wound wire of the 3-D stacks semiconductor structure of another embodiment of the present invention respectively.
As shown in Figure 10, multiple bit line connection pad selector 35 (bit line pad selectors) (i.e.MiLC connection pads
Selector, to select to charged bit line connection pad) it can be formed simultaneously with MOS structure (such as 31,32,33,34).Referring to
Fig. 5 A narration related to above-mentioned MOS structure.In one embodiment, the structure and MOS structure of bit line connection pad selector 35 (such as 31,
32,33,34) identical, details are not described herein for thin portion.To select the bit line connection pad selector 35 to charged bit line connection pad to be
Perpendicular to polysilicon strip.Furthermore each bit line connection pad selector 35 as shown in Figure 10 may be coupled to corresponding polysilicon strip, and shape
At between corresponding conductive plug (such as 27-1,27-2,27-3,27-4) and MOS structure (such as 31,32,33,34).
Later, the metal wound wire of relevant contact (contacts) sum number layer is formed.Referring to Fig. 8 and Fig. 9.Such as figure
Shown in 11, grid line contact 411,412,413,414 and source line contact 431,432,433,434 and bit line contact are being formed
When 451,452,453,454, multiple bit line connection pad selector contact (bit line pad selector are also formed
Contacts) 471,472,473,474.Furthermore in forming layer selection line 51,52,53,54 and source electrode line SL, also form position
Line connection pad selection line (such as 55) is in bit line connection pad selector contact (such as 471,472,473,474).When decoding, when bit line connection pad
Selector 35 is opened, and only selects a corresponding bit line connection pad (i.e.MiLC connection pad) charged.Decoding according to this embodiment
Mode, be via one of MOS structure (such as 31,32,33,34) selection it is corresponding OP layer, and pass through bit line connection pad selector 35 it
One selection is intended to a charged bit line connection pad.Therefore, the bit line capacitance of the 3-D stacks semiconductor structure of embodiment can substantially drop
It is low.
It is to form a MOS layers in metal wound wire and 3-D stacks according to above-described embodiment, in 3-D stacks semiconductor structure
Between storage unit.MOS layers include multiple MOS structures with as layer selector (layer-selectors), to select and decode
Layer plane to be operated.According to embodiment, and though OP layers of the number of plies have it is several layers of, it is only necessary to make MOS layers with a single layer process
MOS structure, thus technique can be simplified and expand process window.Therefore, the 3-D stacks semiconductor structure of embodiment not only has
The good characteristic electron of reliability is particularly suited for the 3-D stacks semiconductor structure of production small size.Furthermore the three of embodiment
The interpretation method of dimension laminated semiconductor structure is transistor (TFT, i.e. MOS through selection wordline (WL), bit line (BL) and top
MOS structure in layer is to select OP layer) decode the storage unit of three-dimensional perpendicular grid, therefore decoded operation very simple with can
It leans on.In addition, the related process that can reduce MiLC connection pad capacitor is also optionally added, it is folded with the three-dimensional that embodiment is greatly reduced
Total bit line capacitance of layer semiconductor structure.Furthermore the 3-D stacks semiconductor structure of embodiment is also inexpensive using non-time-consuming
Technique is suitble to volume production in production.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various change and profit can be made
Decorations.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (10)
1. a kind of 3-D stacks semiconductor structure, comprising:
Multiple laminations are vertically formed on a substrate and are parallel to each other, and one of these laminations include multiple multilayer cylinders, respectively
These multilayer cylinders include that multilayer dielectric layer and plurality of conductive layers alternative stacked form；
One dielectric layer is formed on these laminations；
Multiple conductive plugs are individually formed at the dielectric layer；With
One metal oxide semiconductor layer is formed on the dielectric layer, and the metal oxide semiconductor layer includes multiple MOS knots
Structure is electrically connected with these conductive plugs respectively, and each MOS structure includes:
One patterned polysilicon layer is formed on the dielectric layer；
One patterned oxide layer is formed on the patterned polysilicon layer；
One gate oxide covers the side wall of the patterned polysilicon layer；With
One island grid is formed on the patterned oxide layer to cover the patterned oxide layer and the gate oxide.
2. 3-D stacks semiconductor structure according to claim 1, wherein these laminations are extended along a first direction, should
3-D stacks semiconductor structure further includes:
Multiple semiconductor bars, these each semiconductor bars be extends along a second direction and connects positioned at same level layer difference this
These conductive layers of these multilayer cylinders of a little laminations, wherein the second direction is perpendicular to the first direction；With
Multiple bonding pad structures are electrically connected to these semiconductor bars, wherein be located at same level layer these semiconductor bars be and this
One of a little bonding pad structures are electrically connected,
Wherein these conductive plugs are respectively connected to these different bonding pad structures, and these MOS structures are respectively and electrically connected to this
A little conductive plugs are as layer selector.
3. 3-D stacks semiconductor structure according to claim 2, wherein a serial selection line is progressive forming, and it is each this
A little bonding pad structures connect the first area with a second area including a first area,
Wherein the first area is the region N+ and the second area is n-quadrant, these MOS structures are NMOS structure, these are conductive
Plug is N+ conductive plug；Alternatively,
Wherein the first area is the region P+ and the second area is n-quadrant, these MOS structures are PMOS structure, these are conductive
Plug is P+ conductive plug.
4. 3-D stacks semiconductor structure according to claim 1, wherein the patterning covered by the island grid is more
Crystal silicon layer is undoped polycrystalline silicon, these MOS structures are distinguished via the heavily doped polysilicon portion of these patterned polysilicon layers
It is electrically connected to these conductive plugs；The 3-D stacks semiconductor structure further includes:
Multiple grid line contacts are respectively formed on these island grids of these MOS structures；
Multiple source line contacts are respectively formed at these heavily doped polysilicon portions；
Multiple bit line contacts are formed in the dielectric layer；
Multiple layers of selection line are respectively formed in the contact of these grid lines, and these layer of selection line is parallel to each other and along one first
Direction extends；
Source line is formed on these source line contacts, and the source electrode line is parallel to these layer of selection line；With
Multiple bit lines, the insulated top positioned at these layer of selection line, and these bit lines perpendicular to these layer of selection line and along
One second direction extends.
5. 3-D stacks semiconductor structure according to claim 1, wherein these MOS structures are to penetrate to be formed in the dielectric
Polysilicon strip on layer and be respectively and electrically connected to these conductive plugs, which further includes:
Multiple bit line connection pad selectors form vertical with these polysilicon strips, and respectively these bit line connection pad selectors are coupled to pair
These polysilicon strips answered, and be formed between these corresponding conductive plugs and these MOS structures.
6. 3-D stacks semiconductor structure according to claim 5, wherein the island grid is covered in the patterned oxide
On layer, and by the island grid cover the patterned polysilicon layer be undoped polycrystalline silicon, wherein these MOS structures be via
These patterned polysilicon layers are respectively and electrically connected to these conductive plugs, and the 3-D stacks semiconductor structure further includes:
Multiple bit line connection pad selector contacts are formed on the bit line connection pad selector；
Multiple grid line contacts are respectively formed on these island grids of these MOS structures；
Multiple source line contacts are respectively formed at the heavily doped polysilicon portion of these patterned polysilicon layers and connect source electrode line；
Multiple bit lines connection pad selection line is formed in the contact of these bit line connection pad selectors to select bit line connection pad, and these bit lines
Connection pad selection line is extended along a first direction；
Multiple layers of selection line be respectively formed in these grid lines contact on, and these layer of selection line be parallel to each other and along this first
Direction extends；
Source line is formed on these source line contacts, and the source electrode line is parallel to these layer of selection line；
Multiple bit line contacts are formed in the dielectric layer；With
Multiple bit lines, the insulated top positioned at these bit line connection pad selection lines and these layer of selection line, wherein these bit lines hang down
Directly extend in these bit line connection pad selection lines and these layer of selection line and along a second direction.
7. a kind of manufacturing method of 3-D stacks semiconductor structure, comprising:
Multiple laminations are formed perpendicular on a substrate and being parallel to each other, one of these laminations include multiple multilayer cylinders, respectively
These multilayer cylinders include that multilayer dielectric layer and plurality of conductive layers alternative stacked form；
A dielectric layer is formed on these laminations；
Multiple conductive plugs are formed to be separately located at the dielectric layer；With
A metal oxide semiconductor layer is formed on the dielectric layer, and the metal oxide semiconductor layer includes multiple MOS knots
Structure is electrically connected with these conductive plugs respectively, wherein forming each MOS structure and including:
Forming these each MOS structures includes:
A patterned polysilicon layer is formed on the dielectric layer；
A patterned oxide layer is formed on the patterned polysilicon layer；
Form the side wall that a gate oxide covers the patterned polysilicon layer；With
An island grid is formed on the patterned oxide layer.
8. manufacturing method according to claim 7, wherein these laminations are extended along a first direction, and the manufacturing method is more
Include:
Multiple semiconductor bars are formed, these each semiconductor bars are to extend along a second direction and connect positioned at same level layer not
With these conductive layers of these multilayer cylinders of these laminations, wherein the second direction is perpendicular to the first direction；With
It forms multiple bonding pad structures and is electrically connected to these semiconductor bars, wherein these semiconductors for being located at same level layer are electric
Property is connected to one of these bonding pad structures,
Wherein these conductive plugs are to be respectively connected to these different bonding pad structures, and these MOS structures are respectively and electrically connected to
These conductive plugs are as layer selector.
9. manufacturing method according to claim 7, wherein forming each MOS structure further include:
The patterned polysilicon layer is injected in self-aligned source/drain electrode, makes the patterned polysilicon layer covered by the island grid
Part be undoped polycrystalline silicon, not by the island grid cover the patterned polysilicon layer rest part be then that heavy doping is more
Crystal silicon,
Wherein these MOS structures are respectively and electrically connected to via the part of the heavily doped polysilicon of these patterned polysilicon layers
These conductive plugs.
10. manufacturing method according to claim 7, wherein these MOS structures are more on the dielectric layer through being formed in
Crystal silicon item and be respectively and electrically connected to these conductive plugs, the formation of the metal oxide semiconductor layer further includes:
It is vertical with these polysilicon strips to form multiple bit line connection pad selectors, and these each bit line connection pad selectors are coupled to pair
These polysilicon strips answered are to select a bit line connection pad, wherein the bit line connection pad selector is to be located at these corresponding conductive plugs
Between these MOS structures.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120007167A1 (en) * | 2010-07-06 | 2012-01-12 | Macronix International Co., Ltd. | 3D Memory Array With Improved SSL and BL Contact Layout |
| US20130119455A1 (en) * | 2011-11-11 | 2013-05-16 | Macronix International Co., Ltd. | Nand flash with non-trapping switch transistors |
| US20140054535A1 (en) * | 2012-08-24 | 2014-02-27 | Macronix International Co., Ltd. | Semiconductor structure with improved capacitance of bit line |
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2014
- 2014-12-23 CN CN201410808686.7A patent/CN105789209B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120007167A1 (en) * | 2010-07-06 | 2012-01-12 | Macronix International Co., Ltd. | 3D Memory Array With Improved SSL and BL Contact Layout |
| US20130119455A1 (en) * | 2011-11-11 | 2013-05-16 | Macronix International Co., Ltd. | Nand flash with non-trapping switch transistors |
| US20140054535A1 (en) * | 2012-08-24 | 2014-02-27 | Macronix International Co., Ltd. | Semiconductor structure with improved capacitance of bit line |
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