CN105789121A - Total reflection array substrate and preparation method thereof and display device - Google Patents
Total reflection array substrate and preparation method thereof and display device Download PDFInfo
- Publication number
- CN105789121A CN105789121A CN201610364884.8A CN201610364884A CN105789121A CN 105789121 A CN105789121 A CN 105789121A CN 201610364884 A CN201610364884 A CN 201610364884A CN 105789121 A CN105789121 A CN 105789121A
- Authority
- CN
- China
- Prior art keywords
- connecting line
- layer
- base palte
- array base
- total reflection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a total reflection array substrate and a preparation method thereof, relates to the technical field of liquid crystal display, and aims at solving the problems that when a metal reflection layer is prepared, switchover via holes are corroded, and preparation cost is high.The preparation method of the total reflection array substrate includes the steps that 1, a grid line, a grid electrode, a grid insulating layer, an active layer, a data line, a source electrode, a drain electrode, a passivation layer and passivation layer via holes are formed on a bearing substrate; 2, a metal reflection layer thin film is deposited on the bearing substrate, and a connecting line layer thin film is deposited on the metal reflection layer thin film; 3, a composition process is conducted through a semi-exposure mask plate, a metal reflection layer integrating a pixel electrode function and a reflection function is formed in a display region, a connecting line is formed in a peripheral integrated circuit region, and the connecting line is composed of a metal reflection layer on the lower layer and a connecting line layer on the upper layer.The method is used for preparing the total reflection array substrate.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of total reflection array base palte and preparation method thereof, display device.
Background technology
At TFT-LCD (ThinFilmTransistor-LiquidCrystalDisplay, TFT liquid crystal display) in industry, difference according to display pattern, the array base palte of LCD can be designed as TN pattern (twistednematicliquidcrystalmode, twisted liquid crystal molecules angle is the liquid crystal mode of 90 degree) or ADS pattern (ADvancedSuperDimensionSwitch, senior super dimension field switch technology, utilizes the transverse electric field that the electrode being in same plane produces to make liquid crystal produce deflection and realizes the pattern that image shows).No matter being the array base palte under TN pattern or the array base palte under ADS pattern, major part all uses transmittance structure or semi-transparent semi-reflecting structure, and liquid crystal display is required for using backlight under transmittance structure and semi-transparent semi-reflecting structure.In the prior art, the structure of backlight and complex process, cost height.A kind of total reflection array base palte is developed, it is not necessary to use backlight for this.
At present under TN pattern, the total reflection structure of total reflection array base palte is to prepare layer of metal reflecting layer on the surface of array base palte, and the light that the effect of this metallic reflector is incident to external world reflects, thus not using backlight.
(namely above-mentioned total reflection array base palte requires over 6mask, needing to use 6 mask plates) technique makes, it is followed successively by Gate (grid layer, 1st mask), active (active layer, 2nd mask), SD (source-drain electrode layer, 3rd mask), VIA (passivation layer via hole, including the via connecting thin film transistor (TFT) drain electrode and pixel electrode in array base palte viewing area, and the switching via in peripheral integrated circuit region, the 4th mask), (the connecting line layer in hole is taken in the region transfer of array substrate peripheral integrated circuit to ITO, the 5th mask) and metal (metallic reflector, simultaneously as pixel electrode, 6th mask).
But, in the preparation method of existing total reflection array base palte, owing to the compactness of ITO (the connecting line layer of switching via) is inadequate, when carrying out the preparation of metallic reflector, the etching liquid of metallic reflector can cause the corrosion of switching via.
Further, under existing preparation technology, it is necessary to use 6mask technique, relatively costly.
Summary of the invention
It is an object of the invention to provide a kind of total reflection array base palte and preparation method thereof, display device, the problem of pitting corrosion of transferring for the solution when preparing metallic reflector, and reduce cost simultaneously.
To achieve these goals, the present invention provides following technical scheme:
A first aspect of the present invention provides a kind of preparation method being totally reflected array base palte, and described array base palte includes viewing area and peripheral integrated circuit region, and described preparation method includes:
Step 1, in bearing basement, form grid line and grid, gate insulation layer, active layer, data wire and source, drain electrode, passivation layer and passivation layer via hole；
Step 2, in described bearing basement metal reflective layer thin film, and on described metallic reflection layer film deposit connecting line layer film；
Step 3, it is patterned technique by half-exposure mask plate, having the metallic reflector of pixel electrode function and reflection function concurrently in the formation of described viewing area, form connecting line in described peripheral integrated circuit region, described connecting line is made up of metallic reflector and connecting line layer.
In above-mentioned steps 1, prepared passivation layer via hole include in described viewing area connect pixel electrode and thin film transistor (TFT) drain electrode via and described peripheral integrated circuit region in switching via.
Based on the position of passivation layer via hole, above-mentioned steps 3 includes:
Step 31, there is in the bearing basement of metallic reflection layer film and connecting line layer film coating photoresist in deposition；
Step 32, being exposed by half-exposure mask plate, the position of described switching via does not expose, the position half-exposure of described pixel electrode, all the other positions expose entirely；
Step 33, form connecting line in described not exposure area, formed in described half-exposure region and have the metallic reflector of pixel electrode function and reflection function concurrently, be sequentially etched the described connecting line layer film of removal and described metallic reflection layer film in described full exposure area.
Specifically, described step 33 includes:
Step 331, in described full exposure area, be sequentially etched removal described connecting line layer film and described metallic reflection layer film；
Step 332, carry out photoresist ashing process and remove the photoresist in described half-exposure region, and etch the described connecting line layer film of removal, formed and have the metallic reflector of pixel electrode function and reflection function concurrently；
Step 333, by the photoresist lift off of described not exposure area, described not exposure area formed connecting line.
Technical scheme based on above-mentioned total reflection array base palte preparation method, a second aspect of the present invention provides one total reflection array base palte, including bearing basement, described bearing basement is formed grid line and data wire that spatial vertical is intersected, described grid line and data wire limit pixel region, thin film transistor (TFT) and pixel electrode it is provided with in described pixel region, the grid of described thin film transistor (TFT) is connected with described grid line, source electrode is connected with described data wire, drain electrode is connected with described pixel electrode, wherein, described array base palte includes viewing area and peripheral integrated circuit region, described in described viewing area, pixel electrode is made up of the metallic reflector with reflection function, described peripheral integrated circuit region is provided with switching via, the connecting line connecting described switching via is made up of metallic reflector and connecting line layer.
In described peripheral integrated circuit region, described metallic reflector directly contacts with described connecting line layer.
Described metallic reflector is made up of metal material, and described connecting line layer is made up of indium tin oxide material.
Described metal material is Mo.
Based on the technical scheme of above-mentioned total reflection array base palte, a third aspect of the present invention provides a kind of display device, including the total reflection array base palte according to any one of technique scheme.
In total reflection array base palte provided by the invention and preparation method thereof, display device, first, metallic reflection layer film and connecting line layer film sequentially form, the two is contact directly, when so carrying out half-exposure patterning processes in the step 3 preparing metallic reflector and connecting line layer, even if etching liquid is permeated by connecting line layer film, also can by metallic reflector film barrier, switching via will not be corroded, also having photoresist to stop after carrying out half-exposure even, switching via will not be corroded more；Secondly, after using half-exposure technique, the connecting line of pixel electrode and switching via is formed in a patterning processes, decreases the use of a mask plate, reduces cost.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the present invention, and the schematic description and description of the present invention is used for explaining the present invention, is not intended that inappropriate limitation of the present invention.In the accompanying drawings:
The schematic diagram of the total reflection array base palte preparation method that Fig. 1 provides for the embodiment of the present invention；
Fig. 2 a is the schematic cross-section one of the total reflection array base palte viewing area obtained by preparation method shown in Fig. 1；
Fig. 2 b is the schematic cross-section one in the total reflection array substrate peripheral integrated circuit region obtained by preparation method shown in Fig. 1；
Fig. 3 a is the schematic cross-section two of the total reflection array base palte viewing area obtained by preparation method shown in Fig. 1；
Fig. 3 b is the schematic cross-section two in the total reflection array substrate peripheral integrated circuit region obtained by preparation method shown in Fig. 1；
Fig. 4 a is the schematic cross-section three of the total reflection array base palte viewing area obtained by preparation method shown in Fig. 1；
Fig. 4 b is the schematic cross-section three in the total reflection array substrate peripheral integrated circuit region obtained by preparation method shown in Fig. 1；
Fig. 5 a is the schematic cross-section four of the total reflection array base palte viewing area obtained by preparation method shown in Fig. 1；
Fig. 5 b is the schematic cross-section four in the total reflection array substrate peripheral integrated circuit region obtained by preparation method shown in Fig. 1；
Fig. 6 a is the schematic cross-section five of the total reflection array base palte viewing area obtained by preparation method shown in Fig. 1；
Fig. 6 b is the schematic cross-section five in the total reflection array substrate peripheral integrated circuit region obtained by preparation method shown in Fig. 1；
Accompanying drawing labelling:
101-bearing basement 102-grid line
103-gate insulation layer 104-data wire
105-passivation layer 1051,1052-passivation layer via hole
106-metallic reflection layer film, metallic reflector 107-connecting line layer film, connecting line layer
108-photoresist
Detailed description of the invention
For ease of understanding, below in conjunction with Figure of description, total reflection array base palte that the embodiment of the present invention provides and preparation method thereof, display device are described in detail.
Referring to Fig. 1, the preparation method of the total reflection array base palte that the embodiment of the present invention provides includes:
Step 1, in bearing basement, form grid line and grid, gate insulation layer, active layer, data wire and source, drain electrode, passivation layer and passivation layer via hole；
The specific implementation of step 1 is identical with common practice in industry, owing to the emphasis of the embodiment of the present invention does not lie in the improvement of thin film transistor (TFT), does not therefore show the detailed structure of thin film transistor (TFT) in accompanying drawing, and shown in Fig. 2 a and 2b, this step 1 specifically includes:
First, depositing grid metal level in bearing basement 101, formed grid line 102 and grid by patterning processes, described grid line 102 is connected with grid；
Secondly, the bearing basement 101 being formed with described grid line 102 and grid deposits gate insulation layer thin film, forms gate insulation layer 103；
Afterwards, the bearing basement 101 being formed with described gate insulation layer 103 deposits active layer thin film and data metal layer thin film, is formed with active layer, data wire 104, source electrode and drain electrode by patterning processes, and described data wire 104 is connected with source electrode；
Finally, deposit passivation layer thin film in the bearing basement 101 being formed with active layer, data wire 104, source electrode and drain electrode, passivation layer 105 and passivation layer via hole 1051,1052 is formed by patterning processes.
Wherein, described array base palte includes viewing area and peripheral integrated circuit region, Fig. 2 a show viewing area, Fig. 2 b show peripheral integrated circuit region, prepared passivation layer via hole includes the via 1051 connecting pixel electrode and thin film transistor (TFT) drain electrode in the viewing area shown in Fig. 2 a, and the switching via 1052 in peripheral integrated circuit region described in Fig. 2 b, the Main Function of this switching via is connect mutual separation in peripheral integrated circuit region but needs two parts being electrically connected, include but not limited to the connection between the public electrode of same layer or two mutual separations of different layers.Passivation layer via hole is distinguish between by the present embodiment, in order to when carrying out half-exposure technique, the depth of exposure of zones of different is made a distinction.
Step 2, in described bearing basement metal reflective layer thin film, and on described metallic reflection layer film deposit connecting line layer film；
As best shown in figures 3 a and 3b, Fig. 3 a show viewing area to structure after metal reflective layer thin film 106 and connecting line layer film 107, and Fig. 3 b show peripheral integrated circuit region.
Metallic reflection layer film is generally made up of simple metal material, for instance metal Mo.The material of metallic reflector has the ability of extraneous ray of reflecting, it is not necessary to use backlight, and quality is fine and close, it is not easy to make etching liquid penetrate into.The material of connecting line layer film generally can select ITO (tin indium oxide).
Step 3, it is patterned technique by half-exposure mask plate, having the metallic reflector of pixel electrode function and reflection function concurrently in the formation of described viewing area, form connecting line in described peripheral integrated circuit region, described connecting line is made up of the metallic reflector being positioned at lower floor and the connecting line layer being positioned at upper strata.
Above-mentioned steps 3 specifically includes:
Step 31, having in the bearing basement of metallic reflection layer film and connecting line layer film coating photoresist 108 in deposition, the accompanying drawing after coating photoresist 108 is as shown in Figs. 4a and 4b, and wherein Fig. 4 a show viewing area, and Fig. 4 b show peripheral integrated circuit region；
Step 32, being exposed by half-exposure mask plate, the position of described switching via does not expose, the position half-exposure of described pixel electrode, all the other positions expose entirely；
Step 33, form connecting line in described not exposure area, formed in described half-exposure region and have the metallic reflector of pixel electrode function and reflection function concurrently, be sequentially etched the described connecting line layer film of removal and described metallic reflection layer film in described full exposure area.
In step 33, described full exposure area shows not in the drawings.After half-exposure mask plate exposure imaging, the photoresist of described full exposure area all can be removed in developing procedure, and a part removed by the photoresist in described half-exposure region in developing procedure, and its thickness is thinning.Specifically, the execution process of step 33 includes:
Step 331, in described full exposure area, be sequentially etched removal described connecting line layer film and described metallic reflection layer film；It is noted that the figure obtained after having etched in this step does not show.
Step 332, carry out photoresist ashing process and remove the photoresist in described half-exposure region, and etch the described connecting line layer film of removal, formed and have the metallic reflector of pixel electrode function and reflection function concurrently；
After carrying out photoresist ashing process, the photoresist in half-exposure region is removed, and as shown in Figure 5 a, the photoresist of full exposure area is thinning for its structure, and its structure is as shown in Figure 5 b.Afterwards, double exposure area performs etching, and removes connecting line layer film 107, only retains reflective metals layer film 106, and thus constitutes the metallic reflector 106 having pixel electrode function and reflection function concurrently, and its structure is as shown in Figure 6 a.
Step 333, by the photoresist lift off of described not exposure area, described not exposure area formed connecting line.As shown in Figure 6 b, this connecting line is formed with the connecting line layer 107 being positioned at upper strata the structure of connecting line by the metallic reflector 106 being positioned at lower floor, and metallic reflector 106 directly contacts with connecting line layer 107.
Preparation method for above-mentioned total reflection array base palte, when carrying out half-exposure patterning processes in step 3 to form the metallic reflector being provided simultaneously with pixel electrode function and reflection function, even if etching liquid is permeated by connecting line layer film, also can by metallic reflector film barrier, switching via will not be corroded, after carrying out half-exposure, the photoresist transferred above via is not also removed even, therefore also has photoresist to stop, switching via will not be corroded more；Secondly, after using half-exposure technique, the connecting line of pixel electrode and switching via is formed in a patterning processes, decreases the use of a mask plate, reduces cost.
nullExcept above-mentioned preparation method，The embodiment of the present invention additionally provides a kind of total reflection array base palte，With reference to shown in Fig. 6 a and 6b，This array base palte includes bearing basement 101，Bearing basement 101 is formed grid line 102 and data wire 104 that spatial vertical is intersected，Grid line 102 and data wire 104 limit pixel region，Thin film transistor (TFT) and pixel electrode it is provided with in described pixel region，The grid of described thin film transistor (TFT) is connected with described grid line、Source electrode is connected with described data wire、Drain electrode is connected with described pixel electrode，Wherein，Described array base palte includes viewing area and peripheral peripheral integrated circuit region，As shown in Figure 6 a，Described in described viewing area, pixel electrode is made up of the metallic reflector 106 with reflection function，As shown in Figure 6 b，Described peripheral integrated circuit region is provided with switching via，The connecting line connecting described switching via is made up of the metallic reflector 106 being positioned at lower floor and the connecting line layer 107 being positioned at upper strata.
As shown in Figure 6 b, in described peripheral integrated circuit region, the metallic reflector 106 constituting switching via connecting line directly contacts with connecting line layer 107, not being patterned technique after so having deposited metallic reflection layer film 106 can Direct precipitation connecting line layer film, decrease processing step, reduce cost.
Wherein, metallic reflector 106 is made up of metal material, and connecting line layer 107 is made up of indium tin oxide material.The material of metallic reflector has the ability of extraneous ray of reflecting, it is not necessary to use backlight, and quality is fine and close, it is not easy to make etching liquid penetrate into.Such as, the material of metallic reflector can select metal Mo.
Based on the embodiment of above-mentioned total reflection array base palte, the embodiment of the present invention also provides for a kind of display device, including the total reflection array base palte described in above-described embodiment.
In the description of above-mentioned embodiment, specific features, structure, material or feature can combine in an appropriate manner in any one or more embodiments or example.
The above; being only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; change can be readily occurred in or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.
Claims (9)
1. the preparation method being totally reflected array base palte, it is characterised in that described array base palte includes viewing area and peripheral integrated circuit region, and described preparation method includes:
Step 1, in bearing basement, form grid line and grid, gate insulation layer, active layer, data wire and source, drain electrode, passivation layer and passivation layer via hole；
Step 2, in described bearing basement metal reflective layer thin film, and on described metallic reflection layer film deposit connecting line layer film；
Step 3, it is patterned technique by half-exposure mask plate, having the metallic reflector of pixel electrode function and reflection function concurrently in the formation of described viewing area, form connecting line in described peripheral integrated circuit region, described connecting line is made up of metallic reflector and connecting line layer.
2. the preparation method of total reflection array base palte according to claim 1, it is characterized in that, described passivation layer via hole include in described viewing area connect pixel electrode and thin film transistor (TFT) drain electrode via and described peripheral integrated circuit region in switching via.
3. the preparation method of total reflection array base palte according to claim 2, it is characterised in that described step 3 includes:
Step 31, there is in the bearing basement of metallic reflection layer film and connecting line layer film coating photoresist in deposition；
Step 32, being exposed by half-exposure mask plate, the position of described switching via does not expose, the position half-exposure of described pixel electrode, all the other positions expose entirely；
Step 33, form connecting line in described not exposure area, formed in described half-exposure region and have the metallic reflector of pixel electrode function and reflection function concurrently, be sequentially etched the described connecting line layer film of removal and described metallic reflection layer film in described full exposure area.
4. the preparation method of total reflection array base palte according to claim 3, it is characterised in that described step 33 includes:
Step 331, in described full exposure area, be sequentially etched removal described connecting line layer film and described metallic reflection layer film；
Step 332, carry out photoresist ashing process and remove the photoresist in described half-exposure region, and etch the described connecting line layer film of removal, formed and have the metallic reflector of pixel electrode function and reflection function concurrently；
Step 333, by the photoresist lift off of described not exposure area, described not exposure area formed connecting line.
5. a total reflection array base palte, including bearing basement, described bearing basement is formed grid line and data wire that spatial vertical is intersected, described grid line and data wire limit pixel region, thin film transistor (TFT) and pixel electrode it is provided with in described pixel region, the grid of described thin film transistor (TFT) is connected with described grid line, source electrode is connected with described data wire, drain electrode is connected with described pixel electrode, it is characterized in that, described array base palte includes viewing area and peripheral integrated circuit region, described in described viewing area, pixel electrode is made up of the metallic reflector with reflection function, described peripheral integrated circuit region is provided with switching via, the connecting line connecting described switching via is made up of metallic reflector and connecting line layer.
6. total reflection array base palte according to claim 5, it is characterised in that in described peripheral integrated circuit region, described metallic reflector directly contacts with described connecting line layer.
7. the total reflection array base palte according to claim 5 or 6, it is characterised in that described metallic reflector is made up of metal material, described connecting line layer is made up of indium tin oxide material.
8. total reflection array base palte according to claim 7, it is characterised in that described metal material is Mo.
9. a display device, including the total reflection array base palte as described in any one of claim 5-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610364884.8A CN105789121A (en) | 2016-05-27 | 2016-05-27 | Total reflection array substrate and preparation method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610364884.8A CN105789121A (en) | 2016-05-27 | 2016-05-27 | Total reflection array substrate and preparation method thereof and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105789121A true CN105789121A (en) | 2016-07-20 |
Family
ID=56375341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610364884.8A Pending CN105789121A (en) | 2016-05-27 | 2016-05-27 | Total reflection array substrate and preparation method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105789121A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298806A (en) * | 2016-09-06 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of total reflection array base palte and preparation method thereof and display device |
| CN107731854A (en) * | 2017-09-28 | 2018-02-23 | 京东方科技集团股份有限公司 | Preparation method and array base palte, the display device of a kind of array base palte |
| US20220317532A1 (en) * | 2021-04-01 | 2022-10-06 | Sharp Kabushiki Kaisha | Liquid crystal display device and method for manufacturing same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353324A (en) * | 2000-11-11 | 2002-06-12 | 三星电子株式会社 | Reflective liquid crystal display apparatus and its manufacturing method |
| CN1410807A (en) * | 2001-09-28 | 2003-04-16 | 株式会社日立制作所 | Liquid crystal display element and display device using same |
| CN1512830A (en) * | 2002-12-28 | 2004-07-14 | Lg.������Lcd��ʽ���� | Double side plate type organic electroluminescent device and its producing method |
| CN102279490A (en) * | 2011-04-09 | 2011-12-14 | 福州华映视讯有限公司 | Reflective display and thin-film transistor array substrate thereof |
| CN104375348A (en) * | 2014-12-10 | 2015-02-25 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method and total-reflection liquid crystal display |
| CN104538356A (en) * | 2015-01-07 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN105242468A (en) * | 2015-10-27 | 2016-01-13 | 深圳市华星光电技术有限公司 | Liquid crystal display panel reducing parasitic capacitances and manufacturing method thereof |
-
2016
- 2016-05-27 CN CN201610364884.8A patent/CN105789121A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1353324A (en) * | 2000-11-11 | 2002-06-12 | 三星电子株式会社 | Reflective liquid crystal display apparatus and its manufacturing method |
| CN1410807A (en) * | 2001-09-28 | 2003-04-16 | 株式会社日立制作所 | Liquid crystal display element and display device using same |
| CN1512830A (en) * | 2002-12-28 | 2004-07-14 | Lg.������Lcd��ʽ���� | Double side plate type organic electroluminescent device and its producing method |
| CN102279490A (en) * | 2011-04-09 | 2011-12-14 | 福州华映视讯有限公司 | Reflective display and thin-film transistor array substrate thereof |
| CN104375348A (en) * | 2014-12-10 | 2015-02-25 | 京东方科技集团股份有限公司 | Array substrate, array substrate manufacturing method and total-reflection liquid crystal display |
| CN104538356A (en) * | 2015-01-07 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN105242468A (en) * | 2015-10-27 | 2016-01-13 | 深圳市华星光电技术有限公司 | Liquid crystal display panel reducing parasitic capacitances and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298806A (en) * | 2016-09-06 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of total reflection array base palte and preparation method thereof and display device |
| CN106298806B (en) * | 2016-09-06 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of total reflection array substrate and preparation method thereof and display device |
| CN107731854A (en) * | 2017-09-28 | 2018-02-23 | 京东方科技集团股份有限公司 | Preparation method and array base palte, the display device of a kind of array base palte |
| CN107731854B (en) * | 2017-09-28 | 2020-05-05 | 京东方科技集团股份有限公司 | Preparation method of array substrate, array substrate and display device |
| US20220317532A1 (en) * | 2021-04-01 | 2022-10-06 | Sharp Kabushiki Kaisha | Liquid crystal display device and method for manufacturing same |
| US11762252B2 (en) * | 2021-04-01 | 2023-09-19 | Sharp Kabushiki Kaisha | Liquid crystal display device and method for manufacturing same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100447645C (en) | Thin film transistor substrate of horizontal electric field type liquid crystal display device and fabricating method thereof | |
| US8633066B2 (en) | Thin film transistor with reduced edge slope angle, array substrate and having the thin film transistor and manufacturing method thereof | |
| TWI528072B (en) | Liquid crystal display device and method for fabricating the same | |
| US7999258B2 (en) | Display substrate and method of manufacturing the same | |
| CN102881688B (en) | Array substrate, display panel and array substrate manufacturing method | |
| CN101685229B (en) | Method for manufacturing array substrate of liquid crystal display device | |
| CN100416364C (en) | Array substrate for in-plane switching liquid crystal display device and method of fabricating the same | |
| CN101211084A (en) | Liquid crystal display panel and manufacturing method of the same | |
| CN104952792B (en) | The preparation method of TFT substrate structure | |
| CN101089711A (en) | Liquid crystal display device and a manufacturing method thereof | |
| CN101677058B (en) | Manufacturing method of film construction body | |
| CN105158966A (en) | Curved-surface display panel, manufacturing method thereof, and curved-surface display device | |
| CN103107133B (en) | Array substrate, manufacturing method thereof and displaying device | |
| CN105070727A (en) | Thin film transistor array substrate, manufacturing method thereof and display device | |
| CN101191967B (en) | Liquid crystal display device array substrate and its manufacture method | |
| US6717631B2 (en) | Array substrate for use in LCD device | |
| US20050094079A1 (en) | Thin film transistor substrate using a horizontal electric field type liquid crystal display device and fabricating method thereof | |
| JP2008026435A (en) | Transflective liquid crystal display and its manufacturing method | |
| CN100529926C (en) | Thin film transistor substrate for horizontal electric field LCD device and its manufacture | |
| WO2015180357A1 (en) | Array substrate and manufacturing method therefor, and display device | |
| CN104965324B (en) | The manufacturing method of liquid crystal display device | |
| CN105789121A (en) | Total reflection array substrate and preparation method thereof and display device | |
| CN106024705B (en) | The production method of TFT substrate | |
| CN108346622A (en) | Array substrate and preparation method thereof, display panel | |
| EP3644120A1 (en) | Photomask structure and method for manufacturing array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160720 |
|
| RJ01 | Rejection of invention patent application after publication |