CN105762191A - Semiconductor device and manufacture method thereof - Google Patents

Abstract

The invention provides a semiconductor device. The semiconductor device includes a plurality of fin structures which vertically protrude out form a substrate and extend along a first direction, source and drain regions which are formed at two ends of each fin structure along the first direction, channel regions which contain a plurality of nanowires and are connected between the source and drain regions along the first direction, a gate stack structure which extends along a second direction and surrounds each nanowire, and a filling layer which is located between the bottoms of the plurality of nanowires and the substrate. According to the semiconductor device and the manufacture method thereof, the channels of nanowires are formed between the fin-shaped source and drain regions, and therefore, process cost can be decreased, process complexity can be reduced, and grid control ability and device density can be effectively improved.

Description

Semiconductor device and manufacture method thereof

Technical field

The present invention relates to technical field of semiconductors, more particularly to a kind of FinFET (FinFET) with nanowire channel and manufacture method thereof.

Background technology

It is increasingly miniaturized the challenge brought in order to what tackle semiconductor device, have been proposed for multiple high performance device, particularly in current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, and this structure enhances grid control ability, inhibits electric leakage and short-channel effect.

Such as, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOIMOSFET, short-channel effect (SCE) and leakage can be suppressed to cause induced barrier and to reduce (DIBL) effect, there is less junction capacity, it is capable of raceway groove gently to adulterate, adjusting threshold voltage can be carried out by arranging the work function of metal gates, it is possible to obtain the driving electric current of about 2 times, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, grid encloses channel region end face and two sides, and grid control ability is higher.Further, loopful has more advantage around nano wire multi-gate device.But, in the three-dimensional multi-gate device manufacturing processes such as FinFET, need to adopt the techniques such as CMP to planarize until exposing interlayer dielectric layer (ILD) by the grid material that such as rear grid technique is formed, add process complexity and exist because CMP own limitations brings the possibility of saucerization, reducing reliability.Additionally, FinFET technique often adopts Twi-lithography technique to form PTSL injection, length consuming time and the problem that there is photoetching process alignment precision.These limitations make traditional FinFET cannot obtain the short-channel effect of intended higher grid-control ability, reduction at smaller szie (such as below 10nm).

On the other hand, another technology branch of reply miniaturization challenge is nanowire technique, generally arranges formation silicon nanowire or CNT, the extremely narrow channel region of formation device by etching or be coated with on the liner (pad) of source-drain area.This nano-wire devices can effectively strengthen carrier mobility, and allows possible ballistic transport, greatly improves device performance.But, nano wire technique needs to form extra pad and supports, and precision and mechanical performance control for device etching technics require high.Additionally, in order to strengthen grid-control ability, the metal gates that the grid above nanowire channel manufactures often by rear grid technique, complex process is with high costs.Further, source-drain area is for support pad structure, and often in plan view, floor space is relatively big, have impact on device integration.

Summary of the invention

From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, it is proposed to a kind of save process costs, reduce process complexity and be effectively improved nano wire FinFET and the manufacture method thereof of grid-control ability and device density.

For this, the invention provides a kind of method, semi-conductor device manufacturing method, including: on substrate, form multiple first mask graphs extended in a first direction；Substrate is formed the false grid stacked structure extended in a second direction, crosses over multiple first mask graph；With multiple first mask graphs and false grid stacked structure for mask, etched substrate, form multiple fin structure extended in a first direction, fin structure side in a second direction has the table top from substrate projection；Remove false grid stacked structure, form gate openings, expose the first mask graph；With the first mask graph for mask, etched substrate and table top, form the channel region that multiple nano wire is constituted；The fin structure of channel region both sides in the first direction is formed source-drain area；Forming the gate stack structure extended in a second direction, enclose channel region, wherein gate stack structure includes hafnium gate insulator and metal gates conductive layer.

Wherein, adopt side wall shifting process to form multiple first mask graph, specifically include: on substrate, form the multiple preparation figures extended in a first direction；Preparing figure and substrate are formed insulating dielectric materials layer；Anisotropic etching insulating dielectric materials layer, only leaves sidewall structure in preparation figure side；Etching is removed and is prepared figure, and the sidewall structure stayed constitutes multiple first mask graph.

Wherein, false grid stacked structure includes false grid insulating barrier, false grid conductive layer and false grid cap rock.

Wherein, false grid cap rock is single layer structure and/or ONO multiple structure.

Wherein, grid curb wall is formed in false grid stacked structure both sides in the first direction after being formed after false grid stacked structure or forming fin structure.

Wherein, after formation fin structure, farther include before removal false grid stacked structure: on device, form the first interlayer dielectric layer；Planarize the first interlayer dielectric layer until exposing false grid stacked structure.

Wherein, the step forming channel region farther includes: adopt isotropic etching technique, etched substrate and table top, forms multiple lateral concave in a second direction；Adopt oxidation technology to form oxide, increase lateral concave；Wet etching removes oxide, discharges multiple nano wire.Wherein, oxidation technology is thermal oxide.

Wherein, farther include after forming the channel region that nano wire is constituted, in gate openings and around nano wire, form packed layer.Wherein, packed layer and the etching selection ratio of the material of surrounding are more than 5:1.

Wherein, farther include after forming the channel region that nano wire is constituted, the fin structure of channel region both sides in the first direction is formed source-drain area.Wherein, source-drain area includes heavy-doped source drain region and/or lightly-doped source drain extension region and/or Yun Zhuan source and drain doping district.

Wherein, further include at before removing false grid stacked structure and device is formed the first interlayer dielectric layer and planarizes the first interlayer dielectric layer until exposing false grid stacked structure, and farther include back before forming source-drain area to carve the first interlayer dielectric layer, part exposes the sidewall of fin structure, and the first interlayer dielectric layer stayed constitutes device isolation region.

Wherein, the step removing false grid stacked structure farther includes: form interlayer dielectric layer on device；Planarization interlayer dielectric layer is until exposing false grid stacked structure；It is sequentially etched removal false grid stacked structure, until exposing the first mask graph and table top.

Wherein, farther include after forming channel region, form the gate stack structure extended in a second direction, enclose channel region.Wherein, gate stack structure includes the gate insulator of hafnium and the grid conducting layer of metal material.

Wherein, substrate is the extension lamination alternately supporting substrate at monocrystal silicon or SOI, and the material of extension lamination is selected from the arbitrarily multiple of Si, SiGe, Si:C and combination thereof.

Wherein, the step forming channel region farther includes, and adjusts etch process parameters and makes the etch rate between adjacent two extension lamination different, and selective etch is removed a kind of and left another kind.

The invention also discloses a kind of semiconductor device, including: multiple fin structures, vertical projections on substrate, extend in a first direction；Source-drain area, is formed at the two ends in the first direction of each fin structure；Channel region, comprises multiple nano wire, is connected between source-drain area in the first direction；Gate stack structure, extends in a second direction, encloses each nano wire.

Farther include, packed layer, bottom multiple nano wires and between substrate.

Wherein, the material in nanowire channel district is selected from the arbitrarily multiple of Si, SiGe, Si:C and combination thereof.

According to semiconductor device and the manufacture method thereof of the present invention, between fin-like source-drain area, form the raceway groove of nano wire, save process costs, reduce process complexity, and be effectively improved grid-control ability and device density.

Accompanying drawing explanation

Technical scheme is described in detail referring to accompanying drawing, wherein:

Fig. 1 to Figure 10 is the schematic diagram according to each step of method, semi-conductor device manufacturing method of the present invention.

Detailed description of the invention

Referring to accompanying drawing the feature and the technique effect thereof that describe technical solution of the present invention in conjunction with schematic embodiment in detail, disclose saving process costs, reduce process complexity and be effectively improved nano wire FinFET and the manufacture method thereof of grid-control ability and device density.It is pointed out that similar accompanying drawing labelling represents similar structure, term " first " use herein, " second ", " on ", D score etc., etching etc. can be used for modifying various device architecture or manufacturing process.These modifications do not imply that modified device architecture or the space of manufacturing process, order or hierarchical relationship unless stated otherwise.In the following description, regardless of whether display is in different embodiments, similar parts adopt same or similar accompanying drawing labelling to represent.In various figures, for the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.

Describe hereinafter the many specific details of the present invention, for instance the structure of device, material, size, process technique and technology, in order to be more clearly understood that the present invention.But just as the skilled person will understand, it is possible to do not realize the present invention according to these specific details.Unless particularly pointed out hereinafter, the various piece in semiconductor device can be made up of material well known to those skilled in the art, or can adopt the material with similar functions of exploitation in the future.

According to one embodiment of present invention, referring to figs. 1 through 10, the methods that manufacture semiconductor device being described, wherein the top of each figure is plan view, and bottom is the sectional view of AA line in the first direction or the sectional view of BB line in a second direction.

As it is shown in figure 1, form the first mask 2 extended in a first direction on substrate 1.Substrate 1 can be various forms of suitable substrate, such as body Semiconductor substrate such as Si, Ge etc. and compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb etc., semiconductor-on-insulator substrate (SOI) etc..

In a preferred embodiment of the invention, substrate 1 is monocrystal silicon or SOI substrate.In another preferred embodiment of the present invention, the extension alternative stacked that substrate 1 is the support substrate of monocrystal silicon or SOI (can be horizontal cross lamination, it can also be vertical longitudinal lamination, or level and lateral stack be mixed to form array), epitaxial layer material can be selected from the arbitrarily multiple of Si, SiGe, Si:C and combination thereof, for instance SiGe/Si alternating layer, SiGe/Si:C alternating layer, SiGe/Si:C alternating layer, SiGe/Si/Si:C alternating layer etc..Each epitaxy layer thickness such as 1-50nm preferably 1-20nm so that following channel region is nanowire channel.

For convenience of description, it is described for example with thick body (bulk, for instance body Si) substrate and silicon based material (such as SOI) below.Substrate 1 top surface is formed in the first direction the first mask 2 of the small size lines that (in Fig. 2 AA direction) extends.The material of the first mask 2 is such as the hard mask that the materials such as silicon nitride, silicon oxynitride, diamond like carbon amorphous carbon (DLC) are harder.Formation process can be on substrate 1 by above-mentioned insulating dielectric materials of process deposits such as LPCVD, PECVD, coating above it is exclusively used in the photoresist of beamwriter lithography or EUV lithography, adopt beamwriter lithography or the bargraphs (such as the only 0.5～1.5nm of width in a second direction) of the exposure of EUV lithography machine, development formation fine size photoresist, with photoetching offset plate figure for mask, anisotropic dry etch is not photo-etched the insulating dielectric materials of glue pattern covering and leaves undersized first mask 2 on substrate 1.Further, it is also possible to adopt side wall transfer techniques.nullSuch as in a preferred embodiment of the invention，First adopt photoetching technique (the such as UV photoetching of the large-size of routine、Immersion 193nm photoetching etc.，Usual characteristic size is at more than 20nm) form the preparation figure (not shown) of the relatively soft material matter such as the wider silicon oxide of size，Preparation graphic top surface and sidewall pass through PECVD、HDPCVD、MBE、ALD、The techniques such as sputtering form silicon nitride、Silicon oxynitride、The insulating dielectric materials that the materials such as diamond like carbon amorphous carbon (DLC) are harder，Its thickness is made to be only 0.5～1.5nm by controlling depositing operation，Then anisotropic etching is removed horizontal component and is only left sidewall structure in preparation figure side，Wet etching is removed and is prepared figure subsequently，The sidewall structure stayed constitutes the first mask 2 of small size lines as shown in Figure 1.In addition, photoetching/the etching technics that can also adopt routine forms the first mask graph, it is specifically included on substrate and forms layer of mask material, layer of mask material forms, by conventional exposure, developing process, the multiple photoetching offset plate figures extended in a first direction, forms multiple first mask graph with photoetching offset plate figure for mask etching layer of mask material.

As in figure 2 it is shown, form the false grid extended in a second direction stacking 3 on the first mask 2.After traditional FinFET technique is typically formed mask 2, direct etching substrate 1 forms fin; the application is entirely different with it; do not etch fin but Direct precipitation false grid stacking 3; this is conducive to protecting following nanowire channel district; the liner extra without source-drain area and by mechanical strength during etching of the temporary substrates Material reinforcement of channel region side, be conducive to the fine nano wire of formation of low cost, miniaturization.Specifically, sequentially form false grid dielectric layer 3A, false grid conductive layer 3B and false grid cap rock (3C/3D/3E) by techniques such as LPCVD, PECVD, HDPCVD, MBE, ALD, evaporation, sputterings, and anisotropic etching forms false grid stacked structure subsequently.Wherein, false grid dielectric layer 3A material is silicon oxide, thinner thickness, for instance only 0.8～2nm, for protecting substrate 1 top interface below, reduces interfacial state, prevents over etching.False grid conductive layer 3B material such as non-crystalline silicon, polysilicon, amorphous germanium, polycrystalline germanium, amorphous carbon etc., be mainly used in the pattern of control future gate opening and the Etch selectivity between raising and levels.In an embodiment of the invention, false grid conductive layer 3B thickness/height can be less, for instance only 40nm, and this is primarily to control subsequent gate opening depth-to-width ratio to strengthen metal gates filling rate.False grid cap rock is for protecting false grid conductive layer 3B, and precise controlling etching process is to improve the perpendicularity of sidewall to form required fine lines.In a preferred embodiment of the invention, false grid cap rock is ONO structure, namely includes the 3rd cap rock 3E of the first cover 3C of oxide, the second cap rock 3D of nitride and oxide from bottom to up successively.False grid stacked structure 3 extends in a second direction, vertically crosses the first mask 2 that first direction extends, and the width in the first direction of stacked structure 3 determines the channel region length of subsequent device, for instance only 1～10nm.Now, optional, it is possible to form grid curb wall (layer 4 in Fig. 3) in false grid stacked structure 3 both sides, or as it is shown on figure 3, etching forms grid curb wall after forming fin structure again.

As it is shown on figure 3, etching forms fin structure.With the first mask 2 and false grid stacked structure 3 for mask, adopt anisotropic etch process etched substrate 1, stay multiple parallel fin structure 1F extended in a first direction for the source-drain area of future device on substrate 1.Anisotropic etch process can be the dry plasma etch or the reactive ion etching (RIE) that adopt carbon fluorine base gas to be main etching gas, it is also possible to is adopt TMAH, KOH etc. for the wet etching of Si material corrosive liquid.It should be noted that; due to false grid stacked structure covering protection; substrate 1 below structure 3 is not etched but is directly connected to the backing material not being etched equally below the first mask 2 from second direction side; it is thus provided that the temporary support for following nano-channel district 1C; without the extra liner of source-drain area to strengthen the mechanical strength during etching, be conducive to the fine nano wire of formation of low cost, miniaturization.Hereafter, optional, remove the first mask 2 (although not showing that this step in figure) above fin 1F.Hereafter, grid curb wall 4 is formed in false grid stacked structure 3 both sides in the first direction.Such as defined the dielectrics such as silicon nitride, silicon oxynitride, DLC by techniques such as PECVD, HDPCVD and anisotropic etching forms grid curb wall 4.

As shown in Figure 4, whole device forms the first interlayer dielectric layer (ILD) 5.Such as formed the ILD5 of low-k materials by the technique such as spin coating, spraying, silk screen printing, CVD, low-k materials includes but not limited to organic low-k materials (such as containing the organic polymer of aryl or many rings), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (such as two silicon three oxygen alkane (SSQ) hole, Quito low-k materials, porous silica, porous SiOCH, mix C silicon dioxide, mix F porous amorphous carbon, porous diamond, porous organic polymer).ILD5 completely covers false grid stacked structure 3, grid curb wall 4, fin structure 1F, the isostructural end face of substrate 1 and sidewall.

As it is shown in figure 5, planarization ILD5 is until exposing false grid conductive layer.For example with CMP or return carve (etch-back) technique successively an ILD5, false grid cap rock 3E/3D/3C are carried out planarization process, until expose false grid conductive layer 3B.It should be noted that the table top that substrate 1 material now still remaining bulk below false grid stacked structure 3 is constituted is protruding, connect with side in the middle part of fin structure 1F, it is provided that favourable mechanical support.

As shown in Figure 6, remove false grid stacked structure 3, expose the first mask 2 being disposed below.Material for false grid conductive layer 3B and false grid dielectric layer 3A, select etching technics, ILD5 with side wall 4 define gate openings, exposes the first mask 2 extending in a first direction (being distributed between the fin structure 1F at source-drain area place on 1 material table top 1C at the bottom of middle gasket).Layer 3B for non-crystalline silicon, polysilicon material, it is possible to select TMAH wet etching；Layer 3B for amorphous carbon material, it is possible to select oxygen plasma dry etching；For other materials such as germanium, it is possible to select the combination wet etching of strong acid and strong oxidizer；Layer 3A for silicon oxide material, it is possible to select dHF (dilution HF acid), dBOE (dilution slow release etching agent, NH₄F and HF mixed aqueous solution) etc..Subsequently, with the first mask 2 of exposure for mask, the mesa structure 1C of substrate 1 below is etched formation side-facing depressions.Preferably, it is preferable that perform periodic isotropic etching technics and optional side passivation technique, for instance adopt SF₆、NF₃The etching gas being main carries out dry plasma etch, RIE; and after first side-facing depressions has etched; the protective layer that the polymer such as deposition CF base are constituted; or adopt deposition or oxidation technology to form the protective layer of oxide; so that protecting the recessed side walls formed in follow-up etching process; then ultimately form the multiple cylinder stacked structures shown in Fig. 6 bottom, there is between neighbouring cylinder the laterally recessed or side-facing depressions of BB in a second direction.Pole section can be square, rectangle, circle, oval etc. according to etch process parameters difference.

As it is shown in fig. 7, released the channel region 1C of nano thread structure by rounding process.Inject owing to now not carrying out the injection of source drain extension district and source and drain, high-temperature thermal oxidation (pass into oxygen and/or steam in such as oxidation furnace and obtain the oxide of desired thickness at 800 to 1300 degrees Celsius of lower heat treatment 10s～10min) therefore can be used on multiple cylinder stacked structure bases, lateral concave shown in Fig. 6 to be increased further, junction is thinning further between cylinder.In addition chemical oxidation can also be passed through, chemical oxidizing agent such as nitric acid, hydrogen peroxide or wrap deionized water ozoniferous.Eliminate oxide by wet etching (such as dHF, dBOE etc.) subsequently and obtain the channel region 1C (for space 1A between upper and lower nano wire) that separates stacked up and down multiple nano thread structures.Further, space 1A deposited in gate openings and between nano wire packed layer 6, the conformability such as technique such as HDPCVD, MOCVD, MBE, ALD, the insulating dielectric materials that filling capacity is good, such as having the material of bigger etching selection ratio (such as in dHF, dBOE etching selection ratio more than 5:1 preferred 10:1) with the ILD5 of low k material when the ILD5 of low k is silicon oxide base material matter, packed layer 6 is the materials such as silicon nitride.Optional, it is possible to before deposition packed layer 6, etching removes the first mask 2.

It should be noted that, above-mentioned Fig. 3 to Fig. 7 have employed monocrystal silicon Si or SOI substrate structure for describing the process of a preferred embodiment of the invention, (can be the thermal oxide in conjunction with mask or chemical oxidation for example with oxidation technology, can also be inject O formation oxide of annealing) form isolation material and select HF base corrosive liquid selective removal, it is consequently formed nanowire channel district.But, when another preferred embodiment of the present invention adopts extension lamination as substrate 1, then anisotropic etch process can be made different for different materials etch rate by adjustment technological parameter, such as increase the etch rate for a certain epitaxial layer and reduce for alternative etch rate, selective removal is a kind of and retains the epitaxial layer of another kind of nanoscale, thus forms multiple nano wires alternately in above-mentioned extension alternating layer.

Preferably, after etching forms nanowire channel district, but interlayer dielectric layer (not shown), then passes through etching and removes part interlayer dielectric layer and expose Nano-structure have part inter-level dielectric one to cover on substrate (namely lower zone of Nano-structure) thus forming substrate isolation area (not shown) at channel region.

As shown in Figure 8, return and carve an ILD5, leave the insulation isolation structure between fin structure 1F on substrate 1.Such as when an ILD5 adopts silica based materials, HF base etching liquid wet etching or the adjustment fluorine-based etching gas proportioning of carbon is adopted to make it accelerate etching for silica based materials, anisotropically to carving ILD5 next time, so that false grid stacked structure 3 is completely exposed, part exposes fin structure 1F.The ILD5 stayed define in plan view, enclose fin structure 1F side periphery be dielectrically separated from 5, sometimes referred to as STI5.Hereafter, further, the fin structure 1F of grid curb wall 4 both sides (in the first direction) forms source-drain area.Such as, injected by vertical and/or angle-tilt ion and/or original position doping in the process of epitaxial growth lifting source drain region, in grid curb wall 4 both sides, the fin structure 1F that is distributed in the first direction, define source region 1S and drain region 1D.Although figure illustrate only the source-drain area of single structure, but angle-tilt ion can essentially be passed through and inject formation lightly-doped source drain region (LDD structure) and/or Yun Zhuan source and drain doping district (Halo structure) with further adjusting means performance.

Preferably, if substrate is body Si, then formed after being dielectrically separated from 5, adopt angle-tilt ion to be infused between fin 1F and substrate 1 interface and form break-through barrier layer (PTSL, not shown).This break-through barrier layer can comprise the adulterant contrary with source-drain area conduction type, to form back-biased pn-junction between 1 at the bottom of future channel district 1C and back lining thus stoping substrate break-through.Additionally, PTSL layer can also be ion implanting N, O after and anneal formed dielectric isolation layer, better to realize for being dielectrically separated between channel region 1C and substrate 1.If substrate is SOI, then not necessarily form PTSL.

If substrate is the overlapping substrate of the epitaxial layer on body silicon, form the method on break-through barrier layer except identical with body silicon, all right: by not formed before extension lamination by injecting formation break-through barrier layer or injecting formation break-through barrier layer (or when first epitaxial layer of extension by original position doping formation break-through barrier layer) after first epitaxial layer of extension, inject and after the latter is epitaxially formed break-through barrier layer, carry out periodically epitaxial multilayer epitaxial layer again, on this substrate, then form multiple first mask graphs extended in a first direction again.Remove false grid can etch into inside body silicon layer when performing etching nano wire carrying out opening false grid, it is also possible to etch into the upper surface near zone of ground floor epitaxial layer.Formed in etching and need deposition the first interlayer dielectric layer behind nanowire channel district, then pass through etching and remove part interlayer dielectric layer and expose Nano-structure but have part inter-level dielectric one to cover on substrate (namely lower zone of Nano-structure) thus forming isolation area at channel region.Then follow-up HKMG technique is carried out again.As it is shown in figure 9, form the second interlayer dielectric layer (ILD) 7 on whole device.Adopt the technique similar and/or identical for ILD5 with the oneth and material, form ILD7, completely covers the source-drain area 1S/1D formed in grid curb wall 4, packed layer 6, fin 1F and STI5 around.Preferably, adopt CMP, return the technique planarization ILD7 such as quarter, until exposing packed layer 6.

As shown in Figure 10, remove and be partially filled with layer 6, expose the channel region 1C of nano wire.Packed layer 6 for silicon nitride material, it is possible to adopt hot phosphoric acid corrosion.Preferably, packed layer 6 only retains a undermost part to cover silicon substrate 1, in order to protection substrate 1 boundary defect on surface when follow-up high-g value deposits will not increase.In other words, remaining packed layer 6, bottom the nano wire of multiple nano wire bottommosts and between substrate.Hereafter, grid technique after can adopting, such as by the method such as HDPCVD, MBE, ALD, around channel region 1C, (such as fully wrapped around nanostructure channel district 1C) forms the gate insulator (not shown) of high-g value, its thinner thickness such as only 0.5～2nm.Hafnium is that dielectric constant is more than SiO₂Suitable material constitute, for instance the one of ZrO2, ZrON, ZrSiON, HfZrO, HfZrON, HfON, HfO2, HfAlO, HfAlON, HfSiO, HfSiON, HfLaO, HfLaON and combination in any thereof can be chosen from.Subsequently, by technique grid conducting layers of filler metal material around the gate insulator of high-g value such as MOCVD, MBE, ALD, evaporation, sputterings, it is preferable that include the work function regulating course being selected from TiN, TaN, MoN, WN, TaC and TaCN.Preferably, adopt conformal doping (conformaldoping) implanted dopant in work function regulating course, negative adulterant is injected in work function regulating course for N-type FinFET, the one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb, Er and Tb can be chosen from for the negative adulterant of metal gate；Positive adulterant is injected in work function regulating course for P type FinFET, the one of In, B, BF2, Ru, W, Mo, Al, Ga, Pt can be chosen from for the positive adulterant of metal gate.Preferably, high-K gate dielectric deposition after annealing (postdepositionannealing) can also be included between high-K gate dielectric and formation work function regulating course being formed, to improve the quality of high-K gate dielectric, this is conducive to the work function regulating course subsequently formed to obtain uniform thickness.Preferably, by above-mentioned known depositing operation, the surface of semiconductor structure forms resistance adjustment layer (not shown).Carry out chemically mechanical polishing (CMP) using resistance adjustment layer as stop-layer, to remove the part that the second Metal gate layer is positioned at outside gate openings, and only retain the part being positioned at gate openings (as shown in Figure 10 between grid curb wall 4).

Therefore, according to the semiconductor device that the present invention obtains, including: multiple fin structures, vertical projections on substrate, extend in a first direction；Source-drain area, is formed at the two ends in the first direction of each fin structure；Comprise the channel region of multiple nano wire, be connected between source-drain area in the first direction；Gate stack structure, including gate insulator and grid conducting layer, extends (being perpendicular to first direction) in a second direction, encloses each nano wire.Wherein farther include packed layer, bottom the nano wire of multiple nano wire bottommosts and between substrate.

The all details manufacturing semiconductor device are not described hereinbefore, for instance the formation of source/drain contact, additional interlevel dielectric layer and conductive channel.Those skilled in the art knows the standard CMOS process forming above-mentioned part and how to be applied in the semiconductor device of above-described embodiment, therefore this is no longer described in detail.

It should be noted that, being diagrammatically only by property of preferred embodiment shown in illustrations illustrates a kind of possible technological process, order between each step can be finely tuned, and in a second direction as long as forming before nanowire channel district 1C it in etching has the table top projection of substrate 1 material and supports to provide in BB both sides.

Above description is intended merely to and illustrates and describe the present invention, and is not intended to the exhaustive and restriction present invention.Therefore, the present invention is not limited to described embodiment.For those skilled in the art it will be apparent that modification or change, all within protection scope of the present invention.

According to semiconductor device and the manufacture method thereof of the present invention, between fin-like source-drain area, form the raceway groove of nano wire, save process costs, reduce process complexity, and be effectively improved grid-control ability and device density.

Although the present invention being described with reference to one or more exemplary embodiments, those skilled in the art could be aware that and device architecture or method flow are made without departing from the scope of the invention various suitable change and equivalents.Additionally, many amendments that can be adapted to particular condition or material can be made without deviating from the scope of the invention by disclosed instruction.Therefore, the purpose of the present invention does not lie in and is limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will include all embodiments fallen within the scope of the present invention.

Claims (20)

1. a method, semi-conductor device manufacturing method, including:

Substrate is formed multiple first mask graphs extended in a first direction；

Substrate is formed the false grid stacked structure extended in a second direction, crosses over multiple first mask graph；

With multiple first mask graphs and false grid stacked structure for mask, etched substrate, form multiple fin structure extended in a first direction, fin structure side in a second direction has the table top from substrate projection；

Remove false grid stacked structure, form gate openings, expose the first mask graph；

With the first mask graph for mask, etched substrate and table top, form the channel region that multiple nano wire is constituted.

2. method as claimed in claim 1, wherein, side wall shifting process is adopted to form multiple first mask graph, specifically include: on substrate, form the multiple preparation figures extended in a first direction, preparing figure and substrate are formed insulating dielectric materials layer, anisotropic etching insulating dielectric materials layer, only leave sidewall structure in preparation figure side, etching is removed and is prepared figure, and the sidewall structure stayed constitutes multiple first mask graph；

Or, conventional photoetching/etching technics is adopted to form the first mask graph, it is specifically included on substrate and forms layer of mask material, layer of mask material forms, by conventional exposure, developing process, the multiple photoetching offset plate figures extended in a first direction, forms multiple first mask graph with photoetching offset plate figure for mask etching layer of mask material.

3. method as claimed in claim 2, wherein, false grid stacked structure includes false grid insulating barrier, false grid conductive layer and false grid cap rock；Preferably, false grid cap rock is single layer structure and/or ONO multiple structure.

4. method as claimed in claim 1, wherein, is formed after false grid stacked structure or forms grid curb wall in false grid stacked structure both sides in the first direction after forming fin structure.

5. method as claimed in claim 1, wherein, after forming fin structure, farther includes before first time removal false grid stacked structure: form the first interlayer dielectric layer on device；Planarize the first interlayer dielectric layer until exposing false grid stacked structure.

6. method as claimed in claim 1, wherein, the step forming channel region farther includes: adopt periodic isotropic etching technique and optional side passivation technique, etched substrate and table top, forms multiple lateral concave in a second direction；Adopt oxidation technology to form oxide, increase lateral concave；Wet etching removes oxide, discharges multiple nano wire.

7. method as claimed in claim 6, wherein, oxidation technology is thermal oxide.

8. method as claimed in claim 1, wherein, farther including after forming the channel region that nano wire is constituted, deposition packed layer material CMP, until spilling side wall top and the first interlayer dielectric layer material of false grid storehouse, form packed layer in gate openings and around nano wire.

9. method as claimed in claim 8, wherein, the etching selection ratio of the material of packed layer and surrounding is more than 5:1.

10. method as claimed in claim 8, wherein, farther includes after forming packed layer, returns and carves the first interlayer dielectric layer, and part exposes the sidewall of fin structure, and the first interlayer dielectric layer stayed constitutes device isolation region.

11. such as the method for claim 10, formation farther includes formation source-drain electrode and break-through barrier layer behind device isolation region.

12. the method such as claim 11 forms the second interlayer dielectric layer after forming break-through barrier layer and source-drain electrode on device, planarize the second interlayer dielectric layer until exposing the packed layer within false grid, selective etch is removed and is partially filled with layer, exposes multiple nano thread structure.

13. such as the method for claim 12, wherein, remaining packed layer, between the bottom and substrate of multiple nano thread structures, forms the sealing coat of channel region.

14. such as the method for claim 11, wherein, source-drain area includes heavy-doped source drain region and/or lightly-doped source drain extension region and/or Yun Zhuan source and drain doping district.

15. method as claimed in claim 1, wherein, substrate is the extension lamination alternately that monocrystal silicon or SOI support substrate, it is preferable that the material of extension lamination is selected from the arbitrarily multiple of Si, SiGe, Si:C and combination thereof.

16. method as claimed in claim 1, wherein, farther include after forming channel region, form the gate stack structure extended in a second direction, enclose channel region.

17. such as the method for claim 15, wherein, the step forming channel region farther includes, adjusting etch process parameters and make the etch rate between adjacent two extension lamination different, selective etch is removed a kind of and is left another kind.

18. such as the method for claim 16, wherein, gate stack structure includes the gate insulator of hafnium and the grid conducting layer of metal material.

19. a semiconductor device, including:

Multiple fin structures, vertical projections on substrate, extend in a first direction；

Source-drain area, is formed at the two ends in the first direction of each fin structure；

Channel region, comprises multiple nano wire, is connected between source-drain area in the first direction；

Gate stack structure, extends in a second direction, encloses each nano wire.

20. such as the semiconductor device of claim 19, farther include, packed layer, bottom the nano wire of multiple nano wire bottommosts and between substrate.