CN105762122A - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN105762122A CN105762122A CN201610278166.9A CN201610278166A CN105762122A CN 105762122 A CN105762122 A CN 105762122A CN 201610278166 A CN201610278166 A CN 201610278166A CN 105762122 A CN105762122 A CN 105762122A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Disclosed in the invention is a chip packaging structure comprising a first chip, a second chip, an IC packaging shell, and a wafer made of a material having the same specification as that of the material employed by the first chip or the second chip. The first chip, the second chip, and the wafer are packaged into the IC packaging shell. A second reverse surface of the second chip is laminated on a first circuit surface of the first chip in a staggered mode. The wafer is adjacent to the first chip; and one surface, adjacent to the second chip, of the wafer and the first circuit surface of the first chip are located in a same plane and a second reverse surface that is not laminated on the first circuit surface is covered by the wafer. Because the second chip is stacked on the first chip in a staggered mode, the IC chip integration degree is improved effectively. Moreover, for a non-stacked area of the second chip and the first chip, the wafer made of the material having the same specification as that of the material employed by the first chip or the second chip is used for complete coverage and filling, so that working states of all function chips can be guaranteed effectively and thus a phenomenon that the performances are reduced or the power consumption is increased due to different materials can be avoided.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of chip-packaging structure.
Background technology
At present, along with miniaturization and portable consumer electronics product demand quickly increase, the encapsulation of IC chip is required also more and more higher.Generally, traditional functional chip (as: FLASH, SRAM or DRAM) it is all individually be packaged.And then system after having encapsulated, is formed again in the circuit board by production firm.But, adopt the line system integrated level that traditional chip-packaging structure is formed relatively low, and capacity of resisting disturbance be also relatively low.
Summary of the invention
Based on this, it is necessary to the line system integrated level formed for traditional chip-packaging structure and all relatively low problem of capacity of resisting disturbance, it is provided that a kind of chip-packaging structure.
For realizing a kind of chip-packaging structure that the object of the invention provides, including the first chip, the second chip, IC encapsulating shell and have and the wafer of described first chip or described second chip same size material；
Described first chip, described second chip and described wafer are all encapsulated in described IC encapsulating shell；
Described first chip has the first circuit face and first reverse side relative with described first circuit face；
Described second chip has second circuit face and second reverse side relative with described second circuit face；
Second reverse side dislocation of described second chip is stacked in the first circuit face of described first chip；
Described wafer is arranged with described first chip by chip；And
Described wafer be close to the first circuit face of the one side of described second chip and described first chip in the same plane in, and cover the second reverse side not being stacked in described first circuit face.
Wherein in an embodiment, the width of described second reverse side is less than or equal to the width of described first circuit face；
The side of the side of described wafer and described first chip matches.
Wherein in an embodiment, the thickness of described wafer is equal with the thickness of described first chip.
Wherein in an embodiment, the second reverse side of described second chip is fixing with the overlay area of the first circuit face of described first chip to be cohered.
Wherein in an embodiment, the side of described wafer is fixing with the side of described first chip coheres.
Wherein in an embodiment, described first circuit face is provided with multiple first pad；And
Multiple described first pads are respectively positioned on the non-stacking region of the first circuit face of described first chip and the second reverse side of described second chip；
Described second circuit face is provided with multiple second pad；
The base plate of described IC encapsulating shell is provided with multiple 3rd pad；
Each described first pad is all adjacent near described second pad or described 3rd pad electrical connection；
Wherein, multiple described first pads are distributed in the position, axis of described first chip or the periphery of the first circuit face of described first chip；
Multiple described second pads are distributed in the periphery in the second circuit face of described second chip；
Multiple described 3rd pads are distributed in the sole periphery of described IC encapsulating shell.
Wherein in an embodiment, multiple described first pads and multiple described second pad are all in single or double arrangement.
Wherein in an embodiment, multiple described 3rd pads are single arrangement.
Wherein in an embodiment, the arrangement of the arrangement of described first pad being distributed in described first circuit face side and described second pad being distributed on described second circuit face the same side matches.
Wherein in an embodiment, electrically connected by wire between multiple described first pads, multiple described second pad and multiple described 3rd pad.
Said chip encapsulating structure, by the second reverse side dislocation of the second chip is stacked in the first circuit face of the first chip, the first chip and the second chip is made to form the shape of stacked offset, in IC encapsulating shell, thus at least can encapsulate two panels chip, this is also just effectively increased the integrated level of IC, effectively control the plane space of wiring board simultaneously, and then reduce production cost.Meanwhile, also by arranging and the having and the wafer of the first chip or the second chip same size material of the first chip by chip, wafer it is close to the second reverse side that the second chip is not stacked and placed in the first circuit face by the one side of the second chip and covers.Namely, the wafer with the first chip or the second chip same size material is adopted to be covered by the second reverse side of unsettled the second chip outside the first circuit face of the first chip, thus being effectively ensured the first chip and the independence of the second chip each duty, improve capacity of resisting disturbance.Further, also effectively prevent the phenomenon causing the hydraulic performance decline power consumption of chip to rise because material is different.Finally efficiently solve line system integrated level that traditional chip-packaging structure formed and all relatively low problem of capacity of resisting disturbance.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment one of the chip-packaging structure of the present invention；
Fig. 2 is the left side view of the embodiment one of the chip-packaging structure of the present invention；
Fig. 3 is the top view of the embodiment one of the chip-packaging structure of the present invention；
Fig. 4 is the structural representation of the embodiment two of the chip-packaging structure of the present invention；
Fig. 5 is the top view of the embodiment three of the chip-packaging structure of the present invention；
Fig. 6 is the top view of the embodiment four of the chip-packaging structure of the present invention；
Fig. 7 is the top view of the embodiment five of the chip-packaging structure of the present invention；
Fig. 8 is the structural representation of the embodiment six of the chip-packaging structure of the present invention.
Detailed description of the invention
For making technical solution of the present invention clearly, below in conjunction with drawings and the specific embodiments, technical solution of the present invention is described in further detail.
First, should be noted that, the first chip mentioned in the present invention and the second chip refer respectively to the various functional chips in integrated circuit, as: FLASH (flash memory) chip, SRAM (SRAM) chip and DRAM (dynamic RAM) chip etc..No longer illustrate one by one herein.
Wherein, the first chip and the second chip are respectively provided with circuit face and the reverse side relative with circuit face.Circuit face refers to the one side being provided with corresponding circuit layout.It is to say, the first chip in the present invention has the first circuit face and first reverse side relative with the first circuit face.Accordingly, the second chip has second circuit face and second reverse side relative with second circuit face.
Referring to Fig. 1 to Fig. 3, as a specific embodiment of the chip-packaging structure 100 of the present invention, it includes first chip the 110, second chip 120, IC encapsulating shell 130 and wafer 140.Herein, it should be noted that wafer 140 has and the first chip 110 or the second chip 120 same size material.It is to say, the material of the wafer 140 in the chip-packaging structure 100 of the present invention should be identical with the material of the first chip 110 or the second chip 120.
Wherein, first chip the 110, second chip 120 and wafer 140 are all encapsulated in IC encapsulating shell 130.Further, the second reverse side dislocation of the first chip 110 is stacked in the first circuit face of the first chip 110.That is, part second reverse side of the first chip 110 is placed in the first circuit face of the first chip 110.So that the first chip 110 and the second chip 120 form the structure of stacked offset.Thus, it is possible to be encapsulated in same IC encapsulating shell 130 by the first chip 110 and the second chip 120 simultaneously, this also just effectively prevent a traditional functional chip and is individually encapsulated in the phenomenon in an IC encapsulating shell 130, thus being effectively increased the integrated level of IC.Further, after the chip-packaging structure 100 adopting the present invention carries out plural chip package, when the device after encapsulation is integrated into wiring board can also the plane space of effective control circuit board, it is to avoid the situation that the plane space of wiring board is excessive.
Simultaneously, it is also by setting up the wafer 140 being disposed adjacent with the first chip 110 in chip-packaging structure 100, and arrange wafer 140 be close to the first circuit face of the one side of the second chip 120 and the first chip 110 in the same plane in, the one side being close to the second chip 120 by wafer 140 is completely covered the second reverse side not being stacked in the first circuit face.Namely, unsettled for second reverse side of the second chip 120 part in the first circuit face of the first chip 110 is covered by the one side being close to the second chip 120 by wafer 140, make the first chip 110 and the second chip 120 can be completely independent work, ensure that the duty of the first chip 110 and the second chip 120, thus being effectively increased the capacity of resisting disturbance of the first chip 110 and the second chip 120.Meanwhile, hydraulic performance decline and the power consumption rising etc. of the IC chip cause encapsulation because material is different after are also reduced.
Wherein, should be noted that, in the chip-packaging structure 100 of the present invention, the second reverse side dislocation of the second chip 120 is when being stacked and placed in the first circuit face of the first chip 110, the size of its overlay area, overlay area particular location and stacked time placement direction etc. can be multiple.
Concrete, referring to Fig. 3 and Fig. 4, when the second reverse side dislocation of the second chip 120 is stacked and placed in the first circuit face of the first chip 110, its middle section position place that both can be placed directly within the first circuit face (it should be noted that, middle section position herein refers to certain middle section position on one side of the first circuit face, and it is not the overall center of the first circuit face), it is possible to it is placed directly within the corner location of the first circuit face, as: position, the lower left corner.
Preferably, referring to Fig. 3, preparation for the ease of the chip-packaging structure 100 of the present invention, simplification of flowsheet, as a specific embodiment of the chip-packaging structure 100 of the present invention, the width of the second reverse side of its second chip 120 is preferably less than or equal to the width of the first circuit face of the first chip 110.That is, when carrying out chip package, select the relatively large chip of width as the first chip 110, select the relatively small chip of width as the second chip 120.Thus, when the second reverse side dislocation of the second chip 120 is stacked and placed in the first circuit face of the first chip 110, directly the second reverse side of the second chip 120 can be placed directly within the middle section position of the first circuit face of the first chip 110, the first circuit face of the first chip 110 directly cover the second reverse side of part the second chip 120.And the shape after its encapsulation is comparatively regular, and this also just effectively reduces encapsulation volume, thus further improve the integrated level of IC chip.
Accordingly, in order to further reduce encapsulation difficulty, simplifying encapsulating structure, the side that the side of the wafer 140 being disposed adjacent with the first chip 110 is preferably with the first chip 110 matches.That is, owing to wafer 140 is disposed adjacent with the first chip 110, therefore two sides that wafer 140 is adjacent with the first chip 110 should match, to ensure the seamless applying of wafer 140 and the first chip 110, thus ensureing wafer 140 being completely covered the suspending part of the second reverse side of the second chip 120.This stability that also just further ensure that the IC chip after encapsulation and reliability.
Meanwhile, it should also be noted that fixing being preferably between the overlay area of the first circuit face of the second reverse side of the second chip 120 and the first chip 110 is cohered.That is, by adopting insulating cement part second reverse side of the second chip 120 and the first circuit face of the first chip 110 to be cohered.It is simple to operate, it is easy to accomplish.And it is with low cost.In like manner, the laminating between wafer 140 and the side of the first chip 110 is fixed also by employing insulating cement and coheres.
It addition, it should also be noted that due to wafer 140 be close to the one side of the second chip 120 and the first chip 110 the first circuit face should in the same plane in.Therefore to carrying out wafer 140 and when being disposed adjacent of the first chip 110, it is possible to the relative position relation of accurate assurance wafer 140 and the first chip 110, it is preferred that the thickness of wafer 140 should be equal with the thickness of the first chip 110.Thus, when carrying out when arranging of wafer 140, only need to wafer 140 and the first chip 110 be placed next to each other on the base plate of IC encapsulating shell 130, again the plane of wafer 140 and the first chip 110 need not be calibrated, this also just further simplifies packaging technology, reduce encapsulation difficulty, and also ensure that package quality.
In addition it is also necessary to illustrate, owing to the circuit face of chip generally all can be provided with pad, realize the electrical connection with other chips or device by pad.Therefore, referring to Fig. 3 and Fig. 4, in the chip-packaging structure 100 of the present invention, the first circuit face of its first chip 110 is provided with multiple first pad 111.Further, multiple first pads 111 are respectively positioned on the non-stacking region of the first circuit face of the first chip 110 and the second reverse side of the second chip 120.It is to say, when the second reverse side dislocation of the second chip 120 is stacked and placed in the first circuit face of the first chip 110, it should avoid the pad in the first circuit face, all pads in the first circuit face are revealed.Accordingly, the second circuit face of the second chip 120 being again provided with multiple second pad 121, the base plate of IC encapsulating shell 130 is provided with multiple 3rd pad 131 simultaneously.Wherein, it should be noted that according to practical situation, adopt each first pad 111 that nearby principle is arranged in the first circuit face to be all adjacent the second near pad 121 or the 3rd pad 131 electrically connects.Simultaneously, in multiple second pads 121 set on the second circuit face of the second chip 120, when there is the second pad 121 not electrically connected with the first pad 111, the second pad 121 not electrically connected with the first pad 111 is then set and is adjacent near, and the 3rd pad 131 not electrically connected with the first pad 111 electrically connects.
It is to say, adopt nearby principle to arrange the connection between the second pad 121 of first pad the 111, second chip 120 on the first chip 110 and the 3rd pad 131 on the base plate of IC encapsulating shell 130.
Wherein, it is noted that multiple first pads 111 being arranged in the first circuit face of the first chip 110 can be distributed in the position, axis of the first circuit face of the first chip 110, or is distributed in the periphery of the first circuit face of the first chip 110.Equally, multiple second pads 121 being arranged on the second circuit face of the second chip 120 can preferably be distributed in the periphery in second circuit face, so that the distance between the first chip 110 and the pad of the second chip 120 can be accomplished the shortest.Further, multiple 3rd pads 131 being arranged on the base plate of IC encapsulating shell 130 are then preferably distributed in the periphery of base plate.
Meanwhile, first pad 111 arrangement mode in the first circuit face and second pad 121 arrangement mode on second circuit face can preferably select single arrangement or double arrangement.3rd pad 131 is then single arrangement at the arrangement mode of sole periphery.
In order in the chip-packaging structure 100 of the clearer explanation present invention, first pad the 111, second pad 121 and the 3rd pad 131 arrangement mode on the first circuit face, second circuit face and base plate respectively, be described in detail with three embodiments individually below.
Referring to Fig. 3, in the present embodiment, multiple first pads 111 are distributed in the periphery of the first circuit face of the first chip 110 in single row mode for cloth, multiple second pads 121 are distributed in the periphery in the second circuit face of the second chip 120, the periphery of multiple 3rd same base plates being distributed in IC encapsulating shell 130 with single row mode for cloth of pad 131 equally in single row mode for cloth.Thus, when carrying out the first pad the 111, second pad 121 and when being electrically connected between two of the 3rd pad 131, it is preferred that adopt nearby principle to be attached.Wherein, concrete connection can be shown in Figure 1.It should be noted that when the connection between two carried out between first pad the 111, second pad 121 and the 3rd pad 131, can directly adopt wire to be attached.Preferably, wire can be selected for metal contact wires, as: gold thread, silver wire and copper cash etc..Further, between each connecting line it is order arrangement.That is, situation about all not intersecting between each connecting line.
It addition, referring to Fig. 5, in the present embodiment, multiple first pads 111 are distributed in the first circuit face of the first chip 110 in double-row mode for cloth.Meanwhile, multiple second pads 121 are then distributed in the periphery on the second circuit face of the second chip 120 in single row mode for cloth, in entirely surrounding shape.That is, multiple second pads 121 are on the single second circuit face being arranged in the second chip 120, and are positioned at the side, upper and lower, left and right four in second circuit face.It is understood that it also can be only located at least arbitrarily side in four sides.Multiple 3rd pads 131 are then distributed in the periphery of the base plate of IC encapsulating shell 130 with single row mode for cloth.In this embodiment, when being patterned designing, the connection between first pad the 111, second pad 121 and the 3rd pad 131 adopts nearby principle equally, and does not allow the situation that connecting line intersects occur.Wherein, in the present embodiment, concrete connected mode between pad can be shown in Figure 5.
Further, referring to Fig. 6, in this embodiment, multiple first pads 111 are distributed in the first circuit face of the first chip 110 with single row mode for cloth, and multiple first pad 111 is arranged on the position, axis of the first circuit face.Meanwhile, multiple second pads 121 are then distributed in the periphery on the second circuit face of the second chip 120 with double-row mode for cloth, and in semi-surrounding shape.Concrete, it is as the criterion with direction shown in Fig. 6, multiple pads on the right side being positioned at the second circuit face of the second chip 120 are distributed with double-row mode for cloth, and multiple pads of the upper side and lower side being positioned at the second circuit face of the second chip 120 are then distributed with single row mode for cloth.Multiple 3rd pads 131 are then distributed in the periphery of the base plate of IC encapsulating shell 130 with single row mode for cloth.Equally, the connection between first pad the 111, second pad 121 and the 3rd pad 131 still adopts nearby principle to be attached, and is absent from situation about intersecting between each connecting line, is sequentially arranged.
Further, referring to Fig. 7, in the present embodiment, multiple first pads 111 and multiple second pad 121 arrange with double-row mode for cloth respectively.Wherein, multiple first pads 111 are distributed in the first circuit face of the first chip 110 with double-row mode for cloth, and in semi-surrounding shape.Same, multiple second pads 121 are distributed on the second circuit face of the second chip 120 with double-row mode for cloth, and in semi-surrounding shape.Concrete, it being as the criterion with direction shown in Fig. 7, the second chip 120 dislocation is stacked and placed on the left side of the first circuit face of the first chip 110.Multiple first pads 111 are distributed in the right side of the first circuit face with double-row mode for cloth.Meanwhile, multiple first pads 111 of the upper side and lower side of the first circuit face of the first chip 110 it are distributed in then with single arrangement.The right side in multiple second same second circuit faces being distributed in the second chip 120 with double-row mode for cloth of pad 121.Meanwhile, multiple second pads 121 of the upper side and lower side in the second circuit face of the second chip 120 it are distributed in then with single arrangement.Multiple 3rd pads 131 are then with the periphery of the single base plate being arranged in IC encapsulating shell 130.
Thus, by adopting between the first chip 110 and the second chip 120, multiple different pad arrangement mode is set, make to be electrically connected according to nearby principle between each pad, it is effectively shortened the distance between each pad, thus saving wiring cost further, also simplify wire laying mode simultaneously.And, additionally it is possible to carrying out concrete pad arrangement according to practical situation, this is also just effectively increased the suitability of chip-packaging structure 100 of the present invention, autgmentability and motility.
Wherein, it is to be noted, specific embodiment as the chip-packaging structure 100 of the present invention, distance in order to be further ensured that between pad and pad is minimum, preferably, its arrangement of the first pad 111 being distributed in side in the first circuit face matches with the arrangement of the second pad 121 being distributed in the same side on second circuit face.It is to say, the arrangement mode of multiple first pads 111 of the side being positioned on the first chip 110 should (wherein, this side refers to the side consistent with the first chip 110 with the side being positioned on the second chip 120.That is, the left side of the first chip 110 is consistent with the left side of the second chip 120, and the right side of the first chip 110 is then consistent with the right side of the second chip 120) the arrangement mode of multiple second pads 121 consistent.
Further, it should also be noted that for the significantly more efficient integrated level improving IC chip, thus the plane space of more efficiently control circuit board, as the still another embodiment of the chip-packaging structure 100 of the present invention, it also can encapsulate more functional chip in IC encapsulating shell 130 simultaneously.Hereinafter then to encapsulate four functional chips in IC encapsulating shell 130, the still another embodiment of the chip-packaging structure 100 of the present invention is described in detail.
Concrete, referring to Fig. 8, it also includes the 3rd chip 150 and fourth chip 160.Wherein, the 3rd chip 150 has tertiary circuit face and the 3rd reverse side.Fourth chip 160 has the 4th circuit face and the 4th reverse side.3rd reverse side dislocation of the 3rd chip 150 is stacked and placed on the second circuit face of the second chip 120, simultaneously, another block wafer 140 ' is filled in space between 3rd reverse side and the second circuit face of the second chip 120 of the 3rd chip 150, and the side arranging this wafer 140 and the second chip 120 is close to mutually, and the second circuit face of one side and second chip 120 of this wafer 140 ' next-door neighbour's the 3rd chip 150 in the same plane in so that unsettled for the 3rd chip 150 the 3rd reverse side outside the second chip 120 can be completely covered by this wafer 140 '.Meanwhile, when the 3rd chip 150 is stacked and placed on the second circuit face of the second chip 120, it should make all second pads 121 on second circuit face all reveal, to ensure that the wiring between follow-up pad connects.In like manner, the 4th reverse side of fourth chip 160 then misplaces on the tertiary circuit face being stacked and placed on the 3rd chip 150, and the pad ensured on tertiary circuit face all appears.Simultaneously, also another piece of wafer 140 is filled in the space between the 4th reverse side and the tertiary circuit face of the 3rd chip 150 of fourth chip 160 "; and this wafer 140 " fit tightly with the side of the 3rd chip 150 equally, to ensure this wafer 140 " the tertiary circuit face of one side and the 3rd chip 150 of next-door neighbour's fourth chip 160 in the same plane in, and fourth chip 160 unsettled fourth reverse side threeth chip 150 outside is completely covered.
It is to say, adopt the chip-packaging structure 100 of the present invention, it is possible to realizing encapsulating multiple chips in IC encapsulating shell 130, thus being effectively improved the integrated level of IC chip, and ensureing the state that works alone between each chip, improve the capacity of resisting disturbance of IC chip.It is understood that the number of the wafer 140 being encapsulated in IC encapsulating shell 130 subtracts one again equal to the number of total chip.
Thus, by adopting the chip-packaging structure 100 of the present invention, by the second chip 120 stacked offset on the first chip 110, effectively raise IC chip integration, reduce the production cost of production firm, also effectively reduce the transmission delay of signal simultaneously, improve the reliability of system.And, it is also directed to the non-stacking region of the second chip 120 and the first chip 110, the wafer 140 with the first chip 110 or the second chip 120 same size material is adopted to carry out being completely covered and filling, it is effectively guaranteed the duty of each functional chip, decreases the hydraulic performance decline caused because material is different and power consumption rising etc..
Embodiment described above only have expressed the several embodiments of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to making some deformation and improvement, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a chip-packaging structure, it is characterised in that include the first chip, the second chip, IC encapsulating shell and have and the wafer of described first chip or described second chip same size material；
Described first chip, described second chip and described wafer are all encapsulated in described IC encapsulating shell；
Described first chip has the first circuit face and first reverse side relative with described first circuit face；
Described second chip has second circuit face and second reverse side relative with described second circuit face；
Second reverse side dislocation of described second chip is stacked in the first circuit face of described first chip；
Described wafer is arranged with described first chip by chip；And
Described wafer be close to the first circuit face of the one side of described second chip and described first chip in the same plane in, and cover the second reverse side not being stacked in described first circuit face.
2. chip-packaging structure according to claim 1, it is characterised in that the width of described second reverse side is less than or equal to the width of described first circuit face；
The side of the side of described wafer and described first chip matches.
3. chip-packaging structure according to claim 1, it is characterised in that the thickness of described wafer is equal with the thickness of described first chip.
4. chip-packaging structure according to claim 1, it is characterised in that the second reverse side of described second chip is fixing with the overlay area of the first circuit face of described first chip to be cohered.
5. chip-packaging structure according to claim 1, it is characterised in that the side of described wafer is fixing with the side of described first chip coheres.
6. the chip-packaging structure according to any one of claim 1 to 5, it is characterised in that be provided with multiple first pad in described first circuit face；And
Multiple described first pads are respectively positioned on the non-stacking region of the first circuit face of described first chip and the second reverse side of described second chip；
Described second circuit face is provided with multiple second pad；
The base plate of described IC encapsulating shell is provided with multiple 3rd pad；
Wherein, multiple described first pads are distributed in the position, axis of described first chip or the periphery of the first circuit face of described first chip；
Multiple described second pads are distributed in the periphery in the second circuit face of described second chip；
Multiple described 3rd pads are distributed in the sole periphery of described IC encapsulating shell.
7. chip-packaging structure according to claim 6, it is characterised in that multiple described first pads and multiple described second pad are all in single or double arrangement.
8. chip-packaging structure according to claim 6, it is characterised in that multiple described 3rd pads are single arrangement.
9. chip-packaging structure according to claim 6, it is characterised in that the arrangement of the arrangement of described first pad being distributed in described first circuit face side and described second pad being distributed on described second circuit face the same side matches.
10. chip-packaging structure according to claim 6, it is characterised in that electrically connected by wire between multiple described first pads, multiple described second pad and multiple described 3rd pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610278166.9A CN105762122A (en) | 2016-04-28 | 2016-04-28 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114937658A (en) * | 2022-07-21 | 2022-08-23 | 湖北三维半导体集成创新中心有限责任公司 | Chip system |
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|---|---|---|---|---|
| US20040026789A1 (en) * | 2002-08-08 | 2004-02-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN204102862U (en) * | 2014-08-01 | 2015-01-14 | 深圳市兴森快捷电路科技股份有限公司 | A kind of based on bulk technology multi-chip superposition packaging system |
| CN105390482A (en) * | 2015-11-25 | 2016-03-09 | 北京握奇数据系统有限公司 | Stacked chip and processing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20040026789A1 (en) * | 2002-08-08 | 2004-02-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN204102862U (en) * | 2014-08-01 | 2015-01-14 | 深圳市兴森快捷电路科技股份有限公司 | A kind of based on bulk technology multi-chip superposition packaging system |
| CN105390482A (en) * | 2015-11-25 | 2016-03-09 | 北京握奇数据系统有限公司 | Stacked chip and processing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114937658A (en) * | 2022-07-21 | 2022-08-23 | 湖北三维半导体集成创新中心有限责任公司 | Chip system |
| CN114937658B (en) * | 2022-07-21 | 2022-10-25 | 湖北三维半导体集成创新中心有限责任公司 | Chip system |
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