CN105759517A - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- CN105759517A CN105759517A CN201410781424.6A CN201410781424A CN105759517A CN 105759517 A CN105759517 A CN 105759517A CN 201410781424 A CN201410781424 A CN 201410781424A CN 105759517 A CN105759517 A CN 105759517A
- Authority
- CN
- China
- Prior art keywords
- transistor
- row
- display device
- sub
- pixels
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003491 array Methods 0.000 claims description 2
- 230000000007 visual effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Abstract
A display device comprises a plurality of data lines, a plurality of scanning lines and at least two pixels, wherein the data lines and the scanning lines jointly define a pixel array, and the pixels are configured in the pixel array and jointly comprise two first sub-pixels, two second sub-pixels and two third sub-pixels. One of the first sub-pixels is arranged in a first direction and comprises a first transistor, the other of the first sub-pixels is arranged in a second direction and comprises a second transistor, one of the second sub-pixels is arranged in the first direction and comprises a third transistor, the other of the second sub-pixels is arranged in the second direction and comprises a fourth transistor, one of the third sub-pixels is arranged in the first direction and comprises a fifth transistor, and the other of the third sub-pixels is arranged in the second direction and comprises a sixth transistor.
Description
Technical field
The present invention is related to a kind of Display Technique, and in particular to a kind of display device.
Background technology
Along with Progress & New Products, the technology of display device with day by day progress greatly.General display device adopts twisted nematic (TwistedNematic, TN) liquid crystal technology, but, for user, it is only capable of viewing and admiring the display device adopting TN technology in the angular field of view of level 120 degree and vertical 90 degree.
For meeting the user demand for wider angular field of view, in order to user views and admires display device, and wide viewing angle technology (FringeFieldSwitching, FFS) is arisen at the historic moment.The display device adopting FFS technology is provided that user is close to the angular field of view of 180 degree, and therefore, display device adopts FFS technology mostly now.But, adopt the display device of FFS technology still to have some defects such as colour cast and power consumption, and affect the perception of user.
Summary of the invention
One purpose of present invention is to provide a kind of display device, comprises:
A plurality of data lines；
Multi-strip scanning line, wherein these data wires and these scanning line common definition one pel arrays, this pel array comprises multiple row and multiple row row, and wherein these row are parallel with these scanning lines, and these row are parallel with these data wires；And
At least two pixel, is configured in this pel array, and these pixels jointly comprise:
Two the first sub-pixels, wherein these first sub-pixels therein one are configured at a first direction and comprise a first transistor, in these first sub-pixels, another one is configured at a second direction and comprises a transistor seconds, and wherein this first direction is different from this second direction；
Two the second sub-pixels, wherein these second sub-pixels therein one are configured at this first direction and comprise a third transistor, and in these second sub-pixels, another one is configured at this second direction and comprises one the 4th transistor；And
Two the 3rd sub-pixels, wherein these the 3rd sub-pixels therein one are configured at this first direction and comprise one the 5th transistor, and in these the 3rd sub-pixels, another one is configured at this second direction and comprises one the 6th transistor；
Wherein this first transistor, this third transistor and the 5th transistor are configured at a first row of this pel array；
Wherein this first row comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this first row, wherein this first transistor is configured at this first side of this first row, this third transistor is configured at this second side of this first row, and the 5th transistor is configured at this first side of this first row.
Above-mentioned display device, wherein this transistor seconds, the 4th transistor and the 6th transistor are configured at one second row of this pel array, wherein this second row comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this second row, wherein this transistor seconds is configured at this first side of this second row, 4th transistor is configured at this second side of this second row, and the 6th transistor is configured at this first side of this second row.
Above-mentioned display device, wherein this first transistor and this transistor seconds are configured at a first row of this pel array.
Above-mentioned display device, wherein this first row comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this first row, and wherein this first transistor is configured at this first side of this first row, and this transistor seconds is configured at this second side of this first row.
Above-mentioned display device, wherein this third transistor and the 4th transistor are configured at a secondary series of this pel array.
Above-mentioned display device, wherein this secondary series comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this secondary series, and wherein this third transistor is configured at this first side of this secondary series, and the 4th transistor is configured at this second side of this secondary series.
Above-mentioned display device, wherein the 5th transistor and the 6th transistor are configured at one the 3rd row of this pel array.
Above-mentioned display device, wherein the 3rd row comprise one first side and one second side, this first side and this second side are positioned at this tertial opposite sides, and wherein the 5th transistor is configured at this this first side tertial, and the 6th transistor is configured at this this second side tertial.
Above-mentioned display device, wherein these scanning lines comprise a scan line to one the 4th scan line, wherein this scan line scans line sequential to the 4th, wherein this scan line is coupled to this transistor seconds, this the second scanning line is coupled to this first transistor and this third transistor, this three scan line is coupled to the 4th transistor and the 6th transistor, and the 4th scanning line is coupled to the 5th transistor.
Above-mentioned display device, wherein these data wires comprise one first data wire, one second data wire and one the 3rd data wire, wherein this first data wire, this second data wire and the 3rd data wire sequential, wherein this first data wire is coupled to this third transistor, this second data wire is coupled to this first transistor, the 4th transistor and the 5th transistor, and the 3rd data wire is coupled to this transistor seconds and the 6th transistor.
Therefore, the technology contents according to the present invention, by providing a kind of display device, allow user no matter watch above-mentioned display device from orientation, the viewing visual angle of user is all identical and can improve color offset phenomenon.Additionally, the pixel configuration mode of above-mentioned display device can make its effective area identical, without affecting the taste of display device and improving the phenomenon of bright dark fringe.Furthermore, by pixel array configuration mode, gate drivers can be made only to need to provide the row polarity inversion signal of relatively power saving, the driving effect of point-polarity reversion can be produced on the pel array of display device.
Accompanying drawing explanation
For the above and other purpose of the present invention, feature, advantage and embodiment can be become apparent, the explanation of appended accompanying drawing is as follows:
Fig. 1 is the schematic diagram of the pel array illustrating a kind of display device according to one embodiment of the invention；
Fig. 2 is the schematic diagram of the pel array illustrating a kind of display device according to another embodiment of the present invention；
Fig. 3 is the circuit box schematic diagram illustrating a kind of display device according to further embodiment of this invention；
Fig. 4 is the schematic diagram of the partial pixel array illustrating a kind of display device as shown in Figure 3 according to another embodiment of the present invention；
Fig. 5 is the schematic diagram of the partial pixel array illustrating a kind of display device as shown in Figure 3 according to yet another embodiment of the invention.
Wherein, accompanying drawing labelling:
100,200,400,400A: pel array r1: first row
1000: display device r2: secondary series
1100: display floater r3: the three arranges
1200: data driver SP1, SP2: the first sub-pixel
1300: gate drivers SP3, SP4: the second sub-pixel
B: blue sub-pixels SP5, SP6: the three sub-pixel
C1: the first row T1: the first transistor
C2: the second row T2: transistor seconds
D1～Dn: data wire T3: third transistor
Dir1: first direction the T4: the four transistor
Dir2: second direction T5: the five transistor
G: green sub-pixel the T6: the six transistor
G1～Gn: scanning line V1, V2: visual angle
R: red sub-pixel
Detailed description of the invention
Fig. 1 is the schematic diagram of the pel array 100 illustrating a kind of display device according to one embodiment of the invention.As it can be seen, the configuration mode of pel array 100 is the configuration mode that all pixels are configured at same direction (1Pixel1Dimension, 1P1D).The angular field of view that this kind of configuration mode can provide user to be close to 180 degree, but, owing to user is different in the viewing angle of visual angle V2 from user in the viewing angle of visual angle V1, therefore, it is easy to produce the phenomenon of colour cast.
Fig. 2 is the schematic diagram of the pel array 200 illustrating a kind of display device according to another embodiment of the present invention.As it can be seen, the configuration mode of pel array 200 is the configuration mode that pixel configuration is respectively arranged at both direction (2Pixels2Dimensions, 2P2D).The angular field of view that this kind of configuration mode can provide user to be close to 180 degree, further, since user is identical in the viewing angle of visual angle V2 with user in the viewing angle of visual angle V1, and can improve the color offset phenomenon of display device.
Fig. 3 is the circuit box schematic diagram illustrating a kind of display device 1000 according to further embodiment of this invention.As it can be seen, above-mentioned display device 1000 comprises display floater 1100, data driver 1200 and gate drivers 1300.Above-mentioned data driver 1200 is coupled to a plurality of data lines D1～Dn, and above-mentioned gate drivers 1300 is coupled to multi-strip scanning line G1～Gm.Additionally, display floater 1100 comprises multiple pixel, the configuration mode of above-mentioned pixel refers to Fig. 4.
Fig. 4 is the schematic diagram of the partial pixel array 400 illustrating a kind of display device 1000 as shown in Figure 3 according to another embodiment of the present invention.As it can be seen, it shows the configuration mode of two pixels in pel array 400 illustratively.Above-mentioned pixel jointly comprises two the first sub-pixel SP1, SP2, two second sub-pixel SP3, SP4 and two the 3rd sub-pixels SP5, SP6.
In structure configure on, data wire D1～D3 and scanning the above-mentioned pel array 400 of line G1～G4 common definition, namely above-mentioned pixel is arranged in pel array 400.This pel array 400 comprises multiple row r1～r3 and multirow c1～c2.Above-mentioned row r1～r3 is parallel with scanning line G1～G4, and above-mentioned row c1～c2 is parallel with data wire D1～D3.
In the present embodiment, the first sub-pixel SP1 is configured at first direction Dir1 and comprises the first transistor T1, and the first sub-pixel SP2 is configured at second direction Dir2 and comprises transistor seconds T2, and above-mentioned first direction Dir1 is different from second direction Dir2.Additionally, the second sub-pixel SP3 is configured at first direction Dir1 and comprises third transistor T3, the second sub-pixel SP4 is configured at second direction Dir2 and comprises the 4th transistor T4.Furthermore, the 3rd sub-pixel SP5 is configured at first direction Dir1 and comprises the 5th transistor T5, and the 3rd sub-pixel SP6 is configured at second direction Dir2 and comprises the 6th transistor T6.
Furthermore, above-mentioned the first transistor T1, third transistor T3 and the 5th transistor T5 are configured at the first row c1 of pel array 400.Above-mentioned the first row c1 comprises the first side (such as right side) and the second side (such as left side), the first side and the second side are positioned at the opposite sides of the first row c1.Above-mentioned the first transistor T1 is configured at first side (such as right side) of the first row c1, and third transistor T3 is configured at second side (such as left side) of the first row c1, and the 5th transistor T5 is configured at first side (such as right side) of the first row c1.
Thus, the configuration mode of 2P2D is adopted based on the pel array 400 shown in Fig. 4, except the angular field of view that user can be provided to be close to 180 degree, owing to user is identical in the viewing angle of visual angle V2 with user in the viewing angle of visual angle V1, and the color offset phenomenon of display device 1000 can be improved.On the other hand, owing to the first transistor T1, third transistor T3 and the 5th transistor T5 adopt the configuration mode of alternating expression, and it is arranged in the both sides of the first row c1, therefore, user is identical in the visual angle V2 effective area watching pel array 400 with user in the visual angle V1 effective area watching pel array 400, and reaches to make the purpose of the both sides effective area homogeneity of pel array 400.Generally speaking, the configuration mode of the pel array 400 of the display device 1000 that Fig. 4 provides, it is optimised the color offset phenomenon of display device 1000 and reduces the shortcoming that its taste is bad, and then promoting display taste.
In another embodiment, refer to Fig. 4, transistor seconds T2, the 4th transistor T4 and the 6th transistor T6 are configured at the second row c2 of pel array 400, this second row c2 comprises the first side (such as right side) and the second side (such as left side), the first side and the second side are positioned at the opposite sides of the second row c2.Above-mentioned transistor seconds T2 is configured at first side (such as right side) of the second row c2, and the 4th transistor T4 is configured at second side (such as left side) of the second row c2, and the 6th transistor T6 is configured at first side (such as right side) of the second row c2.
In another embodiment, refer to Fig. 4, the first transistor T1 and transistor seconds T2 and be configured at the first row r1 of pel array 400.On the other hand, aforementioned first row r1 comprises the first side (such as downside) and the second side (such as upside), the first side and the second side are positioned at the opposite sides of first row r1.Above-mentioned the first transistor T1 is configured at first side (such as downside) of first row r1, and transistor seconds T2 is configured at second side (such as upside) of first row r1.
In another embodiment, refer to Fig. 4, third transistor T3 and the 4th transistor T4 is configured at the secondary series r2 of pel array 400.On the other hand, aforementioned secondary series r2 comprises the first side (such as upside) and the second side (such as downside), the first side and the second side are positioned at the opposite sides of secondary series r2.Above-mentioned third transistor T3 is configured at first side (such as upside) of secondary series r2, and the 4th transistor T4 is configured at second side (such as downside) of secondary series r2.
In another embodiment, referring to Fig. 4, the 5th transistor T5 and the 6th transistor T6 is configured at the 3rd row r3 of pel array 400.On the other hand, above-mentioned 3rd row r3 comprise the first side (such as downside) and the second side (such as upside), the first side and the second side be positioned at the 3rd row r3 opposite sides.Above-mentioned 5th transistor T5 is configured at first side (such as downside) of the 3rd row r3, and the 6th transistor T6 is configured at second side (such as upside) of the 3rd row r3.
In another embodiment, refer to Fig. 4, scan line G1～G4 sequential.Scanning line G1 is coupled to transistor seconds T2, scanning line G2 and is coupled to the first transistor T1 and third transistor T3, and scanning line G3 is coupled to the 4th transistor T4 and the 6th transistor T6, scans line G4 and is coupled to the 5th transistor T5.
In another embodiment, refer to Fig. 4, data wire D1～D3 sequential.Data wire D1 is coupled to third transistor T3, data wire D2 and is coupled to the first transistor T1, the 4th transistor T4 and the 5th transistor T5, and data wire D3 is coupled to transistor seconds T2 and the 6th transistor T6.
Refer to the schematic diagram that Fig. 5, Fig. 5 are the partial pixel array 400A illustrating a kind of display device 1000 as shown in Figure 3 according to yet another embodiment of the invention.It should be noted that, the base pixel array configuration in the display device 1000 that pel array 400 is the present invention shown in Fig. 4, the extension configuration mode that pel array 400A is Fig. 4 pel array shown in Fig. 5.The state aware of sub-pixel as shown in Figure 5, scanning line G2 provides the scanning signal of 0V, and scanning line G3 provides the scanning signal lower than 0V, and scans line G4 and provide the scanning signal higher than 0V, to drive the pel array 400A of display device 1000.Additionally, scanning line G5 provides the scanning signal of 0V, scanning line G6 provides scanning signal lower than 0V, and scans line G7 and provide the scanning signal higher than 0V, all the other scanning lines provide scanning signal condition can the rest may be inferred；Only need to provide the signal of row polarity inversion (Columninversion) due to gate drivers 1300, therefore, will not increase the power consumption of the gate drivers 1300 of display device 1000, old friend's pel array 400,400A particular arrangement mode the pel array 400 of display device 1000,400A can be made to produce the driving effect of point-polarity reversion (Dotinversion).
In sum, display device provided by the invention, at least have the advantage that and allow user no matter watch from orientation, the viewing visual angle of user is all identical, and can optimize and improve color offset phenomenon.Additionally, its effective area can be made identical through pixel configuration mode, improve the phenomenon of bright dark fringe.Furthermore, by pixel array configuration mode, gate drivers can be made only to need to provide the row polarity inversion signal of relatively power saving, the driving effect of point-polarity reversion can be produced on the pel array of display device.
Claims (10)
1. a display device, it is characterised in that comprise:
A plurality of data lines；
Multi-strip scanning line, wherein these data wires and these scanning line common definition one pel arrays, this pel array comprises multiple row and multiple row row, and wherein these row are parallel with these scanning lines, and these row are parallel with these data wires；And
At least two pixel, is configured in this pel array, and these pixels jointly comprise:
Two the first sub-pixels, wherein these first sub-pixels therein one are configured at a first direction and comprise a first transistor, in these first sub-pixels, another one is configured at a second direction and comprises a transistor seconds, and wherein this first direction is different from this second direction；
Two the second sub-pixels, wherein these second sub-pixels therein one are configured at this first direction and comprise a third transistor, and in these second sub-pixels, another one is configured at this second direction and comprises one the 4th transistor；And
Two the 3rd sub-pixels, wherein these the 3rd sub-pixels therein one are configured at this first direction and comprise one the 5th transistor, and in these the 3rd sub-pixels, another one is configured at this second direction and comprises one the 6th transistor；
Wherein this first transistor, this third transistor and the 5th transistor are configured at a first row of this pel array；
Wherein this first row comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this first row, wherein this first transistor is configured at this first side of this first row, this third transistor is configured at this second side of this first row, and the 5th transistor is configured at this first side of this first row.
2. display device as claimed in claim 1, it is characterized in that, wherein this transistor seconds, the 4th transistor and the 6th transistor are configured at one second row of this pel array, wherein this second row comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this second row, wherein this transistor seconds is configured at this first side of this second row, 4th transistor is configured at this second side of this second row, and the 6th transistor is configured at this first side of this second row.
3. display device as claimed in claim 1, it is characterised in that wherein this first transistor and this transistor seconds are configured at a first row of this pel array.
4. display device as claimed in claim 3, it is characterized in that, wherein this first row comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this first row, wherein this first transistor is configured at this first side of this first row, and this transistor seconds is configured at this second side of this first row.
5. display device as claimed in claim 1, it is characterised in that wherein this third transistor and the 4th transistor are configured at a secondary series of this pel array.
6. display device as claimed in claim 5, it is characterized in that, wherein this secondary series comprises one first side and one second side, this first side and this second side are positioned at the opposite sides of this secondary series, wherein this third transistor is configured at this first side of this secondary series, and the 4th transistor is configured at this second side of this secondary series.
7. display device as claimed in claim 1, it is characterised in that wherein the 5th transistor and the 6th transistor are configured at one the 3rd row of this pel array.
8. display device as claimed in claim 7, it is characterized in that, wherein the 3rd row comprise one first side and one second side, this first side and this second side are positioned at this tertial opposite sides, wherein the 5th transistor is configured at this this first side tertial, and the 6th transistor is configured at this this second side tertial.
9. display device as claimed in claim 1, it is characterized in that, wherein these scanning lines comprise a scan line to one the 4th scan line, wherein this scan line scans line sequential to the 4th, wherein this scan line is coupled to this transistor seconds, this the second scanning line is coupled to this first transistor and this third transistor, and this three scan line is coupled to the 4th transistor and the 6th transistor, and the 4th scanning line is coupled to the 5th transistor.
10. display device as claimed in claim 9, it is characterized in that, wherein these data wires comprise one first data wire, one second data wire and one the 3rd data wire, wherein this first data wire, this second data wire and the 3rd data wire sequential, wherein this first data wire is coupled to this third transistor, this second data wire is coupled to this first transistor, the 4th transistor and the 5th transistor, and the 3rd data wire is coupled to this transistor seconds and the 6th transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103133583A TW201612613A (en) | 2014-09-26 | 2014-09-26 | Display device |
| TW103133583 | 2014-09-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105759517A true CN105759517A (en) | 2016-07-13 |
| CN105759517B CN105759517B (en) | 2019-06-04 |
Family
ID=56335723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410781424.6A Expired - Fee Related CN105759517B (en) | 2014-09-26 | 2014-12-16 | Display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105759517B (en) |
| TW (1) | TW201612613A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200842791A (en) * | 2007-04-25 | 2008-11-01 | Novatek Microelectronics Corp | LCD and display method thereof |
| US20120008059A1 (en) * | 2010-07-06 | 2012-01-12 | Samsung Electronics Co., Ltd. | Liquid crystal display |
| CN102566176A (en) * | 2010-11-24 | 2012-07-11 | 三星移动显示器株式会社 | Display substrate, display panel and display device |
| CN102629056A (en) * | 2011-11-15 | 2012-08-08 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) array substrate and display device |
| CN103926715A (en) * | 2013-11-18 | 2014-07-16 | 上海中航光电子有限公司 | Pixel unit, pixel array structure and display device |
-
2014
- 2014-09-26 TW TW103133583A patent/TW201612613A/en unknown
- 2014-12-16 CN CN201410781424.6A patent/CN105759517B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200842791A (en) * | 2007-04-25 | 2008-11-01 | Novatek Microelectronics Corp | LCD and display method thereof |
| US20120008059A1 (en) * | 2010-07-06 | 2012-01-12 | Samsung Electronics Co., Ltd. | Liquid crystal display |
| CN102566176A (en) * | 2010-11-24 | 2012-07-11 | 三星移动显示器株式会社 | Display substrate, display panel and display device |
| CN102629056A (en) * | 2011-11-15 | 2012-08-08 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) array substrate and display device |
| CN103926715A (en) * | 2013-11-18 | 2014-07-16 | 上海中航光电子有限公司 | Pixel unit, pixel array structure and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201612613A (en) | 2016-04-01 |
| CN105759517B (en) | 2019-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI637378B (en) | Liquid crystal display | |
| CN106249489B (en) | Liquid crystal display and its array substrate | |
| CN103187038B (en) | A kind of double-gate liquid crystal display device and driving method thereof | |
| CN103926730B (en) | Display device | |
| US20170221436A1 (en) | Liquid crystal panels and the driving circuits thereof | |
| CN105261339B (en) | The driving method of liquid crystal display and liquid crystal panel and liquid crystal panel | |
| TWI428900B (en) | Sub-pixel circuit, display panel and driving method of flat display panel | |
| KR102498791B1 (en) | Display apparatus | |
| CN102707525A (en) | Array substrate, liquid crystal display panel and liquid crystal display device | |
| WO2016000343A1 (en) | Pixel array and driving method thereof and display panel | |
| CN103809313A (en) | Liquid crystal display device and method of driving the same | |
| US9082357B2 (en) | LCD display with pixels having RGBW sub-pixels and where power consumption is reduced by using a polarity inversion pattern in which all red sub-pixels in a column have the same polarity | |
| TWI502262B (en) | Pixel array | |
| CN105761659A (en) | Display device | |
| JPWO2010119597A1 (en) | Display device, liquid crystal display device, driving method of display device, and television receiver | |
| US20180182320A1 (en) | Half source driving liquid crystal display panel and liquid crystal display | |
| KR102423424B1 (en) | Liquid display device | |
| TWI522718B (en) | Pixel array | |
| WO2016041215A1 (en) | Pixel array, display panel and display apparatus | |
| KR101714952B1 (en) | Liquid crystal display panel and driving method thereof | |
| US20120169677A1 (en) | Liquid crystal display and liquid crystal display panel thereof | |
| WO2017063273A1 (en) | Pixel structure | |
| KR102485545B1 (en) | Liquid crystal display device | |
| TWI398713B (en) | Array substrate and flat display device | |
| CN103207489A (en) | Pixel structure, driving method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190604 Termination date: 20201216 |