CN105759255A - CIC multiphase interpolation filter ultrasonic phased array beam delay method - Google Patents

Abstract

The invention discloses a CIC multiphase interpolation filter ultrasonic phased array beam delay method. The method comprises the steps of A, stimulating a multi-array element probe through the focal law, and carrying receiving delay focusing of reflected waves; B, carrying out echo upsampling, increasing the sampling rate from fs to I fs, and meanwhile, carrying out I-path decomposition to form the adjacent two-path 1/(I fs) delay accuracy; and C, achieving multiphase interpolation filter through an N-order CIC filter. The method provided by the invention is based on precise time sequence control and rapid parallel processing capabilities of an FPGA, combines the advantages of flexibility, small computation amount and high anti-mirroring capability that is easily up to 120dB of a CIC interpolation filter, proposes an upsampling zero insertion technique, carries out signal I-time zero interpolation and then filtering, filters out high frequency components through anti-imaging filtering, increases the ultrasonic echo sampling rate from fs to I fs, and meanwhile carries out I-path decomposition to form the adjacent two-path 1/(I fs) delay accuracy.

Description

A kind of CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method

Technical field

The present invention relates to a kind of CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method.

Background technology

Ultrasonic phased array technology is by carrying out high pressure activation phase delay to array element each in supersonic array transducer Control, then the back wave receiving many array elements carries out delay and focusing, to obtain the most controlled synthesis wave beam And the random control of focus position, it is achieved acoustic beam arbitrarily deflects azimuth scan each to workpiece, dynamic to realize State focusing, high speed scanning, sectoring, can detection of complex shaped objects etc., need to be by accurate delay skill Art provides and ensures, is the study hotspot of current Ultrasonic NDT.Wherein, it is achieved accurate focusing time delay is The core of the various focusing algorithm of ultrasonic phase array and difficult point, and form hardware lines time delay, sampling time delay, specially With precision delay methods such as chip time delay, software delays, but its poor universality, cost are high, amendment controls The shortcomings such as difficulty；Software delay is made by digital signal processing algorithm flexibly, realizes the side of accurate delay Method, has highly versatile, the good feature of transplantability, but algorithm is complex, it is achieved method is with skill always It is people's study hotspots.

Cic filter is made up of comb filter and integrator, has linear phase in passband, and hardware is real Now have only to adder, shift unit and register, take resource less, it is achieved simple and speed faster, There is LPF effect, and interpolation and the filtering extraction of arbitrary integer times can be carried out, use CIC to make For polyphase interpolating filter, then can realize performance more preferably velocity of wave time delay.In view of FPGA inside sequential, The particularity of combinational circuit, can fast parallel real-time process signal characteristic, prolong in conjunction with ultrasonic phase array instrument Time focusing principle, with FPGA realize CIC polyphase interpolating filter thin delay algorithm, more traditional time-delay method In terms of operand, calculating speed, resolving power, cost performance, it is respectively provided with greater advantage, is very suitable for reality The focusing delay algorithm that Shi Xingqiang, precision are high realizes.Functional simulation is carried out finally by ModelSim, by FPGA verifies its effect.

Summary of the invention

For solving above-mentioned technical problem, it is an object of the invention to provide a kind of CIC (Cascaded Integrator Comb) polyphase interpolating filtering ultrasound phase-control array beam time-delay method, to conventional hardware line time delay, The schemes such as sampling time delay, special chip time delay, software delay improve, and by liter Sampling techniques, adopt Sample rate is from f_sRise to I f_s, I road is decomposed simultaneously, forms adjacent two-way 1/ (I f_s) delay precision.

The purpose of the present invention is realized by following technical scheme:

A kind of CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method, including:

A encourages many array elements to pop one's head in by focusing on rule, and back wave is received delay and focusing；

B echo rises sampling, and sample rate is from f_sRise to I f_s, I road is decomposed simultaneously, forms adjacent two-way 1/ (I f_s) Delay precision；

C realizes polyphase interpolating by N rank cic filter and filters.

Compared with prior art, one or more embodiments of the invention can have the advantage that

Based on FPGA SECO accurately, fast parallel disposal ability, in conjunction with CIC interpolation filter Flexibly, operand mirror image ability little, anti-the most easily reaches the advantages such as-120dB, proposition liter sampling zero insertion skill Art, filters zero insertion in signal I times again, filters radio-frequency component by anti-mirror image, and ultrasonic echo is adopted Sample rate is from f_sRise to I f_s, I road is decomposed simultaneously, forms adjacent two-way 1/ (I f_s) delay precision.

Accompanying drawing explanation

Accompanying drawing is for providing a further understanding of the present invention, and constitutes a part for specification, with this Inventive embodiment is provided commonly for explaining the present invention, is not intended that limitation of the present invention.In the accompanying drawings:

Fig. 1 is that CIC polyphase interpolating filters ultrasound phase-control array beam time-delay method flow chart；

Fig. 2 is based on polyphase interpolating filtering delay-time focusing principle figure；

Fig. 3 is that data signal rises sampling flow chart；

Fig. 4 is typical I times of interpolation cic filter structured flowchart；

Fig. 5 is that any times of CIC polyphase interpolating filtering FPGA realizes general term circuit structure；

Fig. 6 is the poly phase algorithm simulating result of interpolation 10 times.

Detailed description of the invention

For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing The present invention is described in further detail.

As it is shown in figure 1, filter ultrasound phase-control array beam time-delay method flow chart for CIC polyphase interpolating, should Method comprises the steps:

Step 10 encourages many array elements to pop one's head in by focusing on rule, and back wave is received delay and focusing；

Exploitativeness based on delay algorithm, versatility, use thick time delay to combine with thin time delay method, Realizing wide scope, in high precision time delay, Fig. 2 is based on polyphase interpolating filtering delay-time focusing principle figure, ADC The echo-signal gathered is by thick time delay, thin time delay, focus module, and its key step is as follows:

(1) thick time delay: based on FPGA sequence circuit feature, by trigger or internal memory successively read-write Mode carries out thick time delay, delay precision Δ D_tBy system clock cycle (sampling period) T_s=1/f _s Determine；

(2) thin time delay: then realized by software algorithm less than the thin time delay in sampling period, i.e. high power interpolation Technology improves sample rate, reduces the sampling time, and alleviates FPGA signal transacting by poly phase technology Load improves thin delay precision, sample rate f simultaneously_sEcho-signal polyphase interpolating I times (simultaneously I road decompose), Sample rate is promoted to I f_s, form adjacent two-way 1/ (I f_s) delay precision (such as f_s=100MHz, I=10 are then ΔD_t=1ns)；

(3) focus on: realized by current array probe wafer receipt each road signal phasor superposition, to realize energy Amount polymerization, improves signal to noise ratio.Anticipated various delay times are realized by the combination of time delay thick, thin, its Time delay width scope, in high precision, controllability is strong, provides focusing accuracy accurately for ultrasonic phase array instrument.

Step 20 echo rises sampling, and sample rate is from f_sRise to I f_s, I road is decomposed simultaneously, forms adjacent two Road 1/ (I f_s) delay precision, concrete methods of realizing is as follows:

The sample rate of echo-signal is f_s, sampling time Δ T between two sampling points_s=1/f_s, interpositioning can be passed through, Carry out I times of interpolating sampling rate and rise to I f_s, then sampling time Δ T between two sampling points_s=1/ (I f_s), its precision carries High I times, its echo-signal delay and focusing precision is 1/ (I f_s), Fig. 3 is that data signal rises sampling flow chart；

(1) I times of interpolater, inserts I-1 null value, i.e. realizes I times of interpolation between two original sample point, Speed rises to I f_s；

(2) filtering of anti-mirror image, can make the frequency spectrum of primary signal change after zero insertion, if original series And frequency spectrum is respectively x (n), X (e^jw), then the time domain sequences after interpolation is respectively as follows: with frequency domain spectra

$x^{\′}\left(m\right)=\left\{\begin{array}{cc}x\left(\frac{m}{I}\right),& m=0,\±I,\±I,...\\ 0,& others\end{array}\right.,---\left(1\right)$

X′(e^jω)=X (e^jωI)

Then after interpolation, signal spectrum is that original series frequency spectrum obtains after I times is compressed, and the frequency spectrum after interpolation produces The raw cycle is π/I image component, can be by band a width of π/I, length L low pass filter h_LP(n)(H_LP(ω)) Recover primary signal.

Step 30 realizes polyphase interpolating by N rank cic filter and filters, setting of polyphase interpolating filter Meter, it is achieved step is as follows:

The mathematic(al) representation of N rank cic filter is:

$H\left(z\right)={\left[\underset{k=0}{\overset{I\·M-1}{\mathrm{\Σ}}}{z}^{-k}\right]}^N$ Or $H\left(z\right)=\frac{{(1-z^{-I\·M})}^N}{{(1-z^{-1})}^N}---\left(2\right)$

From formula (2) it can be seen that N rank cic filter equivalence can be equivalent to N number of integrator, comb filtering The combination of device.

Its parameter declaration is as follows: the 1. exponent number of N-CIC wave filter；2. I-extraction or interpolation coefficient；③ The delay factor of M-comb filtering part, typically takes 1.

N rank cic filter is made up of N number of comb filter and integrator, the specific feedback structure existed, Make its structure can not carry out poly phase simply, it is achieved polyphase interpolating filters.

Fig. 4 is typical I times of interpolation cic filter structured flowchart, by comb filter, interpolater, Integrator forms, and because after the interpolated device of signal, speed can drastically promote, typical form interpolation makes at FPGA I f after reason interpolation_sRate signal difficulty strengthens, therefore must transform interpolater, integrator part.Can make Interpolation filtering, poly phase are carried out simultaneously, at f_s(non-I f_s) run under digital display circuit frequency, hard to alleviate Part load, then make that system is more stable, reliability service.

Interpolater integrator in Fig. 4 is analyzed, each register z in integrator_iIt is equivalent to one Accumulator, is f to this interpolation filter input sampling rate_sSerial No., analyze output result.In Slotting I times of i.e. each two sampling point interleaves I-1 zero, is operated in I f_sThe integrator of speed, the most every I 1/I·f_sOne effective sampling point of sampling period input, the input of remaining moment is zero, it is not necessary to carry out computing, as It is can to merge interpolater, integrator, in sample rate f_sUnder complete interpolation filtering computing, Fig. 5 for improve after Any times of CIC polyphase interpolating filtering FPGA realizes general term circuit structure, i.e. in sample rate f_sUnder by many Export mutually, but realize any times of interpolation filtering.

To node adder each in Fig. 5In tax, (x, y), if integral part correspondence register value divides coordinate p Wei z₀、z₁、…、z_N, can obtain Y (i) (i=0,1 ..., I-1) must be variable z₀、z₁、…、z_N's One order polynomial, makes Y (i)=A₀z₀+A₁z₁+A₂z₂+…+A_Nz_N, solve coefficient A below_i.If (i j) is p (i, j) value that node is corresponding, the value that can obtain each node according to Fig. 5 has following recurrence relation to this moment coordinate Formula:

Discounting for median p (i-1, j-1) and p (i, j-1), can directly use t_mMoment nodal value p (0,0)=z₀、 P (0,1)=z₁, p (0,2)=z₂..., p (0, N)=z_NExpression p (x, y).

Given time node (i, 0) is as starting point, and (x, path y) are related to ask between two nodes to seek node (m × n rectangular mesh, upper right angle point to lower-left angle point shortest path number is short path number problemThen Coordinate (i, 0) arrives (x, shortest path number A y)_iCan represent:

$A_i=\left\{\begin{array}{cc}{C}_y^{x-i},& (i\≠0)\\ C_{y-1}^{x-1},& (i=0)\end{array}\right.---\left(4\right)$

Due to register z_iValue for p (i, 0), in this way through coordinate (i, 0) arrive (x, y) after value p (x, y)_i=A_iz_i, Thus nodal value p (x, y)=A₀z₀+A₁z₁+A₂z₂+…+A_Nz_NIt is expressed as follows:

$\begin{array}{c}p(x,y)=\underset{i=\max (0,x-y)}{\overset{x}{\Σ}}p{(x,y)}_i=\mathrm{\δ}\·A_0{z}_0+\underset{i=\max (1,x-y)}{\overset{x}{\Σ}}{A}_i{z}_i\\ =\mathrm{\δ}\·C_{y-1}^{x-1}{z}_0+\underset{i=\max (1,x-y)}{\overset{x}{\Σ}}{C}_y^{x-i}{z}_i\end{array}---\left(5\right)$

Wherein $\mathrm{\δ}=\left\{\begin{array}{cc}0,& x>y\\ 1,& x\≤y\end{array}\right.,$ (remarks: δ=0, represent output item p (x, y) in without z₀)。

Make x=N (cic filter exponent number) can obtain last poly phase output phase:

$Y\left(y\right)=p(N,y)=\mathrm{\δ}\·C_{y-1}^{N-1}{z}_0+\underset{i=max(1,N-y)}{\overset{N}{\Σ}}{C}_y^{N-i}{z}_i,y=0,1,2,...,I-1---\left(6\right)$

Make y=I (interpolation multiple) that next clock cycle register z can be obtained_xValue (gain around feedback value):

$z_x=p(x,I)=\mathrm{\δ}\·C_{I-1}^{x-1}{z}_0+\underset{i=max(1,x-I)}{\overset{x}{\Σ}}{C}_I^{x-i}{z}_i,x=1,2,3,...,N---\left(7\right)$

Formula (6), (7) are referred to as cic filter polyphase interpolating filtering solution formula.

According to above studying CIC polyphase interpolating principle, Fig. 6 is that the poly phase of CIC interpolation 10 times is calculated Method ModelSim simulation result figure, CIC interpolation filter (f_s=100MHz, N=5, M=1, I=10), Signal is carried out multiphase filtering, input 5MHz sinusoidal signal (simulation ultrasonic echo), 10 phase output y0～y9. It can be seen that the 1st, export time delay 9ns (9000ps), adjacent two-way time delay 1ns between 10 tunnels, it was demonstrated that CIC polyphase interpolating filtering delay-time algorithm can reach Δ D_t=1/ (I f_s)=1ns delay precision.

In like manner can verify that any I times of CIC polyphase interpolating filtering algorithm realizes 1/ (I f_s) delay precision effective Property.

Input 5MHz sinusoidal signal is by above-mentioned CIC polyphase interpolating delay technique, after to time delay Signal carries out FFT (Fast Fourier Transformation) conversion and solves each road delay phase, and table 1 is CIC Polyphase interpolating delay time measured value/theoretical value precision comparison table, this interpolation filtering algorithm (f_s=100MHz) Realize 5,2.5,1.25,1,0.625ns time delay stepping, it is known that, maximum relative error is less than-0.28% (0.625ns Time delay stepping), Practical Project has significant application value.

Table 1 CIC delay time measured value/theoretical value precision comparison table

Above-mentioned time-delay method rises Sampling techniques by numeral, improves sampling precision by the mode of software, it is to avoid Rigors to hardware, applies FPGA rapid computations ability, it is achieved sample rate is from f_sRise to I f_s, I road is decomposed simultaneously, forms adjacent two-way 1/ (I f_s) delay precision, it is achieved method is as follows:

The multi-path echo signal gathering ADC, by liter Sampling techniques, carries out I to every road echo-signal Times interpolation (if f_s=100MHz, 1ns delay precision, then I=10) CIC filtering again, I phase decomposition simultaneously exports First via time delay 1/ (I f relatively_s)、2/(I·f_s)、…、(I-1)/(I·f_s) time, (simple in conjunction with thick delay technique Internal memory time delay read, delay precision 1/f_s) wide scope time delay can be realized, described step specifically includes:

1. according to the maximum receiving aperture of ultrasonic phase array instrument, interpolation filtering delay path is designed；

2. by instrument bandwidth index (bandwidth 0.5～15MHz), in conjunction with sample rate f_sWith delay precision, design Cic filter type, exponent number (I, N, M value)；

3. calculate the output of CIC comb section, then filtered output by polyphase interpolating formula (6), (7) calculating I phase, Produce different time delayed signals, be stored in the internal memory of correspondence, read by focusing on rule accordingly.

The filtering ultrasound phase-control array beam time delay of CIC polyphase interpolating, rises the method for sampling by numeral and improves time delay Precision, its stability, reliability, flexibility, precision height.

(1) research and design CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method, enters ultrasonic echo Row interpolation filtering poly phase simultaneously realizes signal lag, and realizes this algorithm by FPGA, is being Under system clock frequency 100MHz, realize 5 respectively, 2.5,1.25,1,0.625ns time delay stepping, join Closing FPGA sequential delay circuit and achieve that large scale and high accuracy time delay, more traditional time-delay method is in fortune Calculation amount, calculating speed, resolving power, cost performance aspect are respectively provided with greater advantage, are very suitable for real-time By force, the focusing delay algorithm that precision is high realizes.

(2) the present invention designs CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method, from ultrasound phase-control Array 1 system delay and focusing principle is set out, and rises Sampling techniques by numeral and improves sampling precision, by CIC Wave filter integral part is analyzed, restructuring interpolater and integrator, makes interpolation and poly phase carry out simultaneously, At system clock frequency f_sUnder the conditions of realize I f after I times of interpolation_sRate signal processes, simultaneously the output of I road, Improve thin delay precision, form adjacent two-way 1/ (I f_s) delay precision；Finally carried out function by ModelSim Emulation, FPGA verifies its precision, under 100MHz sample rate, wherein realizes 16 times of interpolation time delays 0.625ns stepping maximum relative error is less than-0.28%, has significant application value in Practical Project.

Although the embodiment that disclosed herein is as above, but described content is only to facilitate understand this The embodiment invented and use, is not limited to the present invention.In any the technical field of the invention Technical staff, on the premise of without departing from the spirit and scope that disclosed herein, can implement And make any amendment and change in details in form, but the scope of patent protection of the present invention, still must be with institute Attached claims are defined in the range of standard.

Claims (4)

1. a CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method, it is characterised in that institute The method of stating includes:

A encourages many array elements to pop one's head in by focusing on rule, and back wave is received delay and focusing；

B echo rises sampling, and sample rate is from f_sRise to I f_s, I road is decomposed simultaneously, forms adjacent two-way 1/ (I f_s) Delay precision；

C realizes polyphase interpolating by N rank cic filter and filters.

2. CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method as claimed in claim 1, It is characterized in that, described step A specifically includes: encourage many array elements to pop one's head in by certain focusing rule, Back wave is received delay and focusing, makes energy converging, to obtain the most controlled synthesis wave beam and to gather The random control of focal position, by thick time delay, each delay time of thin time delay, it is achieved acoustic beam arbitrarily deflects Azimuth scan each to workpiece.

3. CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method as claimed in claim 1, It is characterized in that, described step B specifically includes:

Sample rate is f_sUltrasound echo signal, by resampling technique, in carrying out I times, zero insertion filters again, Rise sample rate to I f_s, I road is decomposed simultaneously, forms adjacent two-way 1/ (I f_s) delay precision.

4. CIC polyphase interpolating filtering ultrasound phase-control array beam time-delay method as claimed in claim 1, It is characterized in that, described step C specifically includes:

After echo-signal zero insertion is risen sampling, realize anti-mirror image by cic filter and filter high frequency Point, zero insertion in signal I times is filtered again, recombinant C IC filter interpolation device, integrator, in sample rate f_sUnder complete interpolation filtering computing, by poly phase technology realize to I f after interpolation_sThe process of rate signal, I.e. in sample rate f_sUnder heterogeneous output I phase, this wave filter i.e. CIC polyphase interpolating filter.