CN105742486A - Two-end memory electrode comprising discontinuous contact surface - Google Patents

Abstract

The invention describes an electrode for a two-end memory. For example, the electrode may include a contact surface and the contact surface includes at least one discontinuous surface. The electrode may also include another discrete part of one surface that is isolated from, broken from or in contact with the other part of the two-end memory. In one embodiment, the contact surface can be an annular surface or an approximately annular surface. The center of the approximately annular surface, for example at the center of the annular surface, is discontinuous. In some embodiments, the above disclosed electrode can be formed above a discontinuous surface formed via through holes or trenches in an insulator, or formed via a conductive layer over the pillar-shaped device of the insulator.

Description

The two end memorizer electrodes including discontinuous contact surface

Technical field

The disclosure relates generally to electronic memory, for instance, present disclosure describes the noncontinuous electrode for two ends (two-terminal) memory device.

Background technology

Recently, by using the input equipment of such as writing pencil or touching the figure of display on display device with hands

Innovation nearest in technical field of integrated circuits is two end memory technologies.Two end memory technologies and the electric conductivity being such as in that between two ends than the contrast of gating technology are mediated by the 3rd end being called gate terminal.Two end memory devices can be different from three terminal device in function and structure.Such as, some two end memorizeies can construct between pair of conductive contact, contrary with the 3rd terminal near one group of conducting terminal.The present inventor also knows multiple two end memory technologies, for instance, phase transition storage, magnetoresistive memory and other.

Noticeable a kind of two end memorizeies are resistance-type memories.Although many resistance-type memory technology are in the development phase, but multiple technological concepts of resistance-type memory have been confirmed by assignee of the present invention and have been in one or more Qualify Phase to prove or to overthrow relevant theory.Nonetheless, resistance-type memory technology has big advantage at semiconductor electronic industry compared with the technology of competition.

Resistive random access memory (RRAM) is an example of resistance-type memory.The disclosure inventors believe that RRAM has the potential becoming high-density nonvolatile information storage unit technology.In general, RRAM stores information by controllably switching between visibly different resistance states.Single resistance-type memory can store the information of a position or the information of multiple, and what the various storage models confirmed such as assignee provided, it is possible to it is configured to One Time Programmable unit or erasable equipment able to programme.

The present inventor has been proposed that various theory is to explain the phenomenon that resistance switches.In a this theory, resistance switching is the result forming local conductive structure (such as, conductive filament) in otherwise electric insulating medium.Local conductive structure can be can the atom of ionizing or other electric charge conveyer mechanisms be formed by ion, under appropriate circumstances (such as, suitable electric field).In other this theories, in response to the suitable electromotive force being applied on resistive memory cell, it is possible to the electric field-assisted diffusion of atom occurs.In other theories other that the present inventor proposes, in response to binary oxide (such as, NiO, TiO₂Deng) in Joule heating and electrochemical process or by including the oxidation-reduction process of ion conductor of oxide, chalcogenide, polymer etc., it is possible to form conductive filament.

The present inventor expects to show good durability and life cycle based on the resistance device of electrode-insulator-electrode model.It addition, the present inventor expects that these devices have high sheet upper density.Therefore, resistive element could be for the feasible alternative of metal-oxide semiconductor (MOS) (MOS) transistor of digital information storage.The inventor of discussed patent application, for instance, it is believed that the model of resistance-switching memory is provided over some potential technical advantages of non-volatile flash memory MOS device.

In view of foregoing, the memory technology including two end memorizeies and resistance-type memory is made further improvement by the present inventor as possible.

Summary of the invention

Herein below represents the brief overview of this specification, in order to provide the basic comprehension of some aspects to this specification.This summary is not the extensive summary of this specification.Its purpose, neither show key or the important element of this specification, neither describe the scope of any specific embodiment of this specification or any scope of claims.Its objective is to provide in simplified form some concepts of this specification, as the preamble of the more detailed description presented in the present invention.

The many aspects of the disclosure provide the electrode for two end storage component parts.In certain embodiments, described electrode can be at least part of discontinuous surface (such as, contact surface).Such as, described electrode can have another parts of gap or the discontinuous subset (that is, a part) making described surface and described two end memory devices from the teeth outwards and electrically contacts.In certain embodiments, described electrode can include anchor ring or approximate anchor ring, described approximate anchor ring such as in described anchor ring intracardiac have discontinuous.In another embodiment, it is possible to form electrode by the conductive layer above the noncontinuous surface that formed by the through hole (via) in insulator or groove.In still another embodiment, it is possible to form described electrode by the conductive layer above the noncontinuous surface that the column device formed by insulator is formed.

In a further embodiment, present disclose provides two end memory devices.Described two end memory devices can include the first electrode and the non-volatile switchable layer adjacent with described first electrode, and described non-volatile switchable layer is configured to have first physical features relevant to the first state and measure on described first physical features visibly different second physical features relevant with the second state.In addition, described two end memory devices can include the second electrode, described second electrode include at least in part with the electrode surface of the subset physical contact on the switchable layer surface of described non-volatile switchable layer, wherein said electrode surface includes discontinuity zone in the circumference (perimeter) of the described electrode surface physically separate with described switchable layer surface.

In another embodiment, a kind of method describing electrode manufacturing two end memory devices.Described method can include the metal level on the substrate of memory device.Described method may further include and forms oxide skin(coating) at described metal layer.Additionally, described method can include forming through hole and the subset conducting film provided above at the contour surface of the oxide skin(coating) formed by described through hole in described oxide skin(coating).In addition to the above, described method can include being formed over nonvolatile semiconductor memory member in the subset of described conducting film, and the subset of described conducting film is used as the electrode of described nonvolatile semiconductor memory member.

According to additionally other embodiment, discussed disclosing provides a kind of method manufacturing two end memory devices.Described method can include forming oxide skin(coating) in the surface of memory device, and is patterned and etched into described oxide skin(coating) to form column device.It addition, described method can include at the subset conductive material provided above of exposed surface of described column device and provide the non-volatile switching material directly or indirectly contacted above described column device and with described conductive material.Additionally, described method can include being formed over the second conductive material at described switching material.

It is described below and can elaborate some illustrative aspect of this specification by accompanying drawing.But, these aspects represent the several ways of the various ways of the principle that can implement this specification.When considered in conjunction with the accompanying drawings, other advantages of this specification and new feature can become apparent upon from the detailed description below of this specification.

Accompanying drawing explanation

Describing many aspects and the feature of the present invention with reference to the accompanying drawings, wherein similar in entire disclosure accompanying drawing labelling is for referring to similar element.In this manual, many details are elaborated to provide thorough understanding of the present invention.It will be appreciated, however, that not having these details or additive method, parts, material etc. can be used to implement certain aspects of the invention.In other cases, the structure known and equipment are illustrated as block diagram form so that describing the present invention.

Fig. 1 illustrates the block diagram of two end memorizeies of the example according to discussed disclosed embodiment；

Fig. 2 depicts the block diagram of two end memorizeies of the example according to further embodiment；

Fig. 2 A illustrates the schematic diagram on the noncontinuous electrode surface of example for two end memorizeies in an additional embodiment；

Fig. 3 depicts the block diagram according to alternately or additionally two end memorizeies of the example of embodiment.

Fig. 4 and Fig. 5 illustrates the block diagram for forming two end memorizeies of the embodiment according to example；

Fig. 6 and Fig. 7 illustrates the block diagram of the two end memorizeies for forming replacement of the embodiment according to another example；

Fig. 8 depicts the memory architecture of the example of two end memorizeies between the back-end metal layer including described memory architecture；

Fig. 9 illustrates the block diagram of two end memorizeies of the example including selector in a further embodiment；

Figure 10 depicts the block diagram of two end memorizeies of the example including selector in another embodiment；

Figure 11 illustrates the block diagram of the storage architecture of the example including two end memorizeies and selector；

Figure 12 depicts the block diagram of the memory architecture of the example including two end memorizeies and selector in another embodiment；

Figure 13 illustrates the flow chart of the method according to the example for manufacturing two end memorizeies that embodiment of the disclosure；

Figure 14 depicts the flow chart of the method for the example for manufacturing two end memorizeies according to other disclosed embodiments one or more；

Figure 15 illustrates the operation of the example for memory device according to multiple disclosed embodiments and controls the block diagram of environment；

Figure 16 illustrates can in conjunction with the block diagram of the computing environment of the example of multiple embodiments enforcement.

Detailed description of the invention

The present invention relates to the two end memory element for digital information storage.In certain embodiments, two end memory element can include resistive technologies, for instance, resistance switches two end memory element.Resistance used herein switches the component that two end memory element (being also referred to as resistance switching memory element or resistance-switching memory) include having two conductive contacts, has action zone between two conductive contacts.Under the background of resistance-switching memory, the action zone of two end storage devices shows multiple stable or semistable resistance states, and each resistance states has different resistance.Additionally, can form or activate one state of correspondence of multiple state in response to the suitable signal of telecommunication being applied on two conductive contacts.The suitable signal of telecommunication can be magnitude of voltage, current value, voltage or current polarity etc. or theirs is appropriately combined.Although not being exhaustive, resistance switches the example of two end storage devices can include resistive random access memory (RRAM), phase transformation RAM (PCRAM) and reluctance type RAM (MRAM).

Embodiments of the invention can provide the memory element based on filament.One example of filament type memory element may include that conductive layer, such as, metal, p-type (or n-type) silicon (Si) bearing bed (such as, p-type or n-type polysilicon, p-type or n-type polycrystal SiGe etc.) of doping, resisitivity-switching layer (RSL) and the ionizable reactive metal layer of energy.Under proper condition, reactive metal layer can be provided in the ion forming filament in RSL.When removing this condition, for instance, when the electric voltage is removed, ion becomes neutral metal particles, and is trapped in the crystal defect of resisitivity-switching layer.In various embodiments, the neutral metal particles caught contribute to being formed in resisitivity-switching layer conductive filament (such as, in response to ionization excitation, for instance, it is adaptable to make the read voltage of neutral metal particles ionizing again or other excitations).

In multiple embodiments of the disclosure, p-type or n-type silicon bearing bed can include p-type or n-type polysilicon, p-type or n-type SiGe etc..RSL (can also be referred to as resistance switchable dielectric (RSM) in the art) and can include, such as, amorphous silicon layer, the protoxide (such as, SiOx, wherein the value of x is between 0.1 to 2) with the semiconductor layer of intrinsic property, silicon etc..Other examples suitable in the material of RSL can include Si_XGe_YO_ZOxide (such as, the SiO of (wherein, X, Y and Z are positive numbers suitable respectively), silicon_N, wherein N is suitable positive number), non-crystalline silicon (a-Si), amorphous SiGe (a-SiGe), TaO_B(wherein B is suitable positive number), HfO_C(wherein C is suitable positive number), TiO_D(wherein D is suitable number), Al₂O_E(wherein E is suitable positive number), NbO_F(wherein F is suitable positive number) etc. or theirs is appropriately combined.

For including inter alia based on the example of the reactive metal layer of the memory element of filament: the suitable alloy of silver (Ag), gold (Au), nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), ferrum (Fe), manganese (Mn), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), palladium (Pd) or aforementioned substances.According to certain aspects of the invention, it is possible to adopt other suitable conductive materials and above-mentioned compound or combination or similar material as reactive metal layer.Some details of belonging to embodiments of the invention similar with examples detailed above can find in being transferred to the following U.S. Patent application of patentee of present patent application: the patent application serial numbers 11/875 that on October 19th, 2007 submits to, the patent application serial numbers 12/575 that on October 8th, 541 and 2009 submits to, 921, the two patent application is fully incorporated in the application by way of reference and for all purposes.

It is programmed in order to the resistance based on filament is switched memory element, it is possible in memory element, apply suitable program voltage, thus the of a relatively high active component through memory element forms conductive path or filament.This causes that memory element switches to relative low-resistance state from of a relatively high resistance states.In some resistor switching device, it is possible to implement erase process is to make conductive filament deform at least in part, so that memory element returns to high resistance state from low resistance state.In the technology of memorizer, the change of this state can be associated with each state of binary digit.For multiple memory cell array, the word of memory element, byte, page, block etc. can be programmed or wipe to represent the zero or one of binary digit, and store binary information by retaining these states a period of time actually.In various embodiments, multilevel information (such as, multiple positions) can be stored in this memory element.

Should be appreciated that multiple embodiments herein can utilize the multiple memory cell technologies with different physical properties.Such as, different resistance switching memory cell technologies can have different discrete programmable resistances, the program/erase voltage of different associations and other different features.Such as, multiple embodiments of the present invention can adopt the signal of telecommunication to the first polarity to show the first handoff response (such as, one of batch processing state is programmed) and the signal of telecommunication of the second polarity is shown two end switching devices of the second handoff response (such as, being erased to erasing state).Bipolarity switching device is such as contrasted with unipolar device, this unipolar device shows the first handoff response (such as in response to the signal of telecommunication with identical polar and different amplitude, programming) and the second handoff response (such as, erasing).

Those of ordinary skill in the art be will be understood that or is understood by by background provided herein, when many aspects herein and embodiment do not indicate concrete memory cell technologies or program/erase voltage, it is intended that these aspects and embodiment is incorporated to any suitable memory cell technologies and is suitable for the program voltage/erasing voltage operation of memory cell technologies.It is further appreciated that, when needing circuit modification known to persons of ordinary skill in the art or the amendment to operation signal level known to persons of ordinary skill in the art substitutes different memory cell technologies, the embodiment including the memory cell technologies substituted or signal level change is deemed within the scope of the present invention.

The present inventor is familiar with extra non-volatile, the two end memory constructions except resistance-type memory.Such as, ferroelectric RAM (RAM) is exactly an example.Some other example includes reluctance type RAM, organic RAM, phase transformation RAM and conductive bridge RAM etc..Two end memory technologies have different pluses and minuses, and compromise very common between the strengths and weaknesses.Although resistance switches, memory technology is referred has many embodiments disclosed herein, but other two end memory technologies may be used for being suitable to some disclosed embodiments of those skilled in the art.

In multiple disclosed embodiments, it is provided that a kind of two end memory devices including electrode or contact, this two ends memory device has one or more discontinuous on the contact surface of electrode.In certain embodiments, the discontinuous contact area that can limit electrode, thus providing the control of the electrical characteristics (such as, conductive current, leakage current, resistance etc.) to two end memorizeies.In other embodiments, discontinuous off plumb contact area can be provided, it is simple to provide the electric field for contact surface bigger than perpendicular contact region.The invention also discloses the multiple alternative form of two end memory devices, and for manufacturing one or more methods of these devices.

Fig. 1 depicts the block diagram of the example of the memory device 100 according to multiple disclosed embodiments.Memory device 100 can be two end nonvolatile memories above substrate 102.In certain embodiments, substrate 102 can be silicon substrate or other suitable insulated semiconductor material.In certain embodiments, substrate 102 can be control logical substrates, for instance, complementary metal oxide semiconductors (CMOS) (CMOS) substrate.It it is cloth line electrode 104 above substrate 102.Cloth line electrode 104 can be formed by the metal level being arranged on above substrate 102.In certain embodiments, memory device 100 can include other the layers (for example, with reference to Fig. 8, see below) one or more between cloth line electrode 104 and substrate 102.In other embodiments, cloth line electrode 104 can directly on substrate 102.

In certain embodiments, contact layer 106 can be formed above cloth line electrode 104.In alternately or additionally embodiment, memory device 100 can not have contact layer 106 above cloth line electrode.When it is present, it is possible to select contact layer 106 so that or regulating the electric conductivity between cloth line electrode 104 and the miscellaneous part of memory device 100.

In certain embodiments, oxide skin(coating) 108 can be formed above contact layer 106, or in other embodiments, it is possible to formed above cloth line electrode 104.Non-volatile switchable layer 110 can be formed above oxide skin(coating) 108.In many embodiment, according to the handoff technique that memory device 100 adopts, switchable layer 110 can include one or more parts.Such as, in many embodiment, one or more parts can include the material suitable in phase transition storage, magnetic memory, magnetoresistive memory, resistance-switching memory, ferroelectric memory, organic memory, conductive bridge memorizer (conductivebridgememory) etc..First electrode 114 can be formed above switchable layer 110, and the second electrode 112 can at least be partially formed in oxide skin(coating) 108.The knot (junction) of the first electrode 114, switchable layer 110 and the second electrode 112 can form non-volatile switching device 116.Although memory device 100 is depicted as having non-volatile switching device 116 on the right side of the second electrode 112, will be appreciated that, non-volatile switching device 116 can be formed and contact other correct positions of (such as, direct or indirect) or multiple suitable this position (in appropriate circumstances) at the second electrode 112 with switchable layer 110.

As it can be seen, the second electrode 112 can include the discontinuous end face contacted with switchable layer 110.In the example that memory device 100 is described, this discontinuous part can be filled with the centre bore of oxide skin(coating) 108, so that the end face of the second electrode 112 is formed as anchor ring, approximate anchor ring or other suitable shapes (such as, having polygon or the approximate polygon etc. of centre bore).In certain embodiments, the end face of the second electrode 112 contacted with switchable layer 110 can have the end face size of restriction electric current or have the resistance for non-volatile switching device 116 or resistance within the specific limits.In certain embodiments, end face size can be the surface area of end face.In alternately or additionally embodiment, end face size can be the width (width of the end face subset such as, directly contacted with switchable layer 110) of the continuation subset of end face.In order to provide the resistance for non-volatile switching device 116, the second electrode 112 can so that the performance of handoffs of raising of storage stack part 100, the higher current flow uniformity of this device, minimizing Joule heating etc..

In a further embodiment, first electrode the 114, second electrode 112 or cloth line electrode 104 can include the appropriately combined of W, Ti, Cu, Al, Ag, Cu, Pt, Pd, Ta, Ni, Cr, metal nitride, TiN, WN, TaN etc. or aforementioned substances.In certain embodiments, the first electrode 114 second electrode 112 and cloth line electrode 104 can include same or analogous material.In other embodiments, what one or more first electrode the 114, second electrodes 112 or cloth line electrode 104 can include in above-mentioned material is multiple.In at least one embodiment, the first electrode 114 can be include active metal, and the second electrode 112 can include conducting metal or conduction (such as, doping) silicon or silicon compound, and cloth line electrode 104 can include conducting metal group.

In an additional embodiment, switchable layer 110 can include the appropriately combined of non-crystalline silicon (a-Si), TiOx, AlOx, HfOx, SiOx, TaOx, CuOx, NbOx or WOx etc. or aforementioned substances.Switchable layer 110 generally includes the many faults of construction in crystal pattern.In certain embodiments, switchable layer 110 is during manufacture and involuntary non-impurity-doped.As it has been described above, the neutral metal particles in resisitivity-switching layer that defect capture is provided by the first electrode 114 or the second electrode 112.It addition, contact layer 106 can include the appropriately combined of metal-oxide (such as, TiOx, AlOx, HfOx, SiOx, TaOx, CuOx, WOx, NbOx etc.), metal nitride (such as, TiN, WN, TaN etc.) etc. or aforementioned substances.In a further embodiment, substrate 102 can include insulated semiconductor material.Example can include silicon, suitable silicon compound (such as, DOPOS doped polycrystalline silicon, doped polycrystalline SiGe) etc..When by using Damascene technique that copper is used for cloth line electrode 104, contact layer 106 can also be barrier layer, such as, make copper atom such as move in contact layer 106 or migrate across contact layer 106, or preventing copper atom from moving in contact layer 106 or preventing TiN, TaN, WTi etc. through contact layer 106 of migrating.

Fig. 2 illustrates the block diagram of the memory device 200 of the example of the alternately or additionally aspect according to the disclosure.In certain embodiments, storage device 200 may be largely analogous to the memory device 100 of above-mentioned Fig. 1.But, discussed disclosing is not limited to this, and in other embodiments, memory device 200 can be differently configured from memory device 100.

Memory device 200 can include cloth line electrode 202.Cloth line electrode 202 can include the wire such as formed by the metal level of memory device.In one embodiment, wire can be through (for example, with reference to Fig. 8, Figure 11 and Figure 12, see below) that semiconductor substrate Shang Hou road (back-end-of-line) technique is formed.In certain embodiments, contact layer 204 is arranged on above cloth line electrode 202.In other embodiments, memory device 200 does not include contact layer 204.It addition, memory device 200 can include forming the second electrode 206 in insulating barrier 208.Second electrode 206 can include end face 210, and this end face has the continuous part directly contacted with switchable layer 212 and the one or more discontinuous part being not directly contacted with switchable layer 212.It addition, memory device 200 can include the first electrode 214 above switchable layer 212.Nonvolatile semiconductor memory member can be formed by the second electrode 206, switchable layer 212 and the first electrode 214.

In various embodiments, contact layer 204 can have the thickness in the scope of about 50 nanometers (nm) or less.In a further embodiment, the second electrode 206 can have the total height in the scope of about 5n to about 1000nm.In at least one additional embodiment, the end face 210 of the second electrode 206 can have and the continuous part of switchable layer 212 electrical contact, and the width of this continuous part is in the scope of about 1nm to about 50nm.In a further embodiment, switchable layer 212 can have the thickness in the scope of about 1nm to about 50nm.

Fig. 2 A illustrates the schematic diagram of the example on the discontinuous surface of the end face 210 for the second electrode 206.In the first example, discontinuous contact face 210 can include surface of revolution 210A.Surface of revolution 210A can be anchor ring or approximate anchor ring, as shown in the figure, it is also possible to utilize other rotated shape.The surface of revolution 210B disconnected can be other example.The surface of revolution 210B disconnected has the anchor ring of one or more discontinuous part or approximate anchor ring on the circumference of the surface of revolution 210B disconnected.In additional embodiment, discontinuous contact face 210 can include the polygon surface 210C with three or more limits, and it has the discontinuous part in center (such as, centre bore).Another example in discontinuous contact face 210 can include the polygon surface 210D disconnected.The one or more discontinuous part of the surface that the polygon surface 210 disconnected can include having three or more limits and the circumference around the polygon 210D disconnected.

In one or more embodiments, it is possible to select the size in discontinuous contact face 210 to control the electric current density by discontinuous contact face 210.In certain embodiments, it is possible to select the diameter in discontinuous contact face 210 to provide by the targeted current density in discontinuous contact face 210 or resistance.In another embodiment, it is possible to select the width of section in discontinuous contact face 210 to provide targeted current density or resistance.In other embodiments, it is possible to select total surface area or other suitably sized or they be combined to provide targeted current density or resistance.

Fig. 3 depicts the block diagram of the memory device 300 of the alternately or additionally embodiment according to the disclosure.Memory device 300 can be manufactured on substrate 302.In certain embodiments, substrate 302 can be control logical substrates, for instance, complementary metal oxide semiconductors (CMOS) (CMOS) substrate 302.In a further embodiment, it is possible to manufacture substrate 302 at least partially with postchannel process, and this substrate can include one or more active or passive device, for instance, transistor, resistance, electric capacity, inductance etc..In an additional embodiment, it is possible to manufacture the miscellaneous part of memory device 300 at least partially with postchannel process.It should be appreciated, however, that discussed disclosing is not limited to this, for prepare manufacture in quasiconductor or on other mechanism of electronic unit be considered in discussed scope of disclosure.

Substrate 302 can be formed cloth line electrode 304.Cloth line electrode 304 can be made up of suitable conductive material, for instance, metal, metal-oxide (such as, metal nitride), doped semiconductor etc..In certain embodiments, contact layer 306 can be formed above cloth line electrode 304.In a particular embodiment, contact layer 306 can include metal-oxide or metal nitride.In a further embodiment, oxide 308 can be formed in cloth line electrode 304 (or contact layer 306) top.Additionally, the second electrode 312 can at least be partially formed in oxide 308.In certain embodiments, the second electrode 312 can at least have discontinuous on the end face contacted with the switchable layer 310 of memory device 300.In a further embodiment, what the second electrode 312 can have on the bottom surface contacted with contact layer 306 (or, in certain embodiments, contact with cloth line electrode 304) is second discontinuous.Switchable layer 310 can be formed between oxide 308 and the first electrode 314.

In at least one embodiment, the second electrode 312 can be formed on above the column device in oxide 308 (for example, with reference to Fig. 6 and Fig. 7, see below).Second electrode 312 can include the appropriately combined of W, Ti, Cu, Al, Ag, Cu, Pt, Pd, Ta, Ni, Cr, metal nitride (such as, TiN, WN, TaN etc.) etc. or aforementioned substances.In one or more embodiments, switchable layer 310 can include non-crystalline silicon, amorphous silicon germanium, have protoxide (such as, the SiO of the semiconductor layer of intrinsic property, the oxide of silicon, silicon_BWherein B is the number of 0.1 to 2), the oxidized derivatives of silicon (such as, silicon germanium oxide), non-stoichiometric oxide, metal-oxide (such as, zinc oxide), TiOx, AlOx, HfOx, SiOx, TaOx, CuOx, WOx, NbOx or NbOx (wherein x includes each a kind of selected number one group suitable for aforesaid compound) or similar material or aforementioned substances appropriately combined.Additionally, the first electrode 314 can include the appropriately combined of W, Ti, Cu, Al, Ag, Cu, Pt, Pd, Ta, Ni, Cr, metal nitride (such as, TiN, WN, TaN etc.) etc. or aforementioned substances.

Fig. 4 and Fig. 5 illustrates the block diagram according to the memory device technique 400 for manufacturing memory device that embodiment of the disclosure.In certain embodiments, memory device technique 400 can provide memory device, for instance, memory device 100 or memory device 200.But, discussed disclosing is not limited to this, and at least one embodiment, memory device technique 400 can provide other modification of these memory devices.

Memory device technique 400 can include through hole etching, cleaning and deposition process 400A.Through hole etching, cleaning and deposition process 400A can include formation oxide skin(coating) 406A on cloth line electrode 402A.Can in oxide skin(coating) 406A etching vias 404A, thus being formed, there is in oxide skin(coating) 406A the hole of exposed surface.In certain embodiments, this hole can have the cross section of circle or sub-circular, in a further embodiment, this cross section is oval or approximate ellipsoidal, and in a further embodiment, this cross section is polygon or approximate polygon, or in an additional embodiment, this cross section can be other geometry or approximate geometry, or in an additional embodiment, this cross section is non-geometrically.Additionally, although through hole 404A is depicted as having sharp edge at the end face of oxide skin(coating) 406A and the intersection of oxide skin(coating) 406A and cloth line electrode 402A, but these edges can be bending in certain embodiments, and the surface that through hole 404A exposes can have an angled limit, but not completely vertical limit as shown in Figure 4.It addition, road etching, cleaning and deposition process 400A can include forming conductive layer 408A on the end face of oxide skin(coating) 406A and the exposed surface of oxide skin(coating) 406A that formed by through hole 404A.In at least one disclosed embodiment, conductive layer 408A could be arranged to deposit (such as, deposit film), and can have the thickness within the scope of about 1nm to about 50nm.Thickness can be selected to provide by the targeted current density of conductive layer 408A, target resistance etc..

Memory device technique 400 may further include oxide and fills and polishing 400B.400B is filled and polished to oxide can include filling the remainder in the hole formed by through hole 404A with oxide 406B.Oxide 406B can be substantially the same with oxide skin(coating) 406A, although discussed disclosing is not limited to this.After oxide is filled, the end face of memory device can the polished or concordant surface to oxide skin(coating) 406A, remove the conductive layer 408A of the top face of oxide skin(coating) 406A, leave the conductive electrode 402B with the end face substantially concordant with the end face of oxide skin(coating) 406A.

Referring to Fig. 5, continue memory device technique 400.Fig. 5 illustrates switchable layer, top electrode deposition and patterning process 400C.Switchable layer 408C is deposited on oxide skin(coating) 406A, the second electrode 402B and oxide is filled above 406B.In one or more embodiments, switchable layer 408C can have selected from the thickness within the scope of about 1nm to about 50nm.In an additional embodiment, top electrode 410C can be deposited on above switchable layer 408C and pattern.In one or more disclosed embodiments, the combination of top electrode 410C, switchable layer 408C and the second electrode 402B can form resistance switching memory element.

Fig. 6 and Fig. 7 illustrates the block diagram of the memory device technique 500 for manufacturing memory device of the alternately or additionally embodiment according to the disclosure.Referring first to Fig. 6, at top block, depict column etching, cleaning and deposition process 500A.The first conductor 502A can be formed, the first conductor is formed oxide (or other insulant) layer.It addition, oxide skin(coating) can be etched to produce oxide column 504A, as shown in the figure.Although oxidation column 504A is depicted as having sharp edges and the sidewall vertical with the end face of the first conductor 502, but it would be recognized that, in certain embodiments, sharp edges can be circular arch (rounded), and sidewall can with the end face near normal of the first conductor 502A, or in alternative embodiments, with this end face out of plumb.It addition, the second conductor layer 506A can be deposited on above oxidation column 504A.In at least one embodiment, the second conductor layer 506A can have the thickness within the scope of about 1nm to about 50nm.

The bottom box figure of Fig. 6 depicts oxide and fills and polishing process 500B.Oxide is filled and polishing process 500B can include at the second conductor layer 506A oxide material 504B provided above.After oxide material 504B is provided, it is possible to perform polishing process to provide end face 506B.In an embodiment, end face 506B can be polished to remove a part of conductor layer 506A above oxidation column 504A so that the vertical component 506B of conductive layer 506A is concordant with the end face of oxidation column 504 and oxide material 504B or substantially evenly exposes.

Referring to Fig. 7, continue memory device technique 500.Block diagram illustrates switchable layer and top electrode deposition and patterning process 500C.Switchable layer 508C can be deposited on the vertical component 506B of conductive layer 506A, oxide material 504B and the top face of oxidation column 504A.It addition, metal level can be formed above switchable layer 508C, and it is patterned and etched to form top electrode 510C.In one or more disclosed embodiments, the combination of top electrode 510C, switchable layer 508C and conductive layer 506A can form resistance switching memory element.In certain embodiments, two vertical component 506B may be used for forming two independent resistance-switching memory parts.

Fig. 8 illustrates the block diagram of the memory architecture 800 of the example of discussed disclosed one or more further embodiments.The memory architecture 800 of example can include substrate 802.In some disclosed embodiments, substrate 802 can include controlling logic, including passive component or the active parts of electronic device.In at least one embodiment, it is possible to manufacture substrate 802 at least partially with backend process and control logic.

Electrical insulator, for instance, oxide 804 etc., it is possible to be arranged on above substrate 802.It addition, one or more metal levels, including metal level horizontal M3, M4, M5, M6 (in certain embodiments, up to X metal level M_X, wherein X is suitable integer), it is possible to formed in oxide 804.In certain embodiments, metal level can be formed between multilevel oxide 804 interspersedly.It addition, one or more conductive through hole layers can be formed between the subset of each metal level.Via layer can form one or more conductive through hole, including the horizontal V3 of through hole, V4 and V5.

In addition to the above, in an embodiment, memory device 806 can be formed between pair of metal layer.Such as, memory device 806 can be formed between metal level M3 and M4.But, in other embodiments, memory device 806 can be formed between metal level M2 and M3, between metal level M5 and M6, or between other metal levels are to (such as, M3 and M5 etc.).

Memory device 806 can include hearth electrode 812 and its top surface can have that at least one is discontinuous, and described hearth electrode has the bottom surface that the subset with metal level M4 electrically contacts.Such as, the end face of hearth electrode 812 can contact with switchable layer 814, has oxide material in the circumference of the end face contacted with switchable layer 814.The surface area of end face of hearth electrode 812 can be selected to provide a store for the targeted current density of device 806, resistance or other electrical parameters.In at least one embodiment, top electrode 816 can be formed as contacting with the subset of switchable layer 814 and metal level M5.In alternative embodiments, memory device can be formed as not having top electrode 816, and has the switchable layer 814 that the subset with metal level M5 contacts.In various embodiments, it is possible to form metal level M3, M4, M5, M6, through hole V3, V4, V5 or memory device 806 partially or completely through back end fabrication.

Fig. 9 illustrates the block diagram of the memory device 900 of the example of the alternately or additionally embodiment according to the disclosure.Memory device 900 can include the memory unit 902A electrically coupled in series with alternative pack 902B.Memory unit 902A can include the cloth line electrode 904A as bottom.In one embodiment, conductive layer 906A can be formed above cloth line electrode 904A, and in another embodiment, memory unit 902A can be not in contact with a layer 906A.It addition, oxide skin(coating) 908A can be formed above cloth line electrode 904A, there is electrode formed in which, electrode₂910A.In various embodiments, electrode₂910A can include electrode₂The contact surface of 910A (such as, end face, as it is shown in figure 9, or in alternative embodiments, bottom surface) in discontinuous.Above oxide skin(coating) 908A it is and electrode₂The switchable layer 912A of the end face electrical contact of 910A.In one or more embodiments, switchable layer 912A can be non-volatile switchable layer, it is configured to keep one of one group of measurable visibly different state to making switchable layer 912A when there is one of one group of measurable visibly different state relevant suitable storage excitation (such as, electric field, voltage, electric current, Joule heating etc.) being absent from.It addition, another electrode, electrode₁914A can be formed above switchable layer 912A.

As shown in memory device 900, alternative pack 902B can be formed above memory unit 902A, electrically coupled in series with memory unit 902A.Alternative pack 902B can include the first selection electrode₁904B, volatibility switchable layer 906B and the second select electrode₂908B.In one or more embodiments, volatibility switchable layer 906B can have various states, including the deactivation status when activation (such as, activate voltage, activated current etc.) not being applied on memory device 900 and in response to the state of activation of the activation being applied on memory device 900.Additionally, alternative pack 902B can be bipolarity switching device, and wherein positive actuation excitation (such as, positive voltage etc.) can make volatibility switchable layer 906B activate, and negative activation (such as, negative voltage etc.) can also make volatibility switchable layer 906B activate.It addition, when deexcitation, alternative pack 902B can make storage excitation migrate or prevent storage excitation from affecting memory unit 902A, and when activating, storage excitation can affect memory unit 902A.

In at least one embodiment, first electrode is selected₁904B can be the electrode separated.Therefore, second electrode is selected₁904B can be not connected to external source (such as, the power supply outside memory device 900).So, for instance, first selects electrode₁904B can obtain by being applied to the second selection electrode₂908B, electrode₂The caused electric charge of excitation on 910A or cloth line electrode 904A, electric current, voltage etc., in order to the activation of volatibility switchable layer 906B.It is applied to the second selection electrode being absent from₂908B, electrode₂When excitation on 910A or cloth line electrode 904A, first selects electrode₁904B can have the electric charge of reduction, electric current, voltage etc. or not have this electric charge, curtage, consequently facilitating the deexcitation of volatibility switchable layer 906B.In various embodiments, alternative pack 902B can as the co-pending U.S. Patent application No.61/951 submitted on November 3rd, 2014, selector disclosed in 454 is implemented, and this patent application is incorporated herein for all purposes by way of reference.

Figure 10 illustrates the block diagram of the memory device 1000 of the example of the replacement of the further embodiment according to the disclosure.As it can be seen, memory device 1000 can include above alternative pack 1002B and the memory unit 1002A electrically coupled in series with it.In at least one embodiment, memory unit 1002A may be largely analogous to the memory unit 902A of Fig. 9, sees below, or alternative pack 1002B may be largely analogous to alternative pack 902B.But, discussed disclosing is not limited to this, and in an additional embodiment, memory unit 1002A or alternative pack 1002B can be different from memory unit 902A and alternative pack 902B.

Alternative pack 1002B can include the first selection electrode 1004B contacted with volatibility switching device 1006B.Alternately, volatibility switching device 1006B can select electrode 1008B to contact with second.In at least one embodiment, second selects electrode 1008B can select the contrary side of electrode 1004B towards volatibility switching device 1006B with first, although can implement other orientations in other embodiments.

Memory unit 1002A and alternative pack 1002B is electrically coupled in series, and in response to the activation of alternative pack 1002B, outside storage excitation can be responded.Outside responds it addition, can not stored excitation in response to the deexcitation of alternative pack 1002B by memory unit 1002A.As it can be seen, memory unit 1002A can include wiring layer 1004A.In one embodiment, contact layer 1006A can be arranged to contact with wiring layer 1004A.It addition, oxide skin(coating) 1008A can include the electrode 1010A with contact surface, it is discontinuous that this contact surface has at least one surface.Although memory unit 1002A illustrates this contact surface, to have at least one place on the end face of electrode 1010A discontinuous, but other embodiments can include this contact surface, and to have at least one place on the bottom surface of electrode 1010A discontinuous.In at least one other embodiment, multiple contact surfaces can have respective surface discontinuous (such as, have the discontinuous end face in surface and have discontinuous bottom surface, surface).It addition, memory unit 1002A can include the non-volatile switchable layer 1012A of the first surface at non-volatile switchable layer 1012A and electrode 1010A electrical contact.It addition, the second electrode 1014A can be arranged on above the second surface of non-volatile switchable layer 1012A and be in contact with it.

Figure 11 depicts the block diagram of the memory architecture 1100 of the example according to other disclosed embodiment.The framework of the first example is described by top block figure.Being provided with substrate 1102A, this substrate has multiple metal level M3, M4 and M5 in electrical insulator (such as, oxide 1104A).Memory device 1106A is depicted as partly between metal level M3 and M4, and partly between metal level M4 and M5.Memory device 1106A includes the memory unit between metal level M4 and M5, and this memory unit includes the first electrode 1112A with at least one contact surface, and it is discontinuous that at least one contact surface described has surface.It addition, memory unit includes and has the non-volatile switchable layer 1110A of surface discontinuous contact surface electrical contact, and the second electrode 1108A electrically contacted with the subset of non-volatile switchable layer 1110A and metal level M5.It addition, memory device 1106A includes the alternative pack between metal level M3 and M4.Such as, alternative pack can electrically contact with the subset of metal level M4, and the subset of this metal level also electrically contacts with the memory unit of memory device 1106A.Alternative pack can include stack layers more than, and these many stack layers have the contact first the second selection electrode 1118A selecting electrode 1114A, volatibility switchable layer 1116A and the subset with conductive layer M3 to contact with metal level M4.

The framework of the second example is illustrated by bottom box.Being similar to the framework of the first example, be provided with substrate 1102B, this substrate has metal level M3, M4 and M5 in insulant (such as, oxide 1104B).Additionally, it is provided that memory device 1106B, this memory device has the memory unit between the subset and the subset of metal level M4 of metal level M3.Memory unit can include having the second electrode 1108B that the first electrode 1112B of belt surface at least one contact surface discontinuous, non-volatile switchable layer 1110B and the subset with metal level M4 contact.It addition, the subset that alternative pack is arranged to the subset with metal level M4 and metal level M5 contacts.Alternative pack can include the second selection electrode 1114B that the first selection electrode 1118B, volatibility switchable layer 1116B and the subset with metal level M5 contact.

Figure 12 illustrates the block diagram according to the additionally memory architecture 1200 of the additional example of other disclosed embodiments.Top block figure illustrates the first memory part 1206A according to memory architecture 1200.Being provided with substrate 1202A, this substrate has at least two metal level in oxide 1204A, includes metal level M3, M4 and M5 in the illustrated embodiment.First memory part 1206A is between metal level M4 and M5, although allowing other to arrange in other embodiments.Memory device 1206A includes memory unit, and this memory unit includes hearth electrode 1218A (having belt surface at least one contact surface discontinuous), the non-volatile switchable layer 1216A and top electrode 1214A that the subset with metal level M4 below alternative pack contacts.Alternative pack includes the second selection electrode 1208A that the first selection electrode 1212A, volatibility switchable layer 1210A and the subset with metal level M5 contact.

Bottom box figure illustrates the second memory part 1206B according to memory architecture 1200.Substrate 1202B includes at least two metal level M3, M4 and M5 in the oxide 1204B on substrate 1202B.Second memory part 1206B includes the alternative pack below memory unit, this alternative pack have different from first memory part 1206A towards.The first selection electrode 1212B, volatibility switchable layer 1210B and second that alternative pack can include contacting with the subset of metal level M4 selects electrode 1208B.Memory unit can include selecting with second the electrode 1208B bottom electrode 1218B contacted, this top electrodes to have and include surface at least one contact surface discontinuous.It addition, the top electrode 1214B that memory unit can include non-volatile switchable layer 1216B and the subset with metal level M5 contacts.Although second memory part 1206B is in fig. 12 between metal level M4 and M5, but be in other between metal level also according in the discussed scope of disclosure of alternate embodiment.

With reference to describing above-mentioned schematic diagram alternately between several parts (such as, layer) of memory element, its metal level or the memory architecture that is made up of these memory element/metal levels.Should be appreciated that some the suitable alternative aspect in the present invention, these schematic diagrams can include these elements and layer, some element/layers specified or the additional element/layer wherein specified.Sub-element part can also be implemented as the sub-element part electrical connection with other, rather than is included in paternal element/layer.Such as, intermediate layer can be arranged to adjacent with one or more disclosed layers.For example, the less desirable suitable barrier layer migrating or it being controlled that aoxidizes is made to may be located between one or more disclosed layer.In additionally other embodiment, disclosed memory heap or one group of rete can have the layer fewer than diagram.Such as, switchable layer directly can electrically contact with tinsel, rather than has electrode layer between.Additionally, it is noted that one or more disclosed processes can be incorporated in the single process providing consolidation function.The element of disclosed framework can also with other element interconnections one or more that still those skilled in the art are afamiliar with being not specifically described herein herein.

According to example described above schematic diagram, will be better appreciated by by referring to the flow chart of Figure 13 and Figure 14 can the processing method that is carried out of theme disclosed according to the present invention.Although purpose for the purpose of simplifying the description; the method of Figure 13 and Figure 14 is illustrated and is described as a series of square frame; it is to be understood that and recognize; the theme claimed is not by the restriction of square frame order, because some square frames can according to carrying out with order different illustrated and described herein or carrying out with other square frames simultaneously.Additionally, the square frame that also not all illustrates all is implemented method described herein and is necessarily required to.Additionally, it should it is further recognized that the some or all of methods disclosed in entire disclosure can be stored on the article of manufacture so that these methods being transmitted and being sent to electronic equipment.Term used herein " article of manufacture " is intended to the computer program including obtaining from any computer-readable equipment and carrier-bound equipment, storage medium.

Figure 13 illustrates the flow chart of the method 1300 of the example of the electrode for manufacturing two end memory devices according to discussed disclosed additional embodiment.1302, method 1300 can include being formed conductive layer (such as, metal level, doping semiconductor layer etc.) on the substrate of memory device.1304, method 1300 can include square one-tenth oxide skin(coating) on the metal layer.1306, method 1300 can include forming through hole in the oxide layer.1308, method 1300 can include the subset conducting film provided above at the contour surface of the oxide skin(coating) formed by through hole.It addition, 1310, method 1300 can include being formed over nonvolatile semiconductor memory member in the subset of conducting film.In at least one embodiment, the subset of conducting film may serve as the electrode of nonvolatile semiconductor memory member.In at least one embodiment, 1312, method 1300 may further include and forms the selector electrically coupled in series with nonvolatile semiconductor memory member.

In at least one embodiment, through hole can have the cross section of the shape of the group selecting free the following composition in the oxide layer: circle, sub-circular, ellipse, approximate ellipsoidal, polygon and approximate polygon.In alternately or additionally embodiment, this group may further include non-geometric shape of cross section.

According to other embodiments, method 1300 may further include polishing and the either flush of oxide skin(coating) or substantially concordant conducting film.In additionally other embodiments, form selector and can include forming the volatibility selector electrically coupled in series with nonvolatile semiconductor memory member.

According to further embodiment, method 1300 can include forming the volatibility selector directly contacted with the subset of conducting film, and the subset of this conducting film is used as the electrode of nonvolatile semiconductor memory member.In another embodiment, method 1300 can include forming the volatibility selector directly contacted with the second electrode of nonvolatile semiconductor memory member.In another embodiment again, method 1300 can include forming the second conductive layer (such as, the second metal level, the second doping semiconductor layer etc.) in the surface of memory device.In at least one alternately or additionally embodiment, formed and include side formation volatibility selector contrary with nonvolatile semiconductor memory member on the second conductive layer with the volatibility selector of nonvolatile semiconductor memory member series connection.

Figure 14 illustrates the flow chart of the method 1400 of the example for manufacturing two end memorizeies according to discussed disclosed further embodiment.1402, method 1400 can include forming oxide skin(coating) in the surface of memory device.1404, method 1400 can include being patterned and etched into oxide skin(coating) to form column device.1406, method 1400 can include the subset conductive material provided above at the exposed surface of column device.It addition, 1408, method 1400 can include providing the non-volatile switching material directly or indirectly contacted above column device and with conductive material.1410, method 1400 can include being formed over the second conductive material at switching material.In an embodiment, method 1400 can include, and 1412, removes the subset of conductive material to form the conductive material of the subset of the circumference of end face that is substantially concordant with end face and that surround column device from the end face of column device.In alternately or additionally embodiment, the combination of the conductive material above the subset of the exposed surface of column device, non-volatile switching material and the second conductive material forms nonvolatile semiconductor memory member.In a further embodiment, 1414, method 1400 may further include and forms the volatibility selector electrically coupled in series with nonvolatile semiconductor memory member.

In multiple embodiments disclosed in discussed, disclosed memorizer or memory architecture can serve as the independent or integrated embedded memory device with CPU or pico computer.Such as, some embodiments may be embodied as a part (such as, random access memory, cache memory, read only memory, stored memory etc.) for computer storage.Such as, other embodiments may be embodied as portable memory apparatus.The example of suitable portable memory apparatus can include active storage, for instance, secure digital (SD) card, USB (universal serial bus) (USB) store bar, compact flash (CF) card etc. or theirs appropriately combined.(referring to, for instance, Figure 15 and Figure 16, see below).

Fast flash memory bank is used as the factor of compact flash equipment, USB device, SD card, solid-state drive (SSD) and storage class internal memory and other forms.Although in the past 10 years in it turned out flash memory be the successful techniques that boosting driver reduces into the chip density of less device and Geng Gao in proportion, but being as technology scales and drop to the technology crossing 25 nanometers of (nm) memory element, several properities and integrity problem become apparent from.Disclosed aspect solves the subset of these or similar consideration.

Brief, the description summarized of the suitable environment that the many aspects to theme disclosed in this invention can be practiced or carried out in order to provide the background of the many aspects of theme disclosed in this invention, Figure 15 and following discussion to aim to provide.Although solid-state memory and semiconductor framework and for manufacture and operate the processing method of this memorizer or framework general background under described above is theme, it will be recognized to those skilled in the art that the present invention can be combined with other framework or processing method is implemented.In addition, skilled artisan should recognize that, can in system of processing or computer processor individually also or in conjunction with main frame (such as, the computer 1602 of Figure 16 as mentioned below) implement disclosed process, described main frame can include uniprocessor or multiprocessor computer system, microcomputer, mainframe computer and personal computer, Handheld computing device (such as, PDA, smart phone, intelligent watch), based on microprocessor or programmable consumption electronic product or industrial electronics etc..The aspect of diagram can also be implemented by distributed computing environment, and wherein task is performed by the remote processing devices connected by communication network.But, all aspects of sometimes not discussed innovation can be implemented on electronic equipment independently, for instance, storage card, flash memory module, mobile memory etc..In a distributed computing environment, program module may be located on locally or remotely stored device module or equipment.

Figure 15 illustrates the work of the example for memory cell array 1502 according to aspects of the present invention and controls the block diagram of environment 1500.The present invention at least one in, memory cell array 1502 can include multiple memory cell technologies.In at least one embodiment, the memory element of this memory cell technologies can include the two end memorizeies being arranged to two dimension compact as described herein or three-dimensional architecture, this two ends memorizer has at least one electrode, at least one electrode described has at least one contact surface, and it is discontinuous that at least one contact surface described has surface.In another embodiment, memory cell array 1502 can store the operation of the two end memory element being configured to make device manufacture and selector electrically coupled in series.

Row controller 1506 can be formed as adjacent with memory cell array 1502.Additionally, row controller 1506 can be electrically connected with the bit line of memory cell array 1502.Row controller 1506 can control each bit line, thus applying suitable program voltage, erasing voltage or read voltage on selected bit line.

Additionally, work and control environment 1500 can include line control unit 1504.Line control unit 1504 can be formed as adjacent with row controller 1506, and is electrically connected with the wordline of memory cell array 1502.Line control unit 1504 can with the suitable specific row selecting voltage to carry out select storage unit.Additionally, line control unit 1504 can so that programming, wiping or read operation by applying suitable voltage in selected wordline.

Clock source 1508 can provide each clock pulses so that the timing of line control unit 1504 and the reading of row controller 1506, write and programming operation.Clock source 1508 is easy to select wordline or bit line in response to the outside or inside order that work and control environment 1500 receive further.Input/output (i/o) buffer 1512 can pass through I/O buffer or other I/O communication interface and be connected with external host, for instance, computer or other process equipment (not shown, but referring for example to the computer 1602 of Figure 16, as described below).Input/output (i/o) buffer 1512 may be configured to receive write data, receives erasing instruction, exports reading data and receive address date and order data and the address date for each instruction.Address date can pass through address register 1510 and be transferred to line control unit 1504 and row controller 1506.Additionally, input data are sent to memory cell array 1502 by signal input line, and receive output data by output line from memory cell array 1502.Input data can be received from main process equipment, and export data and can be transported to main process equipment by I/O buffer.

The instruction received from main process equipment can be provided to command interface 1514.Command interface 1514 may be configured to receive external control signal from main process equipment, and determines whether the data being imported into output/output buffer 1512 are write data, order or address.Input order can be transported to state machine 1516.

State machine 1516 may be configured to programming and the reprogram of management memory cell array 1502.State machine 1516 receives the order from main process equipment by input/output interface 1512 and command interface 1514, and manages the functions such as the reading relevant to memory cell array 1502, write, erasing, data input, data output.In some respects, state machine 1516 can send and receive the response about having successfully received or perform various order or negative response.

In order to implement the functions such as reading, write, erasing, input, output, state machine 1516 can control clock source 1508.Output pulse can be made to be configured to facilitate line control unit 1504 for control clock source 1508 and specific function implemented by row controller 1506.Output pulse such as can be transported to selected bit line by row controller 1506, for instance is transported to wordline by line control unit 1504.

In conjunction with Figure 16, following system and process can be implemented within hardware, for instance single integrated circuit (IC) chip, multiple IC, special IC (ASIC) etc..It addition, the order of the some or all of procedure blocks occurred in each process is not construed as restriction.Rather, it should be appreciated that some procedure blocks can perform according to multiple order, clearly do not illustrate all of order herein.

With reference to Figure 16, include computer 1602 for the suitable running environment 1600 of the many aspects of theme implementing to claim.Computer 1602 includes processing unit 1604, system storage 1606, coding decoder 1635 and system bus 1608.System bus 1608 connection system element, includes but not limited to system storage 1606 is connected to processing unit 1604.Processing unit 1604 can be arbitrary various available processor.Dual micro processor and other multiple processor structures are also used as processing unit 1604.

System bus 1608 can be the bus structures of arbitrary several types, including memory bus or Memory Controller, peripheral bus or external bus and/or use the local bus of arbitrary various available bus architecture, include but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), extension ISA (EISA), Intelligent Drive Electronics (IDE), VESA local bus (VLB), periphery component interconnection (PCI), card bus, USB (universal serial bus) (USB), advanced graphics port (AGP), PCMCIA's bus (PCMCIA), live wire (IEEE1394) and small computer system interface (SCSI).

In various embodiments, system storage 1606 includes volatile memory 1610 and the nonvolatile memory 1614 that can adopt memory architecture disclosed in one or more.Including such as during starting basic input/output (BIOS) for transmitting the basic subroutine of information between the element of computer 1602 be stored in nonvolatile memory 1612.Additionally, according to the present invention, coding decoder 1635 can include at least one of encoder or decoder, wherein at least one of encoder or decoder can include the combination of hardware, software or hardware and software.Although coding decoder 1635 is described as independent element, but coding decoder 1635 can include in nonvolatile memory 1612.Unrestricted as an example, nonvolatile memory 1612 can include read only memory (ROM), programming ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM) or flash memory.In at least some disclosed embodiment, nonvolatile memory 1612 can adopt memory architecture disclosed in one or more.Additionally, nonvolatile memory 1612 can be computer storage (such as, with the memorizer of computer 1602 or its mainboard physical integration) or mobile memory.The example that can implement the suitable mobile memory of disclosed embodiment can include secure digital (SD) card, compact flash (CF) card, USB (universal serial bus) (USB) memory stick etc..Volatile memory 1610 includes the random access memory (RAM) being used as external cache, and also can adopt one or more memory architectures disclosed in various embodiments.Unrestricted as an example, RAM can take various forms, such as, static RAM (SRAM), dynamic ram (DRAM), synchronous dram (SDRAM), Double Data Rate SDRAM (DDRSDRAM), enhancement mode SDRAM (ESDRAM) etc..

Computer 1602 can also include movement/non-moving, volatile/nonvolatile computer storage media.Figure 16 illustrates such as disk memory 1614.Disk memory 1614 includes but not limited to following device: disc driver, solid state hard disc (SSD), floppy disk, tape drive, Jaz driver, Zip drive, LS-100 driver, flash card or memory stick.In addition, disk memory 1614 can individually include storage medium or in conjunction with other storage mediums, include but not limited to CD drive, such as, compact compact disc-ROM (CD-ROM), CD burning driver (CD-R drive), CD-rewritable driver (CD-RW drive) or digital versatile disc ROM drive (DVD-ROM).For the ease of disk storage 1614 is connected to system bus 1608, it is common to use mobile or non-moving interface, for instance, interface 1616.Will be appreciated that disk storage 1614 can store the information relevant with user.These information can be stored in or be supplied to server or be supplied to the application run on a user device.In one embodiment, user may be notified that (such as, by outut device 1636) is stored in disk memory 1614 and/or is sent to the information type of server or application.User have an opportunity can to select or exit these information of collection and/or with server or Application share (such as, being used as the input from input equipment 1628).

Should be appreciated that Figure 16 describes the software of the vehicle between as the basic computer resources described in user and suitable working environment 1600.This software includes operating system 1618.The operating system 1618 on disk memory 1614 can be stored in for controlling and configure the resource of computer 1602.Application 1620 is by program module 1624 and routine data 1626, for instance, it is stored in the system storage 1606 on/off things table etc. also or on disk memory 1614, the resource management provided by operating system 1618 is provided.Will be appreciated that claimed theme can use with the combination of various operating systems or operating system.

User inputs instruction or information in computer 1602 by input equipment 1628.Input equipment 1628 includes but not limited to sensing equipment, such as mouse, trace ball, stylus, touch pad, keyboard, mike, stick, game paddle, satellite dish, scanner, TV tuner card, digital camera, DV, IP Camera etc..These and other input equipments are connected to processing unit 1604 via interface 1630 by system bus 1608.Interface 1630 includes such as serial port, parallel port, game port and USB (universal serial bus) (USB).Outut device 1636 uses and the more same kind of ports of input equipment 1628.It is therefoie, for example, USB port is provided for the input of computer 1602 and outputs information to outut device 1636 from computer 1602.O adapter 1634 is configured to illustrate there are some outut devices requiring private adapter, except other outut devices, and such as monitor, speaker and printer.Unrestricted as an example, o adapter 1634 includes the video card and the sound card that provide the connection means between outut device 1636 and system bus 1608.It should be noted that, the system of other equipment and/or equipment provides input and fan-out capability, for instance, remote computer 1638.

Computer 1602 can use logic connection to work to be connected in the network environment of one or more remote computer (such as remote computer 1638).Remote computer 1638 can be personal computer, server, router, network PC, work station, based on the device of microprocessor, peer device, smart phone, panel computer or other network nodes, and generally include the many elements described relative to computer 1602.For simplicity, remote computer 1638 only illustrates a storage device 1640.Remote computer 1638 is logically connected to computer 1602 by network interface 1642, is then connected via communication connection 1644.Network interface 1642 comprises wired and/or cordless communication network, for instance, LAN (LAN) and wide area network (WAN) and Cellular Networks.Lan technology includes Fiber Distributed Data Interface (FDDI), copper cable distributed data interface (CDDI), Ethernet, token ring etc..WAN technology includes but not limited to point-to-point link, circuit switching network, such as ISDN (ISDN) and variant thereof, packet switching network and Digital Subscriber Line (DSL).

Communication connection 1644 refers to the hardware/software for network interface 1642 is connected to system bus 1608.Although for simplicity, communication connection 1644 is illustrated as in computer 1602, but can also outside computer 1602.Hardware/software needed for being connected to network interface 1642 includes, it is for illustration purposes only, inside and outside technology, such as, modem including regular telephone grade modem, cable modem and DSL modem, ISDN adapter, and wired and wireless ethernet card, hub and router.

The aspect of the diagram of the present invention can also be implemented by distributed computing environment, and some of which task is performed by the remote processing devices connected by communication network.In a distributed computing environment, program module or storage information, instruction etc. may be located on locally or remotely stored device equipment.

Moreover, it will be appreciated that Various Components as herein described can include circuit, described circuit can include element and the component of desired value, in order to implements the embodiment of subject innovation.Furthermore, it is possible to recognize, it is possible to implement many described Various Components on one or more IC chips.Such as, in one embodiment, it is possible on single IC chip, implement a set of pieces.In other embodiments, it is possible on single IC chip, manufacture or implement the element of one or more correspondence.

Term used herein " element ", " system ", " framework " etc. are intended to indicate that the entity, also or the combination of hardware, software and hardware, software (such as, the software of execution) or firmware of computer or electronic correlation.Such as, element can be that the device of one or more transistor, memory element, transistor or memory element, gate array, programmable gate array, special IC, controller, processor, the process run on a processor, semiconductor memory access or the target that connects, executable program or application, computer etc. or their suitable combinations.Element can include erasable programming (process instruction such as, being stored at least partly on erasable memory) or non-erasable programming (such as, during fabrication burning process instruction on non-erasable memorizer).

Illustrating with example, the process and the processor that perform from memorizer can be both elements.As another example, framework can include the device of electronic hardware (such as, transistor in parallel or series), processing instruction and processor, and this device is according to being suitable to the mode of device of electronic hardware to implement processing instruction.In addition, framework can include discrete component (such as, transistor, gate array etc.) or the device (gate array, power line, ground connection, input signal cable and output signal line etc. that such as, the serial or parallel connection device of transistor is connected with program circuit) of element.System can include one or more element and one or more structural system.The system of one example may include that the switching component structure system including input/output line and the transmission gate transistor intersected；And power supply；Signal generator；Communication bus；Controller；I/O interface；Address register etc..Will be appreciated that, it is contemplated that the overlaps in some definition, and structural system or system can be independent element or the element etc. of another structural system, system.

Apart from the above, by using typical manufacturing technology, programming technique or engineering to manufacture hardware, firmware, software or their any suitable combination, theme disclosed in this invention may be embodied as the article of method, device or manufacture to control electronic equipment to implement theme disclosed in this invention.Term used herein " equipment ", " article of manufacture " are intended to the computer program comprising electronic equipment, semiconductor equipment, computer or obtaining from the readable equipment of any computer, carrier or medium.Computer-readable medium can include hardware medium or software medium.Additionally, medium can include non-transient medium or transmission medium.In an example, non-transient medium can include computer-readable hardware medium.The instantiation of computer-readable hardware medium can include but not limited to: magnetic storage apparatus is (such as, hard disk, floppy disk, tape etc.), CD (such as, dense form CD (CD), digital versatile disc (DVD) etc.), smart card and flash memory (such as, storage card, storage bar, USB flash disk etc.).Computer-readable transmission medium can include carrier wave etc..Certainly, it will be appreciated by the person skilled in the art that and this configuration can be carried out multiple amendment when without departing from the scope of theme disclosed in this invention or spirit.

The content of foregoing description includes the example of subject innovation.Certainly, in order to describe the purpose of subject innovation, it is impossible to each of element or method is described it is contemplated that combination, but those of ordinary skill in the art will be consequently realised that, it is possible to subject innovation is carried out many further combinations and permutations.Therefore, theme disclosed in this invention is intended to comprise all this replacement, the modifications and variations that are within the spirit and scope of the invention.In addition, for term " comprising ", " including ", " having ", " having " and the change thereof that detailed description of the invention is used also or in claims, when in the claims be used as transition word time, this term according to term " by ... composition " be understood to that the similar fashion of " including " is intended to inclusive.

Additionally, word used herein " exemplary " is meant to as an example, illustrates or illustrates.Any aspect or design described herein as " exemplary " are not necessarily to be construed as the aspect or design that are preferable over or are better than other.On the contrary, word " exemplary " is used to be intended to state in a concrete fashion concept.Term "or" used herein is intended to the "or" being meant to inclusive rather than the "or" of exclusiveness.It is to say, unless otherwise specifically noted, or be clearly expressly understood from context, " X adopts A or B " is intended to be meant to the arrangement of any natural inclusive.If it is to say, X adopts A, X to adopt B, or X adopts both A and B, then " X adopts A or B " meets any one aforesaid example.Additionally, the article " " used in this specification and the appended claims and " one " should usually be understood to " one or more ", unless otherwise specifically noted, or clearly it is expressly understood from context and refers to singulative.

It addition, the some parts of detailed description of the invention describes the algorithm to the data bit in electronic memory and process operation.The description of these processes or expression are that those skilled in the art for effectively conveying to the mechanism of other those skilled in the art by the essence of their work.In general, process is herein understood as causing the action sequence being certainly in harmony of expected result.These actions are the actions needing physical quantity is carried out physical operations.Generally, although may not, the form of these physical quantitys is able to be stored, transmits, combines, the signal of telecommunication of operation relatively in other words conj.or perhaps or magnetic signal.

Be primarily to and be used in conjunction with, be proved to it is suitable that, these signals are used as position, numerical value, element, symbol, character, item, numeral etc..But, it should it is contemplated that, all these item and similar terms will be associated with suitable physical quantity, and are only the appropriate label being applied to these physical quantitys.Unless otherwise specifically noted, or clearly it is expressly understood from that discussed above, it is to be appreciated that, in whole theme disclosed in this invention, utilize and such as process, calculate, replicate, imitated, determine or the discussion of the term such as transmission refers to action or the process of process system and/or similar consumption or industrial electronics or machine, these systems and/or product or machine are by circuit, data that physics (electrically or electronically) amount in the memorizer of depositor or electronic equipment is represented or signal operation or be transformed into the memorizer of machine or computer system or depositor or other this information storage units, analogously represented other data of physical quantity in transmission and/or display device or signal.

For the several functions that said elements, framework, circuit, process etc. realize, term (including " meaning " that represent) for describing these elements is intended to any element with the specific function realizing described element (such as, the equivalents of function) corresponding, unless otherwise specifically noted, although structurally inequivalence is in structure disclosed in this invention, these structures realize function illustrated by the illustrative aspects of embodiment in this article.In addition, although specific feature possibility is disclosed with reference to the only one in several embodiments, but this feature can be desired and its favourable mode is combined with other features one or more of other embodiments according to any given or specific application.It should also be appreciated that embodiment includes system and computer-readable medium, described computer-readable medium has the executable instruction of computer of the action and/or event for performing multiple process.

Claims (20)

1. a two end memory device, including:

First electrode；

Non-volatile switchable layer, described non-volatile switchable layer is adjacent with described first electrode, described non-volatile switchable layer is configured to have first physical features relevant to the first state and second physical features relevant with the second state, described second physical features can measure significantly different with described first physical features；And

Second electrode, including at least in part with the electrode surface of the subset physical contact on the switchable layer surface of described non-volatile switchable layer, wherein, described electrode surface with the circumference of described electrode surface that separates on described switchable layer surface physics in include discontinuity zone.

2. two end memory devices according to claim 1, wherein said electrode surface includes the some rotation at least partly surrounding in the circumference of described electrode surface or the shape substantially rotated.

3. two end memory devices according to claim 1, wherein said electrode surface includes two regions being shaped as border in the circumference with described electrode surface, and further, wherein, described discontinuity zone is the second area in circumference, and described second area includes in said two shape or less.

4. two end memory devices according to claim 1, wherein said electrode surface is the region in the multiple described circumferences being shaped as border in the group selecting free the following to form: circular or sub-circular, ellipse or approximate ellipsoidal, polygon or approximate polygon.

5. two end memory devices according to claim 4, wherein said electrode surface is anchor ring or approximate anchor ring.

6. two end memory devices according to claim 1, farther including the cloth line electrode that adjacent with described hearth electrode and by the conductor of memory device subset is formed, described wiring electrode includes the combination of W, Ti, Cu, Al, Ag, Pt, Pd, Ta, Ni, Cr, metal nitride, TiN, WN, TaN, the doped silicon of conduction or the doping SiGe of conduction or aforementioned substances.

7. two end memory devices according to claim 1, farther including the contact layer between described hearth electrode and described cloth line electrode, described contact layer is formed by the combination of metal-oxide, TiOx, AlOx, HfOx, SiOx, TaOx, CuOx, WOx, metal nitride, TiN, WN, TaN or aforementioned substances.

8. two end memory devices according to claim 1, wherein top electrode or described hearth electrode include the combination of W, Ti, Cu, Al, Ag, Pt, Pd, Ta, Ni, Cr, metal nitride, TiN, WN, TaN or aforementioned substances.

9. two end memory devices according to claim 1, wherein said switchable layer includes the combination of non-crystalline silicon (a-Si), TiOx, AlOx, HfOx, SiOx, TaOx, CuOx, NbOx, WOx, solid electrolyte or aforementioned substances.

10. two end memory devices according to claim 1, wherein said electrode surface includes the continuum contacted with described switchable layer surface physics, the thickness of described continuum at about 1nm to about between 50nm

11. two end memory devices according to claim 1, the described discontinuity zone in the circumference of wherein said electrode surface is filled with electrical insulator.

12. two end memory devices according to claim 1, wherein, described two end memory devices also meet at least one in the following:

Described hearth electrode has the height within the scope of about 5nm to about 1000nm；Or

Described switchable layer has the switchable layer thickness in 1nm to 50nm scope.

13. a manufacture method for the electrode of two end memory devices, including:

The substrate of memory device is formed metal level；

Described metal level is formed oxide skin(coating)；

Described oxide skin(coating) is formed through hole；

The subset of the contour surface of the oxide skin(coating) formed by described through hole provides conducting film；And

Subset at described conducting film is formed over nonvolatile semiconductor memory member, and the described subset of described conducting film is used as the electrode of described nonvolatile semiconductor memory member.

14. method according to claim 13, described through hole forms the cross section of the shape with the group selecting free the following composition in described oxide skin(coating): circle, sub-circular, ellipse, approximate ellipsoidal, polygon and approximate polygon.

15. method according to claim 13, farther include to polish and the either flush of described oxide skin(coating) or approximate concordant described conducting film.

16. method according to claim 13, farther include: form the volatibility selector electrically coupled in series with described nonvolatile semiconductor memory member.

17. method according to claim 16, it is formed with described volatibility selector and farther includes at least one in the following:

Forming the described volatibility selector directly contacted with the subset of described conducting film, the subset of described conducting film is used as the electrode of described nonvolatile semiconductor memory member；

Form the described volatibility selector directly contacted with the second electrode of described nonvolatile semiconductor memory member；Or

The substrate of described memory device is formed the second metal level, wherein, formed and include with the described volatibility selector of described nonvolatile semiconductor memory member series connection forming described volatibility selector on the side contrary with described nonvolatile semiconductor memory member of described second metal level.

18. the method manufacturing two end memory devices, including:

The substrate of memory device is formed oxide skin(coating)；

It is patterned and etched into described oxide skin(coating) to form column device；

The subset of the exposed surface of described column device arranges conductive material；

Described column device arranges non-volatile switching material, and directly or indirectly contacts with described conductive material；And

Described switching material is formed the second conductive material.

19. method according to claim 18, farther include to remove the subset of described conductive material to form the conductive material with the approximate concordant of the end face of described column device and the subset of the circumference of the end face surrounding described column device from the end face of described column device.

20. method according to claim 18, wherein the combination of the conductive material in the subset of the described exposed surface of described column device, described non-volatile switching material and described second conductive material forms nonvolatile semiconductor memory member；And farther include to form the volatibility selector electrically coupled in series with described nonvolatile semiconductor memory member.