CN105740496A - Comprehensive optimization device and method for large-scale integrated circuit design and manufacture - Google Patents
Comprehensive optimization device and method for large-scale integrated circuit design and manufacture Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention discloses a novel comprehensive optimization device and method for large-scale integrated circuit design and manufacture. The device comprises an imaging system used for acquiring a process image of a chip in a chip manufacturing process; a calculation system used for analyzing and processing the acquired process image; and an information feedback system used for feeding back an analysis and process result to a chip design-manufacture process. According to the novel comprehensive optimization device and method, real-time information exchange in the large-scale integrated circuit design and manufacture process is organized again, the chip design and chip manufacture are considered together as a uniform process, and the comprehensive optimization is enabled to be possible. Therefore, multiple problems caused by the fact that an existing integrated circuit chip design process and an existing integrated circuit chip manufacturing process are separated in different economic entities are solved, the development period of integrated circuit products is accordingly reduced, and the rate of finished products in the large-scale integrated circuit manufacturing process is ensured.
Description
Technical field
The present invention relates to IC design and manufacture optimization system regions, especially the complex optimum Apparatus and method for of VLSI Design and manufacture.
Background technology
For IC manufacturing industry fund high concentration, the feature of professional and technical personnel's high concentration, the specialization of IC industry defines present chip Chevron Research Company (CRC) (fabless, namely without the chip Chevron Research Company (CRC) of manufacturer) and the general layout shared out the work and help one another of chip foundry (namely foundry specializes in the company of chip manufacturing).Under this general layout, chip Chevron Research Company (CRC) and chip foundries become independent economic entity.Between the two by limited data exchange, carrying out the cycle of the design of IC products, trial production, redesign, the final yield rate realizing requiring also starts large-scale production.This process is broadly divided into three phases, as shown in Figure 1:
First stage is the Basic Design stage, mainly is required to start with to carry out the functional design of chip, logical design, circuit design, physical Design (wiring) and technological design from chip functions by chip Chevron Research Company (CRC).Technological design therein needs according to the basic live width selected and the PDK/DDK (representing the data base of chip manufacturing factory process capability) provided by chip foundries, and by simulation means etc., completes the initial process design of chip.Design at these stage New function parts by examination print repeatedly on mask and silicon chip and detection, need to constantly improve, be finally completed the design of New function parts.After the design of whole chip completes, design drawing is submitted to chip foundries.Here, " design drawing " usually occurs with the form of design database, rather than paper drawing.
In second stage, chip foundries is produced as a trial by the small lot of chip, adjusts, optimization processing procedure, and is finally reached the optimization of processing procedure, reaches the requirement of yield rate, ready for large-scale production.
Phase III is the monster chip production phase.According to the data that second stage is obtained, under best process conditions, enter the large batch of production phase.
In the design of this chip and manufacture process, owing to design and the manufacture of chip are separated from each other in different economic entities, therefore bring many problems.Maximum problem is in this design-manufacture process, information exchange only very limited between chip Chevron Research Company (CRC) and chip foundries, chip Chevron Research Company (CRC) can not be fully understood by for the production technology ability of chip foundries in the design phase, and chip foundries is very unclear for the design idea of components and parts designer in the fabrication stage yet, the cycle designed and developed and produce as a trial thus must be made elongated, and be extremely difficult to overall optimization.Additionally the ageing of information exchange is also a problem under these conditions: even if chip foundries is ready to provide accurate process data to chip Chevron Research Company (CRC), the establishment of technical papers and PDK (ProcessDesignKits) is difficult to complete in time, thus delaying the construction cycle.Raising along with chip integration, particularly when the node size of semiconductor technology narrows down to less than 20 nanometers, more, more difficult production technology problem needs to solve, thus Real Data Exchangs and the total optimization between chip Chevron Research Company (CRC) and chip foundries becomes more and more important.
Summary of the invention
The present invention provides the complex optimum Apparatus and method for (HolisticProcessOptimization of a kind of novel VLSI Design and manufacture, HPO), this equipment can promote that the real time information in IC design manufacture process exchanges, chip design and chip manufacturing are combined consideration as a unified process, and carry out complex optimum, its objective is to reduce the process exploitation cycle of chip, improve the yield rate of ic manufacturing process.
A kind of complex optimum equipment of VLSI Design and manufacture, including: imaging system, computing system, and information feedback system, wherein,
Described imaging system, for the artwork picture of acquisition chip manufacture process chips；
Described computing system, for being analyzed the described artwork picture collected processing；
Described information feedback system, for feeding back to the module of chip design-manufacture process, for control chip design-manufacture process by the result after analyzing and processing.
As preferably, described in feed back to the content of chip design-manufacture process and be: the deviation of technical process, the optimization of mask and the renewal of processing procedure model；Specifically include:
The deviation of described technical process is the setting of adjusting process parameter in chip manufacturing proces；
The optimization of described mask is according to the parameter fed back, the Optical Proximity Correction of mask to be redesigned and re-optimization in mask fabrication process；
The renewal of described processing procedure model is the relevant parameter of described technical process to pass to chip Chevron Research Company (CRC) by updating processing procedure model, and is revised chip by chip Chevron Research Company (CRC) and design so as to more meet the manufacturing condition of foundries.
As preferably, the artwork picture gathered in described imaging system is the image on critical process node.
As preferably, the analyzing and processing in described computing system includes: defects detection, key dimension measurement, process window expectation.
As preferably, also including data-storage system, for the temporary described artwork picture gathered.
As preferably, described data-storage system, it is additionally operable to storage chip process data and fault detection data；
Correspondingly, described computing system, it is additionally operable to according to described chip technology data and fault detection data, chip manufacturing proces is modeled, emulation, optimizes, and update processing procedure model.
As preferably, also including, chip design database, for storing the design data of related chip, for defects detection and simulation optimization module.
As preferably, also including, processing procedure model database, for storing the data of processing procedure model, and it is supplied to chip design use.
As preferably, described imaging system is electronic scanner microscope.
The optimization equipment that the present invention proposes changes the data relationship between existing chip Chevron Research Company (CRC) and chip foundries, such that it is able to solve the problem that the design of prior art chips is separated from each other with chip manufacturing, chip design and chip manufacturing are closely connected, makes them become an ingredient optimizing system.Information exchange platform provided by the invention makes chip design vendors can understand the making technology condition of chip foundries timely and accurately so that it is design meets the production technology of chip foundries；This platform also makes chip foundries can follow the tracks of the change of process conditions in time, adjusts process parameter in time so that manufacture process can carry out ensureing the requirement of yield rate is achieved smooth sequential.
Personnel in this area work, or the personnel being familiar with Control System Design can easily see that the present invention advocates is a closed-loop control system, referring to Fig. 2, its control object is chip design-manufacture process, including chip design, fabrication mask and chip manufacturing.And chip designs-manufacture polyoptimal system HPO, it it is a controller with sampling unit.This controller achieves internal ring control by the information of chip manufacturing proces is fed back；By the information of mask fabrication process is fed back, including the re-optimization of mask, it is achieved that medium ring controls；Fed back by the renewal to processing procedure model and the information to chip design process and achieve outer shroud control.The purpose of this closed-loop control system is to ensure that control object, and namely foregoing chip design-manufacture process, steadily runs, efficiently to reduce the trial-production cycle of new product, it is ensured that the yield rate of manufacture process.
Provided by the present invention from another one angle is an information flow framework.In this HPO framework, to the continuous sampling of critical process node in manufacture process, analysis and the process to these sampling gained information, and to utilize these information be crucial to feedback and the optimization of technical process.In this framework, many original with following software modules relevant with chip making technology can integrate, and effectively shares resource, shares information.These modules include, and are not limited to: original design optimization module, manufacturability design module, mask complex optimum module, mask chip optimize module, chip or mask on-line checking module, accident analysis self-learning module, mask and chip processing procedure model etc. jointly.
By the realization of this information flow, the invention provides the comprehensive optimization method of a kind of VLSI Design and manufacture, specifically, the method includes:
Artwork picture by imaging system acquisition chip manufacture process chips；
It is analyzed processing by the described artwork picture collected by described computing system；
Result after described analyzing and processing is fed back, the setting of adjusting process parameter in chip manufacturing proces；
In mask fabrication process, the Optical Proximity Correction of mask is redesigned and re-optimization by the parameter according to feedback；
By updating processing procedure model, the deviation of described technical process is passed to chip Chevron Research Company (CRC), and described information is fed back to user.
It should be noted that; each sequence of steps above; all it is only the implementation not of the same race of the present invention; it it is not a kind of restriction to sequence of steps; in concrete application process; the sequencing implementing step can being adjusted, certainly, the method after implementing step that adjusts is still within protection scope of the present invention.
Existing chip design and manufacture will be brought revolutionary impact by the enforcement of the present invention: owing to continuously process for making being sampled, manufacturing process model can be updated timely, thus designer can predict the performance of chip more accurately；Chip image in the direct collection technology process of high-speed, high precision chip image collecting system, optimizing software can by being adjusted chip manufacturing proces the contrast of designed image and artwork picture automatically, decrease by manually revising the required time, improve work efficiency, and decrease the dependence to professional and technical personnel.
Accompanying drawing explanation
Fig. 1 is the graph of a relation of the prior art chips technological process of production；
Fig. 2 is the composition structure chart of the complex optimum equipment of VLSI Design of the present invention and manufacture；
Fig. 3 is the flow chart of the comprehensive optimization method of VLSI Design of the present invention and manufacture.
Detailed description of the invention
Below in conjunction with accompanying drawing and following nonlimiting examples, the present invention will be further described.
Referring to Fig. 2, the VLSI Design of present invention proposition and the comprehensive optimization system (HolisticProcessOptimization of manufacture, HPO) including: for the imaging system 600 of acquisition chip processing procedure chips artwork picture, for gathered image is analyzed, detects, and processing procedure process be modeled, emulate, optimize, the data that control store and computing system 700, chip design database 800 and processing procedure model database 900 and the auxiliary equipment being correlated with and facility.
Described imaging system 600 at least includes scanning electron microscope, by described scanning electron microscope artwork picture of acquisition chip on the critical process node of chip manufacturing 500；
The storage of described data and computing system 700 include computer cluster, connect the express network of computer cluster, possess storage device, database server that network connects, and corresponding application software and module.The task of computing system is to be analyzed the chip technology image gathered processing.Described data-storage system may be used for keeping in the chip technology image gathered, and then by computing system, it is processed.
The purpose using computer cluster and express network in computing system is to enable computing system to process calculating task in real time.Computer cluster and the express network present invention not being done special restriction, calculating task can be processed in real time as long as meeting.
The described analyzing and processing to artwork picture includes defects detection, key dimension measurement, process window estimation；The purpose of these analyzing and processing is that the deviation to technical process carries out feedback control.
Chip manufacturing 500 process is modeled by described computing system always according to accumulated chip technology data and fault detection data, emulation, optimizes, and updates processing procedure model.
Described chip design database 800 is in order to store the design data of related chip, for the module such as defects detection and simulation optimization.
The data that described processing procedure model database 900 is relevant in order to store processing procedure model, and in the way of encryption connection, exchange the information of processing procedure model with chip Chevron Research Company (CRC) 100 and be supplied to chip and design 200 processes.
Described " deviation of technical process is carried out feedback control " includes, but are not limited to: the setting of adjusting process parameter in chip manufacturing 500 process；In fabrication mask 400 process, the Optical Proximity Correction (OPC) of mask is redesigned and re-optimization by the parameter according to feedback；Pass information to the chip Chevron Research Company (CRC) problematic portion to chip by renewal processing procedure model redesign.
Still as in figure 2 it is shown, first have to realize the imaging system 600 of high-quality high speed, to the critical process node collection technology image in existing integrated circuit production process.At technological phase now, the production technology that the foundries 300 of tip uses is desirable that use electronic scanner microscope is as imaging system 600, to ensure the effective resolution of artwork picture and quality.If the process node that foundries 300 uses allows the imaging system 600 using other as sampling tool, such as, optically-based imaging system, as long as the resolution of artwork picture and picture quality can be guaranteed, such sampling system is also operable.
Computing system requires can the technique image information that collect be processed in real time, to ensure the real-time of the information collected.This is the high requirement of a comparison for computing system.The time needed due to detection and optimized algorithm is longer than the time of imaging system collection technology image, and computing system is generally adopted the mode of computer cluster and the artwork picture collected is carried out parallel processing.This just requires corresponding computer cluster node, connects the express network of each node, the systems soft ware etc. of management computer cluster.This computer cluster can also store system by embedding data, if the data collected can not immediately treat complete, it is possible to be first temporarily stored in data-storage system, reprocessing after resource to be calculated is available.
Should be understood that the concrete software module run in computing system and be not belonging to ingredient given to this invention, just it has been observed that provided by the present invention is a framework, various applicable software modules can be run in this framework.But at least should include defects detection module, photomask optimization module, critical size measurement module, processing procedure model optimization module etc. at computing system.Personnel in industry work can judge the suitability of a software module easily.
Need the interface setting up computing system and fabrication mask department and chip manufacturing department so that the deviation of the technical process detected by computing system and the correction that this deviation is done can be communicated to fabrication mask department and chip manufacturing department in time.Because these interfaces are all belonging to foundries 300 internal interface, it is achieved get up and have no problem.
The content of processing procedure model database 900 should at least include the PDK/PDD conventional contents comprised, and should increase the content that corresponding processing procedure model optimization module provides.The present invention does not specify the content format of processing procedure model database 900, because this form is different because of each chip foundries 300.The affiliated facility of processing procedure model database 900 also includes the user of encryption and connects and management module.The function of this module is management user, i.e. chip Chevron Research Company (CRC), the access to processing procedure model database 900, it is ensured that the information security of user and foundries 300 self, and ensures the information security between the different user of foundries.
Chip design database 800 actually includes design data server, because computing system needs the local data of chip as a rule.Design data server is accomplished by extracting the local data of this segment chip from chip design database 800 and it is necessary to provide these data in time, to meet the demand of computing system.Chip design database 800 also must be provided with security management mechanism, with the safety of the intellectual property (chip design) that the information security and client ensureing client is stored in this design database.
Use the complex optimum equipment that the present invention proposes can promote that the real time information in IC design manufacture process exchanges, chip foundries is facilitated to obtain the technical information of manufacture process in time, these technical information are utilized constantly to improve chip processing procedure, and the information of these technical information and process capability is supplied to chip Chevron Research Company (CRC) in time, can the making technology condition of analog chip foundries exactly, to its making technology being designed to meet chip foundries, to improve yield rate as soon as possible, shorten the trial production period of semiconductor product, so as to enter large-scale production as soon as possible.
As it is shown on figure 3, the invention provides the comprehensive optimization method of a kind of VLSI Design and manufacture, specifically, the method includes:
S101, artwork picture by imaging system acquisition chip manufacture process chips；
S102, it is analyzed the described artwork picture collected processing by described computing system；
S103, by after described analyzing and processing result feed back, the setting of adjusting process parameter in chip manufacturing proces；
S104, in mask fabrication process according to feedback parameter the Optical Proximity Correction of mask is redesigned and re-optimization；
S105, the deviation of described technical process is passed to chip Chevron Research Company (CRC) by updating processing procedure model, and described information is fed back to user.
It should be noted that; each sequence of steps above; all it is only the implementation not of the same race of the present invention; it it is not a kind of restriction to sequence of steps; in concrete application process; the sequencing implementing step can being adjusted, certainly, the method after implementing step that adjusts is still within protection scope of the present invention.
The artwork picture gathered in S101 is the image on critical process node.
Analyzing and processing in S102 includes: defects detection, key dimension measurement, process window expectation.
The method also includes, and is kept in by the described artwork picture gathered.Meanwhile, it is additionally included in data base storage chip process data and fault detection data；Correspondingly, chip manufacturing proces is modeled by S102 computing system according to described chip technology data and fault detection data, emulation, optimizes, and updates processing procedure model.
The method also includes, the design data of storage related chip, for step and the data storing processing procedure model of defects detection and simulation optimization module, and described data is supplied to the step that chip design uses.
As preferably, the equipment of collection technology image is electronic scanner microscope.The imaging system that it is pointed out that in the present embodiment is not limited to scanning electron microscope, it is also possible to replace with other products；As long as ensure that the speed of acquisition chip artwork picture and meeting the quality of imaging.
It should be noted that; each sequence of steps above; all it is only the implementation not of the same race of the present invention; it it is not a kind of restriction to sequence of steps; in concrete application process; the sequencing implementing step can being adjusted, certainly, the method after implementing step that adjusts is still within protection scope of the present invention.
Existing chip design and manufacture will be brought revolutionary impact by the enforcement of invention: owing to continuously process for making being sampled, manufacturing process model can be updated timely, thus designer can predict the performance of chip more accurately；Chip image in the direct collection technology process of high-speed, high precision chip image collecting system, optimizing software can by being adjusted chip manufacturing proces the contrast of designed image and artwork picture automatically, decrease by manually revising the required time, improve work efficiency, and decrease the dependence to professional and technical personnel.
Embodiment in above-described embodiment can combine further or replace; and embodiment is only that the preferred embodiments of the present invention are described; not the spirit and scope of the present invention are defined; under the premise without departing from design philosophy of the present invention; the various changes and modifications that in this area, technical scheme is made by professional and technical personnel, belong to protection scope of the present invention.
Claims (10)
1. the complex optimum equipment of a VLSI Design and manufacture, it is characterised in that including: imaging system, computing system and information feedback system, wherein,
Described imaging system, for the artwork picture of acquisition chip manufacture process chips；
Described computing system, for being analyzed the described artwork picture collected processing；
Described information feedback system, for feeding back to the module of chip design-manufacture process by the result after analyzing and processing.
2. complex optimum equipment according to claim 1, it is characterised in that described in feed back to the content of chip design-manufacture process and be: the deviation of technical process, the optimization of mask and the renewal of processing procedure model；Particularly as follows:
The deviation of described technical process is the setting of adjusting process parameter in chip manufacturing proces；
The optimization of described mask is according to the parameter fed back, the Optical Proximity Correction of mask to be redesigned and re-optimization in mask fabrication process；
The renewal of described processing procedure model is, by renewal processing procedure model, the parameter of technical process is passed to chip design database, and amendment chip designs.
3. complex optimum equipment according to claim 1, it is characterised in that the artwork picture gathered in described imaging system is the image on critical process node.
4. complex optimum equipment according to claim 1, it is characterised in that the analyzing and processing in described computing system includes: defects detection, key dimension measurement, process window expectation.
5. complex optimum equipment according to claim 1, it is characterised in that also include data-storage system, for the temporary described artwork picture gathered.
6. complex optimum equipment according to claim 5, it is characterised in that described data-storage system, is additionally operable to storage chip process data and fault detection data；
Correspondingly, described computing system, it is additionally operable to according to described chip technology data and fault detection data, chip manufacturing proces is modeled, emulation, optimizes, and update processing procedure model.
7. complex optimum equipment according to claim 5, it is characterised in that also include, chip design database, for storing the design data of related chip, for defects detection and simulation optimization module.
8. complex optimum equipment according to claim 1, it is characterised in that also include, processing procedure model database, for storing the data of processing procedure model, and is supplied to chip design use.
9. complex optimum equipment according to claim 1, it is characterised in that described imaging system is electronic scanner microscope.
10. the method according to the arbitrary described complex optimum equipment of claim 1-9, it is characterised in that including:
Artwork picture by imaging system acquisition chip manufacture process chips；
It is analyzed processing by the described artwork picture collected by described computing system；
Result after described analyzing and processing is fed back, the setting of adjusting process parameter in chip manufacturing proces；
In mask fabrication process, the Optical Proximity Correction of mask is redesigned and re-optimization by the parameter according to feedback；
By updating processing procedure model, the parameter of described technical process is passed to chip design database, amendment chip design.
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