CN105720108A - Low-capacitance and low-voltage semiconductor overvoltage protection device - Google Patents
Low-capacitance and low-voltage semiconductor overvoltage protection device Download PDFInfo
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- CN105720108A CN105720108A CN201610176392.6A CN201610176392A CN105720108A CN 105720108 A CN105720108 A CN 105720108A CN 201610176392 A CN201610176392 A CN 201610176392A CN 105720108 A CN105720108 A CN 105720108A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 42
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 24
- 239000001301 oxygen Substances 0.000 claims description 24
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 21
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 229910052698 phosphorus Inorganic materials 0.000 claims description 13
- 239000011574 phosphorus Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000000523 sample Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000012360 testing method Methods 0.000 claims description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000013461 design Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000001012 protector Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
- 229910052753 mercury Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66121—Multilayer diodes, e.g. PNPN diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a low-capacitance and low-voltage semiconductor overvoltage protection device. A chip layer comprises an N-type substrate, P2 base regions, N-type regions and emitter N-type doped regions, wherein the P2 base regions, the N-type regions and the emitter N-type doped regions are symmetrically diffused at the upper part and the lower part of the N-type substrate; P1 base regions are diffused in the emitter N-type doped regions and the P2 base regions; and the P1 base regions and the P2 base regions are varied doped base regions. Base region diffusion is divided into twice; the varied doped base regions are achieved; the P1 base regions are in high-concentration P-type doped diffusion; and the P2 base regions are in low-concentration P-type doped diffusion, so that the area of high-concentration regions at two sides of a PN junction is greatly reduced; low-voltage and over-voltage protection functions are ensured; the parasitic junction capacitance of a PN junction is greatly reduced; the low-capacitance design target is achieved; the process is simple; and the cost is low.
Description
Technical field
The present invention relates to a kind of low-capacitance over-voltage protector, more particularly to a kind of low electric capacity low-voltage semiconductor overvoltage protecting device.
Background technology
Along with making rapid progress of communication/communication technology, HD video, express network development increasingly swift and violent, relevant device signaling interface is more and more higher to the capacitance requirements of low pressure over-voltage protector.
The longitudinal design structure of current main flow solid discharging tube, as it is shown in figure 1, generally comprise the diffusion of two-sided boron and two-sided phosphorus two techniques of diffusion.Wherein to be P base rudimentary with N-type substrate and edge that to wear place, boundary, district parasitic for junction capacity.Owing to low voltage product needs the diffusion of PN junction two ends all to reach significantly high concentration, according to junction capacity computing formula:Conventional low voltage over-voltage protector parasitic capacitance can be very big, and generally at more than 100PF, but the junction capacity of this order of magnitude cannot meet the requirement of data transmission in high speed communication/communications field.
Chinese patent literature CN1851927 discloses a kind of low-capacitance over-voltage protector, and its capacitance requirements is at below 30pF.This device is made up of the semiconductor device etc. of emitter junction, collector junction, pin and lead frame, and this chip is formed four layers of bidirectionally symmetric structure of both-end by three P-N junction, and each group is doped to N from top to bottom successively respectively2、P2、N1、P1Four layers.Requiring at below 30pF although it also can meet junction capacity, but structure is more complicated, complex manufacturing technology, cost of manufacture is higher comparatively speaking.
Summary of the invention
Technical problem for above-mentioned existence; the present invention seeks to: a kind of low electric capacity low-voltage semiconductor overvoltage protecting device is provided, base diffusion is divided into twice, it is achieved varying doping base; P1 base is the doping diffusion of high concentration P type; P2 base is the doping diffusion of low concentration P type, so that PN junction both sides area with high mercury area is substantially reduced, it is ensured that low pressure and while over-voltage protecting function; substantially reduce the parasitic junction capacitance of this PN junction; achieving low capacitor design target, technique is simple, with low cost.
The technical scheme is that
A kind of low electric capacity low-voltage semiconductor overvoltage protecting device; chip layer includes N-type substrate, above and below N-type substrate, symmetrical diffusion has P2 base and N-type region and emitter stage n-type doping district; it is characterized in that; having P1 base, described P1 base and P2 base in emitter stage n-type doping district with the diffusion of P2 base is P type varying doping base.
Preferably, described P1 base is high concentration P type impure base region, and described P2 base is low concentration P type impure base region.
Preferably, chip layer surface is metallic electrode district.
Preferably, described metallic electrode district includes four floor, respectively aluminum, titanium, nickel and silver.
The preparation method that the invention also discloses a kind of low electric capacity low-voltage semiconductor overvoltage protecting device, it is characterised in that comprise the following steps:
S01: diffuse to form two-sided P1 base at crystal column surface, described P1 base is high concentration p type impurity region；
S02: diffuse to form P2 base overlapping with P1 base, described P2 base is low concentration p type impurity region；
S03:N1 phosphorus district spreads, and forms the low PN junction punctured with P1 base, and concurrently forms emitter stage n-type doping.
Preferably, following steps are specifically included:
S11: crystal column surface once oxidation, forms field oxygen barrier layers: furnace temperature 1100 DEG C, oxygen 4L/min, hydrogen 5L/min, the desirable oxidation layer thickness of formation is 1.5 μm ± 10%；
S12: diffuse to form P1 base: carry out boron source deposit under furnace temperature 1000 DEG C, oxygen 2L/min, nitrogen 3L/min, deposition time is 30min；Carrying out boron source propelling under furnace temperature 1200 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 200min, and using four probe test diffusion square resistances is 15 Ω ± 10%, and junction depth is 23 μm ± 10%；
S13: diffuse to form P2 base: carry out boron source deposit under furnace temperature 950 DEG C, oxygen 2L/min, nitrogen 3L/min, deposition time is 18min；Carrying out boron source propelling under furnace temperature 1200 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 500min, and using four probe test diffusion square resistances is 50 Ω ± 10%, junction depth 20 μm ± 10%；
S14:N1 phosphorus district spreads: at furnace temperature 1050 DEG C, oxygen 2L/min, nitrogen 3L/min, taking and carry out phosphorus source deposit under the nitrogen 1L/min of source, deposition time is 18min；Carrying out phosphorus source propelling under furnace temperature 1100 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 260min, and using four probe test diffusion square resistances is 1 Ω ± 10%, junction depth 10 μm ± 10%；
S15: deposit metal layer: by ion beam metallization evaporator technique deposit metal layer.
Preferably, the metal layer of described step S15 is four layers, respectively is 1 μm of aluminum, titanium 0.3 μm, 0.7 μm of nickel, silver 0.5 μm.
Compared with prior art, the invention have the advantage that
1. base diffusion is divided into twice; realize varying doping base; P1 base is the doping diffusion of high concentration P type; P2 base is the doping diffusion of low concentration P type; so that PN junction both sides area with high mercury area is substantially reduced; while ensureing low pressure and over-voltage protecting function, substantially reduce the parasitic junction capacitance of this PN junction, it is achieved that low capacitor design target.Can be widely used in high definition security device, have a good application prospect.
2. this low electric capacity low-voltage semiconductor overvoltage protecting device, simple in construction, it is achieved technique is simple, greatly reduces cost.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described:
Fig. 1 is the vertical structure schematic diagram of existing low-voltage over-voltage protector；
Fig. 2 is the vertical structure schematic diagram of the low electric capacity low-voltage semiconductor overvoltage protecting device of the present invention；
Fig. 3 is the preparation method flow chart of the low electric capacity low-voltage semiconductor overvoltage protecting device of the present invention；
Fig. 4 is the range of scatter schematic diagram of P1 base of the present invention；
Fig. 5 is the range of scatter schematic diagram of P2 base of the present invention；
Fig. 6 is the range of scatter schematic diagram of N1 base of the present invention；
Fig. 7 is the range of scatter schematic diagram in metallic electrode district of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with detailed description of the invention and with reference to accompanying drawing, the present invention is described in more detail.It should be understood that these descriptions are illustrative of, and it is not intended to limit the scope of the present invention.Additionally, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring idea of the invention.
Embodiment:
As shown in Figure 2; a kind of low electric capacity low-voltage semiconductor overvoltage protecting device; chip layer includes N-type substrate 1, above and below N-type substrate 1, symmetrical diffusion has P2 base 2 and N-type region 3 and emitter stage n-type doping district 4; P1 base 5 is had with P2 base 2 diffusion in emitter stage n-type doping district 4; P1 base 5 is high concentration P type impure base region, and P2 base 2 is low concentration P type impure base region.Chip layer surface is metallic electrode district 6.Metallic electrode district 6 includes four floor, 1 μm of aluminum, titanium 0.3 μm, 0.7 μm of nickel, silver 0.5 μm.
As it is shown on figure 3, the preparation method of a kind of low electric capacity low-voltage semiconductor overvoltage protecting device of the present invention, comprise the following steps:
S01: diffuse to form two-sided P1 base at crystal column surface, described P1 base is high concentration p type impurity region, and this area capacitance value is CP1；
S02: diffuse to form P2 base overlapping with P1 base, described P2 base is low concentration p type impurity region, and this region total capacitance value is about CP1+CP2；
S03:N1 phosphorus district spreads, and forms the low PN junction punctured with P1 base, and concurrently forms emitter stage n-type doping.
The over-voltage protector of the present invention is made up of diffusion furnace, and the wafer parameters of use is: resistivity 40～50 Ω/cm thickness 220 μm ± 10%；
Specifically include following steps:
S11: crystal column surface once oxidation, forms field oxygen barrier layers: furnace temperature 1100 DEG C, oxygen 4L/min, hydrogen 5L/min, the desirable oxidation layer thickness of formation is 1.5 μm ± 10%；
S12: diffuse to form P1 base: carry out boron source deposit under furnace temperature 1000 DEG C, oxygen 2L/min, nitrogen 3L/min, deposition time is 30min；Carrying out boron source propelling under furnace temperature 1200 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 200min, and using four probe test diffusion square resistances is 15 Ω ± 10%, and junction depth is 23 μm ± 10%；Range of scatter is as shown in Figure 4.
S13: diffuse to form P2 base: carry out boron source deposit under furnace temperature 950 DEG C, oxygen 2L/min, nitrogen 3L/min, deposition time is 18min；Carrying out boron source propelling under furnace temperature 1200 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 500min, and using four probe test diffusion square resistances is 50 Ω ± 10%, junction depth 20 μm ± 10%；Range of scatter is as shown in Figure 5.
S14:N1 phosphorus district spreads: at furnace temperature 1050 DEG C, oxygen 2L/min, nitrogen 3L/min, taking and carry out phosphorus source deposit under the nitrogen 1L/min of source, deposition time is 18min；Carrying out phosphorus source propelling under furnace temperature 1100 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 260min, and using four probe test diffusion square resistances is 1 Ω ± 10%, junction depth 10 μm ± 10%；Range of scatter is as shown in Figure 6.
S15: deposit metal layer: by ion beam metallization evaporator technique deposit metal layer.Metal layer is four layers, respectively is 1 μm of aluminum, titanium 0.3 μm, 0.7 μm of nickel, silver 0.5 μm.Range of scatter is as shown in Figure 7.
Following table is the parameter comparison of made sample after this design of use:
As seen from the above table, parasitic junction capacitance, ensureing on the basis of original product function and parameter, is reduced into original about 20%, it is possible to achieve junction capacity desired value is less than 30PF by the present invention.
It should be appreciated that the above-mentioned detailed description of the invention of the present invention is used only for exemplary illustration or explains principles of the invention, and it is not construed as limiting the invention.Therefore, any amendment of making when without departing from the spirit and scope of the present invention, equivalent replacement, improvement etc., should be included within protection scope of the present invention.Additionally, claims of the present invention be intended to fall in the equivalents on scope and border or this scope and border whole change and modifications example.
Claims (7)
1. one kind low electric capacity low-voltage semiconductor overvoltage protecting device; chip layer includes N-type substrate, above and below N-type substrate, symmetrical diffusion has P2 base and N-type region and emitter stage n-type doping district; it is characterized in that; having P1 base, described P1 base and P2 base in emitter stage n-type doping district with the diffusion of P2 base is P type varying doping base.
2. low electric capacity low-voltage semiconductor overvoltage protecting device according to claim 1, it is characterised in that described P1 base is high concentration P type impure base region, described P2 base is low concentration P type impure base region.
3. low electric capacity low-voltage semiconductor overvoltage protecting device according to claim 1, it is characterised in that chip layer surface is metallic electrode district.
4. low electric capacity low-voltage semiconductor overvoltage protecting device according to claim 3, it is characterised in that described metallic electrode district includes four floor, respectively aluminum, titanium, nickel and silver.
5. the preparation method of one kind low electric capacity low-voltage semiconductor overvoltage protecting device, it is characterised in that comprise the following steps:
S01: diffuse to form two-sided P1 base at crystal column surface, described P1 base is high concentration p type impurity region；
S02: diffuse to form P2 base overlapping with P1 base, described P2 base is low concentration p type impurity region；
S03:N1 phosphorus district spreads, and forms the low PN junction punctured with P1 base, and concurrently forms emitter stage n-type doping.
6. the preparation method of low electric capacity low-voltage semiconductor overvoltage protecting device according to claim 5, it is characterised in that specifically include following steps:
S11: crystal column surface once oxidation, forms field oxygen barrier layers: furnace temperature 1100 DEG C, oxygen 4L/min, hydrogen 5L/min, the desirable oxidation layer thickness of formation is 1.5 μm ± 10%；
S12: diffuse to form P1 base: carry out boron source deposit under furnace temperature 1000 DEG C, oxygen 2L/min, nitrogen 3L/min, deposition time is 30min；Carrying out boron source propelling under furnace temperature 1200 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 200min, and using four probe test diffusion square resistances is 15 Ω ± 10%, and junction depth is 23 μm ± 10%；
S13: diffuse to form P2 base: carry out boron source deposit under furnace temperature 950 DEG C, oxygen 2L/min, nitrogen 3L/min, deposition time is 18min；Carrying out boron source propelling under furnace temperature 1200 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 500min, and using four probe test diffusion square resistances is 50 Ω ± 10%, junction depth 20 μm ± 10%；
S14:N1 phosphorus district spreads: at furnace temperature 1050 DEG C, oxygen 2L/min, nitrogen 3L/min, taking and carry out phosphorus source deposit under the nitrogen 1L/min of source, deposition time is 18min；Carrying out phosphorus source propelling under furnace temperature 1100 DEG C, oxygen 2L/min, nitrogen 3L/min, the propelling time is 260min, and using four probe test diffusion square resistances is 1 Ω ± 10%, junction depth 10 μm ± 10%；
S15: deposit metal layer: by ion beam metallization evaporator technique deposit metal layer.
7. the preparation method of low electric capacity low-voltage semiconductor overvoltage protecting device according to claim 6, it is characterised in that the metal layer of described step S15 is four layers, respectively is 1 μm of aluminum, titanium 0.3 μm, 0.7 μm of nickel, silver 0.5 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610176392.6A CN105720108A (en) | 2016-03-25 | 2016-03-25 | Low-capacitance and low-voltage semiconductor overvoltage protection device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610176392.6A CN105720108A (en) | 2016-03-25 | 2016-03-25 | Low-capacitance and low-voltage semiconductor overvoltage protection device |
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| CN105720108A true CN105720108A (en) | 2016-06-29 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229349A (en) * | 2016-09-30 | 2016-12-14 | 安徽富芯微电子有限公司 | A kind of ultra-low capacitance low-voltage semiconductor discharge tube chip and manufacture method thereof |
| CN106653864A (en) * | 2017-02-27 | 2017-05-10 | 杭州赛晶电子有限公司 | N+ PN- PN+ type forward and reverse overvoltage protection silicon diode, and silicon core and manufacturing method thereof |
| CN113725210A (en) * | 2021-07-19 | 2021-11-30 | 富芯微电子有限公司 | High-power semiconductor overvoltage protection device |
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| US4695863A (en) * | 1985-03-12 | 1987-09-22 | Thomson Csf | Gateless protection thyristor with a thick, heavily doped central N-layer |
| JPH05335558A (en) * | 1992-06-04 | 1993-12-17 | Fuji Electric Co Ltd | Bidirectional 2-terminal thyristor |
| US5429953A (en) * | 1992-07-15 | 1995-07-04 | Texas Instruments Incorporated | Method of forming solid state suppressors with concave and diffused substitution regions |
| CN102263126A (en) * | 2010-05-27 | 2011-11-30 | 新电元工业株式会社 | Short-circuit Thyristor |
| CN204130543U (en) * | 2013-10-17 | 2015-01-28 | 意法半导体(图尔)公司 | Vertical power parts |
| CN205452296U (en) * | 2016-03-25 | 2016-08-10 | 昆山海芯电子科技有限公司 | Low electric capacity low -voltage semiconductor overvoltage protector spare |
-
2016
- 2016-03-25 CN CN201610176392.6A patent/CN105720108A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4695863A (en) * | 1985-03-12 | 1987-09-22 | Thomson Csf | Gateless protection thyristor with a thick, heavily doped central N-layer |
| JPH05335558A (en) * | 1992-06-04 | 1993-12-17 | Fuji Electric Co Ltd | Bidirectional 2-terminal thyristor |
| US5429953A (en) * | 1992-07-15 | 1995-07-04 | Texas Instruments Incorporated | Method of forming solid state suppressors with concave and diffused substitution regions |
| CN102263126A (en) * | 2010-05-27 | 2011-11-30 | 新电元工业株式会社 | Short-circuit Thyristor |
| CN204130543U (en) * | 2013-10-17 | 2015-01-28 | 意法半导体(图尔)公司 | Vertical power parts |
| CN205452296U (en) * | 2016-03-25 | 2016-08-10 | 昆山海芯电子科技有限公司 | Low electric capacity low -voltage semiconductor overvoltage protector spare |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229349A (en) * | 2016-09-30 | 2016-12-14 | 安徽富芯微电子有限公司 | A kind of ultra-low capacitance low-voltage semiconductor discharge tube chip and manufacture method thereof |
| CN106229349B (en) * | 2016-09-30 | 2019-05-10 | 富芯微电子有限公司 | A kind of ultra-low capacitance low-voltage semiconductor discharge tube chip and its manufacturing method |
| CN106653864A (en) * | 2017-02-27 | 2017-05-10 | 杭州赛晶电子有限公司 | N+ PN- PN+ type forward and reverse overvoltage protection silicon diode, and silicon core and manufacturing method thereof |
| CN106653864B (en) * | 2017-02-27 | 2023-07-25 | 杭州赛晶电子有限公司 | N (N) + PN - PN + Silicon diode with forward and reverse overvoltage protection and silicon core and manufacturing method thereof |
| CN113725210A (en) * | 2021-07-19 | 2021-11-30 | 富芯微电子有限公司 | High-power semiconductor overvoltage protection device |
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