CN105718241B - A kind of sort-type mixed branch forecasting system based on SPARC V8 architectures - Google Patents
A kind of sort-type mixed branch forecasting system based on SPARC V8 architectures Download PDFInfo
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Abstract
A kind of sort-type mixed branch forecasting system based on SPARC V8 architectures,Branch instruction type is obtained according to instruction PC inquiry branch target caches in fetching level first,Branch instruction is assigned to respective prediction module,Redirect branch prediction and use the return address storehouse RAS with dynamic configuration counter,Indirect branch prediction has used the method that supplement is predicted,The flag bit Tag uses that conditional branch prediction records last time branch prediction correctness in conditional branching target cache CBTB redirect tri-state transfer algorithm partially,It is recorded in decoding level according to the decoding object information to instruction in information of forecasting table (PIT),Judge performing level,If the prediction result of branch instruction is redirects,Then result judgement is carried out using jump forecasting result determining device Arbiter_T,If the prediction result of branch instruction is not redirect,Then result judgement is carried out using not jump forecasting result determining device Arbiter_N,Solving branch instruction instruction delay to caused by streamline influences,Improve the execution efficiency of processor.
Description
Technical field
The present invention relates to a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures, especially for
It is pre- that the wide variety of SPARC processors of space industry give a kind of sort-type mixed branch based on SPARC V8 architectures
Examining system, i.e., using the mixed branch prediction scheme of instruction classification formula.
Background technology
In field of processors, one of the classical representative of SPARC architectures as risc processor, occupy particularly significant
Status.Microprocessor based on SPARC frameworks is with good expansibility, and has been widely used in aviation at present, has led to
Letter and various Embedded Application fields.Therefore develop with higher performance can be towards various target customer's application demands
SPARC processors there is good application prospect.
Processor architecture research at present achieves very big development, and pipelining greatly enhances instruction
Level degree of parallelism (Instruction Level Parallelism), but with the continuous complexity of application demand, high-performance treatments
The research of device remains the focus of academia's research.The factor of constraint high-performance processor development has many kinds, wherein on referring to
The research for making level parallel is to develop one of key factor of high-performance processor, and influence instruction level parallelism one it is crucial because
Element is exactly branch instruction present in program.
Execution of the branch instruction to processor pipeline Program has material impact, and the branch instruction redirected will weight
The new direction for changing instruction stream in streamline, this will introduce more bubbles (bubble) in a pipeline, be handled in the modern times
In body architecture, the hardware cost and power consumption penalty that branch instruction is brought are also with pipeline depth and streamline firing order
Width (issue width) increase and increase.Therefore the research on branch prediction techniques is always popular research heat
One of point.
Branch prediction techniques are to improve the important means of processor performance, and its purpose is that the control weakened between instruction is related
Property (control dependence), so as to improve instruction level parallelism, improve processor performance.The increase of pipeline depth will
Influence of the branch instruction to track performance can be deepened, along with instruction multi-emitting technology (Multiple Instruction
Launch application), influence of the branch instruction to track performance further increases, therefore the development of branch prediction techniques is one
Kind is inevitable.
Promoting the principal element of branch prediction techniques development has：1st, the appearance of new opplication and new processor structure carry
Go out to need to be adapted to their new forecasting mechanism.2nd, with the development of deep submicron process, the problem of power consumption of processing unit increasingly
Important, this just needs to be weighed between the efficiency and power consumption of processor branch prediction.3rd, the new skill such as super flowing water and superscale
The application of art make it that processor is still very big to the demand of branch prediction accuracies.
Branch prediction techniques will not only consider its prediction accuracy, it is also contemplated that the hardware spending that it brings to processor
With the influence of clock delay, existing branch prediction techniques are often because hardware size is too big, prediction algorithm is excessively complicated, branch
The raising of prediction reason the constrains processor performance such as accuracy is not high.
The content of the invention
The technology of the present invention solves problem：Overcome the deficiencies in the prior art, propose that one kind is based on SPARC V8 system knots
The sort-type mixed branch forecasting system of structure, you can to improve the accuracy of branch instruction predictions, and can reduces hardware size, no
Make prediction algorithm excessively complicated.
The present invention technical solution be：
The present invention is made up of following module：PC management modules, branch instruction enquiry module, branch instruction predictions mould
Block, branch instruction information logging modle, branch instruction predictions result judge module, unconditional branch target cache UBTB
(Unconditional Branch Target Buffer), conditional branching target cache CBTB (Conditional Branch
Target Buffer), return address storehouse RAS (Return Address Stack), indirect branch target caching IBTB
(Indirect Branch Target Buffer), pattern history table PHT (Patter History Table), information of forecasting
Table (PIT) (Prediction Info Table)；
Unconditional branch target cache UBTB (Unconditional Branch Target Buffer) stores no bar
Part redirects branch instruction type information corresponding to branch instruction PC values, and is redirected corresponding to unconditional jump branch instruction PC values
Destination address；
Conditional branching target cache CBTB (Conditional Branch Target Buffer) stores conditional jump
Branch instruction type information corresponding to branch instruction PC values, and jump target corresponding to conditional jump branch instruction PC values
Location；
Return address storehouse RAS (Return Address Stack) is stored to be returned corresponding to returning branch instruction PC values
Destination address；
Indirect branch target caching IBTB (Indirect Branch Target Buffer) stores indirect branch instruction
Jump target addresses corresponding to PC values；
Pattern history table PHT (Patter History Table) stores branch corresponding to indirect branch instruction PC values and jumped
Turn direction；
Information of forecasting table (PIT) (Prediction Info Table) stores information of forecasting corresponding to branch instruction PC values；
PC management modules, receive branch prediction results that instruction PC values, the branch instruction predictions module of outside input send,
The branch prediction results feedback information that renewal and correction module are sent.The branch that wherein branch instruction predictions module is sent is pre-
Result is surveyed, including, whether branch instruction predictions redirect, branch instruction predictions jump target addresses, renewal and correction module
The branch prediction results feedback information sent, including branch instruction PC values, branch prediction results correctness, branch instruction redirect
Whether, branch instruction jump target addresses, in branch predicting system initial launch, PC management modules instruct according to outside input
PC values calculate plus a fixed numerical value of N produces next instruction PC value, and this numerical value of N fixed can be handled with processor
Command length, and the branch prediction algorithms taken are relevant, and next instruction PC value is then sent into branch instruction and inquires about mould
Block；If branch prediction results mistake in the branch prediction results feedback information that renewal and correction module are sent, gives up
The branch prediction results that branch instruction predictions module is sent, if the branch that then judgement renewal and correction module are sent is pre-
Survey branch instruction in result feedback information to redirect, then the branch prediction results feedback information sent renewal and correction module
Middle branch instruction jump target addresses are sent into branch instruction enquiry module as next instruction PC value；If renewal and mistake are entangled
Branch prediction results mistake in the branch prediction results feedback information that positive module is sent, then give up branch instruction predictions module and send
Branch prediction results, if then judging branch in renewal and the branch prediction results feedback information sent of correction module
Instruction does not redirect, then branch instruction PC values add in branch prediction results feedback information renewal and correction module sent
The numerical value of N of fixation said before, which calculates, produces next instruction PC value, and it is sent into branch instruction enquiry module；If more
Branch prediction results are correct in the branch prediction results feedback information that new and correction module is sent, if then judging branch
Branch instruction predictions redirect in the branch prediction results that branch prediction module is sent, then point branch instruction predictions module sent
Branch instruction predictions jump target addresses are sent into branch instruction enquiry module as next instruction PC value in branch prediction result；Such as
Branch prediction results are correct in the branch prediction results feedback information that fruit is updated and correction module is sent, if then judged
Branch instruction predictions do not redirect in the branch prediction results that branch instruction predictions module is sent, then instruction PC values outside being sent into
Next instruction PC value of generation is calculated plus the numerical value of N of fixation said before, and it is sent into branch instruction enquiry module；Together
When by next instruction PC values deliver to outside to being instructed corresponding to instruction PC values into row decoding, by after decoding Instruction decoding letter
Breath sends branch instruction decoding information logging modle back to, outside that Instruction decoding information corresponding to instruction PC values is sent into external command
Execution unit is performed, and execution result information is sent into branch instruction predictions result judge module；
Branch instruction enquiry module, the instruction PC values that PC management modules are sent are received, according to unconditional branch target cache
UBTB (Unconditional Branch Target Buffer) and conditional branching target cache CBTB (Conditional
Branch Target Buffer) storage instruction PC values branch instruction type corresponding with instruction PC values, obtain and PC pipe
Branch instruction type information corresponding to the instruction PC values that reason module is sent, then will instruction PC values and branch instruction type information
It is sent into branch instruction predictions module；
Branch instruction predictions module, receive instruction PC values and branch instruction type letter that branch instruction enquiry module is sent
Breath, if branch instruction type information show present instruction PC values corresponding to branch instruction, be unconditional jump and branch target
Address is the branch instruction directly redirected, then the branch instruction predictions redirect, then by inquiring about unconditional branch target cache
UBTB (Unconditional Branch Target Buffer), obtain branch instruction predictions corresponding with instruction PC values and jump
Turn destination address, while obtain referring to the branch according to numerical value of N of the instruction PC values plus the fixation used in PC management modules
Return address corresponding to order, then return address is recorded in return address storehouse RAS (Return Address Stack)；
If branch instruction type information show present instruction PC values corresponding to branch instruction, be return type branch instruction, then from
A return address is taken out in return address storehouse RAS (Return Address Stack) as the branch of the return type to refer to
Order prediction jump target addresses；If branch instruction type information show present instruction PC values corresponding to branch instruction, be indirect
Branch instruction, then indirect branch instruction prediction redirect, then from indirect branch target caching IBTB (Indirect Branch
Target Buffer) in read instruction PC values corresponding to branch instruction predictions jump target addresses, if do not divided indirectly
Branch instruction corresponding to instruction PC values is read in branch target cache IBTB (Indirect Branch Target Buffer)
When prediction jump target addresses are IBTB (Indirect Branch Target Buffer) prediction of failure, then from unconditional
Read corresponding to instruction PC values and divide in branch target cache UBTB (Unconditional Branch Target Buffer)
Branch branch prediction jump target addresses, this mode, which is referred to as, supplements prediction；If branch instruction type information shows present instruction
Branch instruction corresponding to PC values, it is conditional branch instructions, then passes through query pattern history lists PHT (Patter History
Table branch instruction predictions corresponding with instruction PC values) are obtained and redirect direction, then pass through querying condition branch target cache
CBTB (Conditional Branch Target Buffer) obtains branch instruction predictions corresponding with instruction PC values and redirected
Destination address；Branch instruction predictions corresponding to instruction PC values in branch instruction predictions module, instruction PC values are redirected direction
And branch instruction predictions jump target addresses are sent into branch instruction information logging modle, while in branch instruction predictions module
Instruction PC values, branch instruction predictions corresponding to instruction PC values redirect direction and branch instruction predictions jump target addresses are given
Enter PC management modules；
Branch instruction information logging modle, receive instruction PC values, instruction PC values pair that branch instruction predictions module is sent
The branch instruction predictions answered redirect direction and branch instruction predictions jump target addresses, receive the instruction PC values pair of outside input
Instruction decoding information is answered, judges whether present instruction is branch instruction according to Instruction decoding information corresponding to instruction PC values, and be
The no prediction for having carried out branch instruction and having redirected direction and branch instruction jump target addresses, and information record is believed in prediction
Cease in table (PIT) (Prediction Info Table), the instruction PC values received are then sent into branch instruction predictions result and sentenced
Disconnected module；
Branch instruction predictions result judge module, receive instruction PC values, reception that branch instruction information logging modle is sent
The execution result information of the instruction of the execution result information of the instruction of outside input, wherein outside input includes, and branch instruction is jumped
Turn direction, branch instruction jump target addresses, according to present instruction implementing result and unconditional branch target cache UBTB
(Unconditional Branch Target Buffer), conditional branching target cache CBTB (Conditional Branch
Target Buffer) and information of forecasting table (PIT) (Prediction Info Table) in record information to branch prediction knot
The correctness of fruit is judged, i.e., if branch instruction direction redirects in the execution result information of the instruction of outside input,
The correction judgement of branch prediction results is then carried out using jump forecasting result determining device Arbiter_T, if outside input
Branch instruction direction does not redirect in the execution result information of instruction, then using not jump forecasting result determining device Arbiter_
N carry out branch prediction results correction judgement, obtain branch prediction correctness information, then present instruction PC values, divide
Branch prediction correctness information, branch instruction redirect direction, branch instruction jump target addresses are sent to renewal and error correcting
Module；
Renewal and correction module, it is pre- to receive the instruction PC values sent of branch instruction predictions result judge module, branch
Survey correctness information, branch instruction redirect direction, branch instruction jump target addresses, if branch prediction is correct, utilize
Instruction PC values, the branch instruction that branch instruction predictions result judge module is sent redirect direction, branch instruction jump target addresses
Information is to unconditional branch target cache UBTB (Unconditional Branch Target Buffer), conditional branching target
Cache CBTB (Conditional Branch Target Buffer), return address storehouse RAS (Return Address
Stack), indirect branch target caching IBTB (Indirect Branch Target Buffer), pattern history table PHT
Corresponding information in (Patter History Table), information of forecasting table (PIT) (Prediction Info Table) is carried out more
Newly, instruction PC values, branch prediction correctness information, branch instruction are then redirected into direction, branch instruction jump target addresses
It is sent into PC management modules；If branch prediction results mistake, error correcting signal is sent into outside, outside will be entangled according to mistake
Positive signal carries out error correcting to processor pipeline, then will instruction PC values, branch prediction correctness information, branch instruction
Redirect direction, branch instruction jump target addresses are sent into PC management modules；
The branch instruction predictions of return type, which have used, wherein in branch instruction predictions module carries dynamic configuration counter
Return address storehouse RAS (Return Address Stack)：
Return address storehouse RAS (Return Address Stack) with dynamic configuration counter, in dynamic configuration
Counter will not point to the storehouse in return address storehouse RAS (Return Address Stack) when being not used
Any one, only when counter uses, counter is just locked, fixed sensing return address storehouse RAS
That of the storehouse of counter is used in (Return Address Stack)；
The wherein prediction conditional branch target cache CBTB of branch instruction predictions module conditional branch instruction
The renewal of (Conditional Branch Target Buffer) has used redirects tri-state transfer algorithm partially：
It is conditional branch instructions prediction conditional branch target cache CBTB to redirect tri-state transfer algorithm partially
Branch prediction state flag bit Tag state transition algorithms in (Conditional Branch Target Buffer), branch are pre-
Survey state flag bit Tag and be used for recording branch instruction in the upper correctness once predicted, correctly remain 0, mistake puts 1, jumps partially
Turning tri-state transfer algorithm has three states, is represented with a bit register, with conditional branching target cache CBTB (Conditional
Branch Target Buffer) exemplified by list item n, initial Tag states are 0, write the branch instruction information redirected for the first time
When state remain 0.When Tag states are 0, Tag if not having to redirect when the branch instruction of record is performing next time
State is set to 1, otherwise remains 0.When Tag states are 1, if the branch instruction of record is not jumped when performing next time
Turn, then empty the information of this list item n records, be reset to original state, otherwise Tag states are set to 0；
Wherein in branch instruction enquiry module, according to instruction PC inquiry unconditional branch target caches UBTB
(Unconditional Branch Target Buffer) or conditional branching target cache CBTB (Conditional Branch
Target Buffer) in the instruction PC values branch instruction type corresponding with instruction PC values that prestores；
Wherein in branch instruction predictions result judge module, jump forecasting result determining device Arbiter_T evaluation algorithms are such as
Under：
If instructing PC values in branch instruction predictions result judge module, inquiry information of forecasting table (PIT) (Prediction
Info Table) in there is no occurrence, then branch instruction perform mistake, be judged as branch misprediction；If instruction PC values are looked into
Asking in information of forecasting table (PIT) (Prediction Info Table) has occurrence, then branch instruction performs correct, is judged as point
Branch prediction is correct；
Jump forecasting result determining device Arbiter_N evaluation algorithms are not as follows：
If instructing PC values in branch instruction predictions result judge module, inquiry information of forecasting table (PIT) (Prediction
Info Table) in there is no occurrence, then branch instruction performs correct, is judged as that branch prediction is correct；If instruction PC values are looked into
Asking in information of forecasting table (PIT) (Prediction Info Table) has occurrence, then branch instruction performs mistake, is judged as point
Branch prediction error；
Compared with the prior art, the invention has the advantages that：
(1) design employs sort-type mixed branch Forecasting Methodology, can more preferable pin by classifying to branch instruction
More excellent branch prediction schemes are taken different branch instructions, improve the coverage to branch instruction predictions.
(2) mode of supplement prediction is taken for indirect branch instruction, as IBTB (Indirect Branch Target
Buffer last time jump target) is read during prediction of failure from UBTB (Unconditional Branch Target Buffer)
Address is predicted as supplement, can further improve branch prediction accuracy.
(3) for redirecting branch and returning branch instruction, the return address storehouse with dynamic configuration counter has been used
RAS (Return Address Stack), more branch instruction informations can be recorded with less hardware resource, improve resource
Utilization rate, smaller hardware cost.
(4) PHT can preferably be coordinated using tri-state transfer algorithm is redirected partially in conditional jump branch instruction predictions, and
When exclude branch prediction redundancy interference information, improve the accuracy of prediction.
(5) separated unconditional branch target cache UBTB has been used in branch instruction enquiry module
(Unconditional Branch Target Buffer) or conditional branching target cache CBTB (Conditional Branch
Target Buffer), different classes of branch instruction is individually stored, reduce the interference information of correlation, improve the correct of prediction
Rate.
(6) jump forecasting result determining device Arbiter_T and not has been used in branch instruction predictions result judge module
Jump forecasting result determining device Arbiter_N separately judged branch prediction results, can be more accurately to branch prediction knot
Fruit is judged, is advantageous to error correcting, improves processor performance.
Brief description of the drawings
Fig. 1 is branch predicting system design architecture of the present invention.
Fig. 2 is that the present invention redirects branch prediction part design architecture.
Fig. 3 is returning branch predicted portions design architecture of the present invention.
Fig. 4 is indirect branch predicted portions design architecture of the present invention.
Fig. 5 is conditional branch prediction part of the present invention design architecture.
Fig. 6 is that Tag states redirect tri-state partially in CBTB of the present invention (Conditional Branch Target Buffer)
Transfer algorithm.
Fig. 7 is RAS of the present invention (Return Address Stack) dynamic configuration counter allocation algorithm.
Fig. 8 is that flow is corrected in prediction result inspection of the present invention.
Fig. 9 is prediction result evaluation algorithm of the present invention.
Figure 10 is function structure chart of the present invention.
Embodiment
The present invention basic ideas be：A kind of sort-type mixed branch forecasting system based on SPARC V8 architectures,
Branch instruction type is obtained according to instruction PC inquiry branch target caches in fetching level first, branch instruction is assigned to respective
Prediction module, redirect branch prediction and use return address storehouse RAS (the Return Address with dynamic configuration counter
Stack), indirect branch prediction has used the method that supplement is predicted, in indirect branch target caching IBTB (Indirect
Branch Target Buffer) prediction of failure when from unconditional branch target cache UBTB (Unconditional Branch
Target Buffer) in read last time jump target addresses and predict that conditional branch prediction delays in conditional branching target as supplement
The flag bit Tag for depositing record last time branch prediction correctness in CBTB (Conditional Branch Target Buffer) is adopted
With tri-state transfer algorithm is redirected partially, information of forecasting table (PIT) is recorded according to the decoding object information to instruction in decoding level
In (Prediction Info Table), correctness of the level according to present instruction implementing result to branch prediction results is being performed
Judged, if the prediction result of branch instruction to redirect, is entered using jump forecasting result determining device Arbiter_T
Row result judges, if the prediction result of branch instruction not redirect, uses not jump forecasting result determining device
Arbiter_N carries out result judgement, and solving branch instruction instruction delay to caused by streamline influences, and improves processor
Execution efficiency.
The embodiment of the embodiment of the present invention is described in more detail with reference to Figure of description.Below by
The embodiment being described with reference to the drawings is by exemplary, is only used for explaining invention, and is not construed as limiting the claims.
The present invention is a kind of mixed branch Predictive Design Method based on instruction classification mode, as shown in Figure 10, including：
In fetching level according to instruction PC inquiry unconditional branch target cache UBTB (Unconditional Branch
Target Buffer) or conditional branching target cache CBTB (Conditional Branch Target Buffer), divided
Branch instruction type, branch instruction is assigned to respective prediction module；
It is the prediction of the branch instruction directly redirected to unconditional jump and branch target address to redirect branch prediction to be, is jumped
Turn branch's class branch instruction predictions to redirect, by inquiring about unconditional branch target cache UBTB (Unconditional Branch
Target Buffer) branch prediction jump target addresses are obtained, while return address is recorded in dynamic configuration counter
Return address storehouse RAS (Return Address Stack) in；
It is that the subroutine call return redirected indirectly refers to unconditional jump and branch target address that returning branch prediction, which is,
The prediction of order, returning branch class branch prediction redirect, and are taken from return address storehouse RAS (Return Address Stack)
Obtain branch prediction jump target addresses；
It is the prediction of the branch instruction redirected indirectly to unconditional jump and branch target address that indirect branch prediction, which is,
Connect branch's class branch prediction to redirect, from indirect branch target caching IBTB (Indirect Branch Target Buffer)
Branch prediction jump target addresses are read, in indirect branch target caching IBTB (Indirect Branch Target
Buffer) from unconditional branch target cache UBTB (Unconditional Branch Target during prediction of failure
Buffer), middle reading last time jump target addresses are predicted as supplement；
Conditional branch prediction is to the prediction that conditional branching and branch target address are the branch instruction directly redirected, condition
Branch's class instruction redirects direction by pattern history table PHT (Patter History Table) predictions, passes through conditional branching mesh
Mark caching CBTB (Conditional Branch Target Buffer) predicted branches prediction jump target addresses, its conditional
Branch prediction state flag bit Tag is used in branch target cache CBTB (Conditional Branch Target Buffer)
Tri-state transfer algorithm is redirected partially, can preferably record the relevant information for redirecting branch instruction；
Judge whether present instruction is branch instruction according to the decoding result to instruction in decoding level, and whether carried out
Branch instruction redirects the prediction of direction and branch instruction jump target addresses, and information record in information of forecasting table (PIT)
In (Prediction Info Table)；
Level is being performed according to present instruction implementing result and unconditional branch target cache UBTB (Unconditional
Branch Target Buffer), conditional branching target cache CBTB (Conditional Branch Target Buffer)
The correctness of branch prediction results is carried out with the information of record in information of forecasting table (PIT) (Prediction Info Table)
Judge, if the prediction result of branch instruction to redirect, is tied using jump forecasting result determining device Arbiter_T
Fruit judges, if the prediction result of branch instruction not redirect, uses not jump forecasting result determining device Arbiter_N
Carry out result judgement；
If branch instruction predictions result is correct, streamline continues fetching and performed, if there is mistake in prediction result,
Cancel false command in this stage, going out again fetching from correct destination address performs.
It is as shown in Figure 1 branch predicting system design architecture, unconditional branch target cache UBTB (Unconditional
Branch Target Buffer) in record the jump target addresses of unconditional jump branch instruction, conditional branching target is delayed
With depositing jump target that conditional jump branch instruction is record in CBTB (Conditional Branch Target Buffer)
Location, return address storehouse RAS (Return Address Stack) is return address storehouse, records return type branch instruction
Jump target addresses, global branch history register GBHR (Global Branch History Register) record branch
The history jump information of instruction.Pattern history table PHT (Patter History Table) records conditional jump branch instruction
Direction prediction information.Indirect branch target caching IBTB (Indirect Branch Target Buffer) records indirectly
Jump target addresses corresponding to branch instruction PC values.
In fetching level according to instruction PC inquiry unconditional branch target cache UBTB (Unconditional Branch
Target Buffer) or conditional branching target cache CBTB (Conditional Branch Target Buffer), divided
Branch instruction type, branch instruction is assigned to respective prediction module.It is to unconditional jump and branch's mesh to redirect branch prediction
Mark address is the prediction of the branch instruction directly redirected, redirects branch's class branch instruction predictions and redirects, by inquiring about unconditional point
Branch target cache UBTB (Unconditional Branch Target Buffer) obtains jump target addresses, while return
Address is recorded in return address storehouse RAS (Return Address Stack)；Returning branch prediction is to unconditional jump
And branch target address is the prediction of the subroutine call return instruction redirected indirectly, returning branch class branch prediction redirects, and
Jump target addresses are obtained from return address storehouse RAS (Return Address Stack)；Indirect branch prediction is to nothing
Conditional jump and branch target address are the prediction of the branch instruction redirected indirectly, and indirect branch class branch prediction redirects, from
Jump target addresses are read in IBTB (Indirect Branch Target Buffer), in IBTB (Indirect Branch
Target Buffer) prediction of failure when last time is read from the UBTB (Unconditional Branch Target Buffer)
Jump target addresses are predicted as supplement；Conditional branch prediction is that conditional branching and branch target address are divided for what is directly redirected
Zhi Zhiling prediction, the instruction of conditional branching class predict the side of redirecting by pattern history table PHT (Patter History Table)
To, pass through CBTB (Conditional Branch Target Buffer) predict jump target addresses.
It is illustrated in figure 2 and redirects branch prediction part design architecture, Call PC branch's jump target addresses is recorded in
In UBTB (Unconditional Branch Target Buffer), UBTB (Unconditional Branch are inquired about
Target Buffer) form obtains branch target address T_addr, and the PC addresses next instruction are recorded in return simultaneously
It is because being passed through in specific implementation process Program used here as 8 in address stack RAS (Return Address Stack) form
Call instructions have delay groove below after crossing compiling, comprising a delay instruction, therefore are performed after the return of When subroutine return instruction
Next instruction PC values be Call PC+8.
Returning branch predicted portions design architecture is illustrated in figure 3, when running into a RET or RETL instructions, by looking into
Ask unconditional branch target cache UBTB (Unconditional Branch Target Buffer) or conditional branching target is delayed
CBTB (Conditional Branch Target Buffer) is deposited it is known that this is a subroutine return instruction, therefore is needed
An instruction is taken out from return address storehouse RAS (Return Address Stack) to redirect as the branch of return instruction
Destination address T_addr.
Indirect branch predicted portions design architecture is illustrated in figure 4, when running into a JMPL instruction, passes through index module
Index module generation search terms retrieval IBTB (Indirect Branch Target Buffer) find current branch instruction
Branch target address T_addr, while UBTB (Unconditional Branch Target Buffer) can also retrieve generation
One T_addr, performed by the one of branch target address fetching for being used as prediction of T_addr select modules selection,
What is preserved in UBTB (Unconditional Branch Target Buffer) is that current branch instruction JMPL is once held upper
Branch target address during row, branch target address caused by preferred IBT, as IBTB (Indirect Branch Target
Buffer the jump target addresses information of relative branch instruction is can not find in), then relevant information is notified to give T_addr select
Module, with selecting branch's jump target that the last time performs in UBTB (Unconditional Branch Target Buffer)
Location is as prediction result.
Conditional branch prediction part design architecture is illustrated in figure 5, GBHR is global branch history shift register, is used for
The branch instruction that record occurs recently redirects historical information, represents that branch redirects with 1, represents that branch does not occur with 0
Redirect.PHT (Patter History Table) records conditional branch instructions historical information, and is worked as by these information predictions
Whether preceding branch instruction redirects.It is the branch instruction that directly redirects when running into a conditional branching and branch target address
Afterwards, search terms are generated by index module Index module and retrieves branch history pattern table PHT (Patter History
Table), the prediction result whether current branch redirects is obtained, according to this result in CBTB (Conditional
Branch Target Buffer) branch's jump target addresses for providing and branch select between address when not redirecting, as
Next proceed to the address of fetching execution.
If Fig. 6 is that Tag states redirect tri-state conversion partially in CBTB (Conditional Branch Target Buffer)
Algorithm.Branch target cache CBTB (Conditional Branch Target Buffer) is specifically used to record condition and redirected point
Zhi Zhiling jump target addresses information.CBTB (Conditional Branch Target Buffer) is in conditional branch prediction
Middle use.CBTB (Conditional Branch Target Buffer) is with have recorded branch's jump target of conditional branching
Location.Due to it with UBTB (Unconditional Branch Target Buffer) independently of each other, and only record condition branch
The branch instruction of type, therefore branch pattern mark B_type positions need not be set, but because it is conditional branching, therefore need
Flag bit Tag is set to assist CBTB (Conditional Branch Target Buffer) to update, Tag is used for recording phase
The correctness that the branch instruction answered was predicted in last time, 0 is correctly remained, mistake puts 1.Redirecting tri-state transfer algorithm has three shapes partially
State, represented with a bit register, three states using CBTB (Conditional Branch Target Buffer) list item n as
Example, initial Tag states are 0, and state remains 0 when writing the branch instruction information redirected for the first time.When Tag states are 0, such as
The branch instruction of fruit record does not have to redirect when performing next time, and Tag states are set to 1, otherwise remain 0.Tag states
For 1 when, if the branch instruction of record does not have to redirect when performing next time, empty the information of this list item n records, it is multiple
Position is original state, and otherwise Tag states are set to 0.
, it is necessary to PHT (Patter History Table) and CBTB in the prediction of this kind of branch instruction of conditional branching
(Conditional Branch Target Buffer) cooperates to completion branch instruction and redirects direction and jump target
The prediction of address.PHT (Patter History Table) is used for the direction of predicted condition branch instruction, CBTB
(Conditional Branch Target Buffer) carrys out jump target addresses when predicted condition branch instruction redirects.
Because it is the prediction made to same branch instruction, therefore their search terms must be consistent, using same by branch
The index entry that history and branch address are generated by Index module.PHT (Patter History Table) makes point
The prediction that Zhi Zhiling is not redirected, makes the prediction that branch instruction redirects again, and CBTB (Conditional Branch Target
Buffer) jump target addresses of the branch instruction only redirected to PHT (Patter History Table) predictions are made
Prediction, therefore corresponding relation between the two will necessarily have certain deviation, be embodied in：
PHT 1. (Patter History Table) predicting branch instructions redirect, CBTB (Conditional
Branch Target Buffer) in there is no the jump target addresses of respective branch instructions；
PHT 2. (Patter History Table) predicting branch instructions redirect, CBTB (Conditional
Branch Target Buffer) in have the jump target addresses of respective branch instructions；
PHT 3. (Patter History Table) predicting branch instructions do not redirect, CBTB (Conditional
Branch Target Buffer) in there is no the jump target addresses of respective branch instructions；
PHT 4. (Patter History Table) predicting branch instructions do not redirect, CBTB (Conditional
Branch Target Buffer) in have the jump target addresses of respective branch instructions.
More than in four kinds of states, 2., 3. state that state has been, 1., 4. state is to belong to devious to entangle in time
Positive state, if PHT (Patter History Table) predictions are correct, 1. state can bring negative shadow to branch prediction
Ring, and 4. state has no adverse effect to branch prediction.
If 1. the prediction of conditional branching is in state, hold according to the order that branch redirects does not occur originally continuing fetching
OK, because PHT (Patter History Table) has the possibility of prediction error, then the instruction that continuation order fetching performs can
Can be in correct instruction execution path.If 4. the prediction of conditional branching is in state, according to not occurring point for prediction
The order that branch redirects continues fetching and performed.
The renewal of predicted state is using two saturated counters algorithms in PHT (Patter History Table),
When state is in saturation state, only prediction of failure can just change the result of branch prediction twice, therefore can be well
Record always redirect, always do not redirect and have redirect strongly skewed popularity branch instruction information.CBTB
The renewal of (Conditional Branch Target Buffer) using redirecting tri-state transfer algorithm, this algorithm energy partially
Record redirects the relevant information of branch instruction well.1. if the prediction of conditional branching is in state, and PHT (Patter
History Table) predict correctly, then when predicting next time in CBTB (Conditional Branch Target Buffer)
The jump target addresses of recorded dependent instruction, jump out state 1..If prediction of the conditional branch prediction to certain branch instruction
In state 4., then at most state is in 4. twice in succession, in CBTB (Conditional Branch Target Buffer)
The record information of correlation will be removed.
RAS (Return Address Stack) dynamic configuration counter allocation algorithm is illustrated in figure 7, counter exists
Some list item when use and in unfixed sensing RAS (Return Address Stack), only exists
When counter uses, counter is just locked, and counting is used in fixed sensing RAS (Return Address Stack)
The list item of device, in order to improve the utilization rate of counter while save resource.RAS_index is RAS (Return
Address Stack) list item pointer, Counter_index be counter Counter list item pointer-digit represent be
The list item label that pointer RAS_index is pointed in RAS (Return Address Stack).RAS_index original states point to 0
Position, Counter_index point to first counter 1, need to write return when running into a subroutine call branch instruction
A upper table in the branch target address T_addr of instruction and this destination address and RAS (Return Address Stack)
The address contents of item are unequal, then RAS_index pointers add 1, if the flag flag bits of a upper list item are 1, then say
A bright upper list item has used counter, polyphony some subfunction of attaching most importance to, and finishes to repeat to call in current PC, starts
Another subfunction is have invoked, Counter_index pointers add 1.If necessary to write return instruction branch target address and
The address contents of a upper list item are equal then current RAS (Return Address in RAS (Return Address Stack)
Stack) list item flag put 1, Counter_index sensing counter contents add 1, RAS_index pointers keep it is constant.Work as chance
To a subroutine call return instruction, it is necessary to the branch target address in the list item of RAS_index sensings be read, if this table
Flag corresponding to is 0, then RAS_index pointers subtract 1 after reading.If flag corresponding to this list item is 1, read
Counter_index pointers subtract 1 after finishing, if Counter_index pointers are changed into 0 after subtracting 1, it is also necessary to which this table is corresponding
Flag is set to 0.Original state is returned to if RAS (Return Address Stack) writes completely to restart.Counter_index
First counter covering write-in is returned after writing completely.
It is illustrated in figure 8 prediction result inspection and corrects flow, records and work as in BPM (Branch Predict Module)
The historical information of the preceding branch instruction redirected, remember in information of forecasting table (PIT) (Prediction Info Table) form
The information of branch instruction in current pipeline is recorded, two modules of Arbiter_N, Arbiter_T are entered to the result of branch prediction
Row checks renewal.For the PC values obtained in fetching level, predicted first by BPM (Branch Predict Module), if
Prediction hit, then it is assumed that this instruction is branch instruction and once occurred, then according to BPM (Branch Predict
Module) branch target address of prediction is performed from new address fetching, and the PC of this branch instruction is recorded in prediction letter
Cease in table (PIT) (Prediction Info Table) table.If do not hit, then it is assumed that this is not branch instruction either one
The branch instruction not occurred before bar, then needs to use decoding logic to judge, if present instruction is branch instruction
Words, it is recorded in information of forecasting table (PIT) (Prediction Info Table) table.After branch instruction is finished, look into
Ask information of forecasting table (PIT) (Prediction Info Table) form, if the PC currently performed in Branch PC forms,
Then continue branch outcome checking.If this branch instruction result is predicted not occur using Arbiter_N modules
As a result judge, judge if this branch instruction result is predicted result to occur, using Arbiter_T modules.
If Fig. 9 is prediction result evaluation algorithm, if this branch instruction result uses Arbiter_N moulds not occur
Block is predicted result judgement, if this branch instruction result is predicted result using Arbiter_T modules and sentenced to occur
It is disconnected.In Arbiter_N modules, if the PC values currently performed are at information of forecasting table (PIT) (Prediction Info Table)
In do not hit, then branch instruction performs correct, if the PC values currently performed are in information of forecasting table (PIT) (Prediction
Info Table) in hit, show that this branch instruction performs mistake, then remove related streamline, update information of forecasting table (PIT)
(Prediction Info Table) form, while PC manage module go out again fetching from correct PC addresses and performed.
In Arbiter_T modules, if the PC values currently performed are in information of forecasting table (PIT) (Prediction Info Table)
Do not hit, show that branch instruction performs mistake, then remove related streamline, renewal information of forecasting table (PIT) (Prediction
Info Table) table, while PC manage module go out again fetching from correct PC addresses and performed.If currently perform
PC values are hit in information of forecasting table (PIT) (Prediction Info Table), and target address prediction is correct, then branch
Instruction performs correct, renewal information of forecasting table (PIT) (Prediction Info Table) table, if destination address is incorrect,
Branch instruction performs mistake, then removes related streamline, updates information of forecasting table (PIT) (Prediction Info Table) table,
PC manage module go out again fetching from correct PC addresses and performed simultaneously.
In summary, the present invention devises a kind of sort-type mixed branch prediction system based on SPARC V8 architectures
System, by classifying to branch instruction, preferably can take more excellent branch prediction schemes, energy for different branch instructions
It is enough to have been applied in SPARC associative processors, pass through with less hardware resource, raising branch prediction accuracy, the present invention
Branch prediction accuracy is improved, the performance of processor is improved, is widely used in space industry.
Claims (7)
- A kind of 1. sort-type mixed branch forecasting system based on SPARC V8 architectures, it is characterised in that including：PC is managed Module, branch instruction enquiry module, branch instruction predictions module, branch instruction information logging modle, branch instruction predictions result Judge module, renewal and correction module, unconditional branch target cache UBTB, conditional branching target cache CBTB, return Address stack RAS, indirect branch target caching IBTB, pattern history table PHT, information of forecasting table (PIT)；Unconditional branch target cache UBTB, store branch instruction type corresponding to unconditional jump branch instruction PC values and believe Breath, and jump target addresses corresponding to unconditional jump branch instruction PC values；Conditional branching target cache CBTB, branch instruction type information corresponding to conditional jump branch instruction PC values is stored, with And jump target addresses corresponding to conditional jump branch instruction PC values；Return address storehouse RAS, store and return to destination address corresponding to returning branch instruction PC values；Indirect branch target caches IBTB, stores jump target addresses corresponding to indirect branch instruction PC values；Pattern history table PHT, store indirect branch instruction PC values corresponding to branch redirect direction；Information of forecasting table (PIT), store information of forecasting corresponding to branch instruction PC values；PC management modules, receive branch prediction results, renewal that instruction PC values, the branch instruction predictions module of outside input are sent And the branch prediction results feedback information that correction module is sent, the branch prediction knot that wherein branch instruction predictions module is sent Fruit, including, whether branch instruction predictions redirect, branch instruction predictions jump target addresses；Renewal and correction module are sent Branch prediction results feedback information, including branch instruction PC values, branch prediction results correctness, branch instruction redirect with No, branch instruction jump target addresses；In branch predicting system initial launch, if what renewal and correction module were sent Branch prediction results mistake in branch prediction results feedback information, then give up the branch prediction knot that branch instruction predictions module is sent Fruit, if then judging that branch instruction redirects in renewal and the branch prediction results feedback information that correction module is sent, Branch instruction jump target addresses are as next in the branch prediction results feedback information that renewal and correction module are sent Bar instruction PC values are sent into branch instruction enquiry module；If the branch prediction results feedback letter that renewal and correction module are sent Branch prediction results mistake in breath, then give up the branch prediction results that branch instruction predictions module is sent, if then judged more Branch instruction does not redirect in the branch prediction results feedback information that new and correction module is sent, then renewal and error correcting Branch instruction PC values calculate plus fixed numerical value of N in the branch prediction results feedback information that module is sent produces next instruction PC values, and this next instruction PC value is sent into branch instruction enquiry module；What if renewal and correction module were sent Branch prediction results are correct in branch prediction results feedback information, if then judging the branch that branch instruction predictions module is sent Branch instruction predictions redirect in prediction result, then branch instruction is pre- in branch prediction results branch instruction predictions module sent Survey jump target addresses and be sent into branch instruction enquiry module as next instruction PC value；If renewal and correction module are sent Branch prediction results are correct in the branch prediction results feedback information come, if then judging what branch instruction predictions module was sent Branch instruction predictions do not redirect in branch prediction results, then instruction PC values outside being sent into add the numerical value of N meter of the fixation Calculate and produce next instruction PC value, and it is sent into branch instruction enquiry module；Next instruction PC value is delivered into outside simultaneously To being instructed corresponding to next instruction PC value into row decoding, by the Instruction decoding information back branch instruction decoding information after decoding Logging modle, it is outside will next instruct after Instruction decoding information performs corresponding to PC values, obtain execution result information and be sent into divide Branch branch prediction result judge module；Branch instruction enquiry module, the next instruction PC values that PC management modules are sent are received, according to unconditional branch mesh The instruction PC values of mark caching UBTB and conditional branching target cache CBTB storages branch corresponding with described next instruction PC value Instruction type, branch instruction type information corresponding with the next instruction PC value that PC management modules are sent is obtained, then by under One instruction PC value and branch instruction type information are sent into branch instruction predictions module；Branch instruction predictions module, receive next instruction PC value and branch instruction type that branch instruction enquiry module is sent Information, if branch instruction type information show current next instruction PC values corresponding to branch instruction, be unconditional jump and Branch target address is the branch instruction directly redirected, then the branch instruction predictions redirect, then by inquiring about unconditional branch Target cache UBTB, branch instruction predictions jump target addresses corresponding with this next instruction PC value are obtained, while according to institute State the numerical value of N that next instruction PC value adds the fixation used in PC management modules and obtain return ground corresponding with the branch instruction Location, then the return address is recorded in the storehouse RAS of return address；If branch instruction type information shows current next Branch instruction corresponding to instructing PC values, it is the branch instruction of return type, then takes out return address from the storehouse RAS of return address Branch instruction predictions jump target addresses of the return address of stack top as the return type in storehouse RAS；If branch Instruction type information shows currently branch instruction corresponding to next instruction PC value, is indirect branch instruction, then the indirect branch Branch prediction is redirected, and it is pre- that branch instruction corresponding to this next instruction PC value is then read from indirect branch target caching IBTB Jump target addresses are surveyed, are divided if do not read in indirect branch target caches IBTB corresponding to this next instruction PC value When branch branch prediction jump target addresses are IBTB prediction of failure, then read from unconditional branch target cache UBTB under this Branch instruction predictions jump target addresses corresponding to one instruction PC value, this mode are defined as supplement prediction；If branch refers to Make type information show currently branch instruction corresponding to next instruction PC value, be conditional branch instructions, then pass through query pattern History lists PHT obtains branch instruction predictions corresponding with this next instruction PC value and redirects direction, the branch instruction predictions side of redirecting Whether redirect to i.e. branch instruction predictions, then obtained and described next instruction by querying condition branch target cache CBTB Branch instruction predictions jump target addresses corresponding to PC values；The next instruction PC values in branch instruction predictions module, Branch instruction predictions corresponding to the next instruction PC values redirect direction and branch instruction predictions jump target addresses are sent into Branch instruction information logging modle, while next instruction PC values in branch instruction predictions module, described next Branch instruction predictions corresponding to instruction PC values redirect direction and branch instruction predictions jump target addresses are sent into PC management modules；Branch instruction information logging modle, receive next instruction PC values that branch instruction predictions module sends, it is described under Branch instruction predictions corresponding to one instruction PC value redirect direction and branch instruction predictions jump target addresses, receive outside defeated The next instruction PC value corresponding instruction decoding informations entered, according to Instruction decoding letter corresponding to described next instruction PC value Breath judges whether present instruction is branch instruction, and whether has carried out that branch instruction redirects direction and branch instruction redirects mesh The prediction of address is marked, and judged result information record in information of forecasting table (PIT), then the next finger received PC values are made to be sent into branch instruction predictions result judge module；Branch instruction predictions result judge module, including：Jump forecasting result determining device Arbiter_T and not jump forecasting result Determining device Arbiter_N；Branch instruction predictions result judge module, receive next that branch instruction information logging modle is sent and instruct PC values, connect The execution result information of the instruction of outside input is received, the execution result information of the wherein instruction of outside input includes, branch instruction Direction, branch instruction jump target addresses are redirected, knot is performed according to instruction corresponding to the next instruction PC values received The information recorded in fruit and information of forecasting table (PIT) is judged the correctness of branch prediction results, i.e., if the execution of instruction Branch instruction redirects direction to redirect in object information, then pre- using redirecting in branch instruction predictions result judge module The correction judgement that result determining device Arbiter_T carries out branch prediction results is surveyed, if divided in the execution result information of instruction Zhi Zhiling redirects direction not redirect, then is sentenced using the not jump forecasting result in branch instruction predictions result judge module Disconnected device Arbiter_N carries out the correction judgement of branch prediction results, branch prediction correctness information is obtained after judgement, then Described next instruction PC value, branch prediction correctness information, branch instruction are redirected direction, branch instruction jump target Location is sent to renewal and correction module；Renewal and correction module, receive next instruction PC values, branch that branch instruction predictions result judge module is sent Prediction correctness information, branch instruction redirect direction, branch instruction jump target addresses, if branch prediction is correct, profit The next instruction PC values, the branch instruction sent with branch instruction predictions result judge module redirect direction, branch instruction Jump target addresses information is delayed to unconditional branch target cache UBTB, conditional branching target cache CBTB, indirect branch target The corresponding information deposited in IBTB, pattern history table PHT, information of forecasting table (PIT) is updated, then by next instruction PC value, Whether branch prediction correctness information, branch instruction redirect, branch instruction jump target addresses are sent into PC management modules；If Branch prediction results mistake, then after producing error correcting signal, the error correcting signal is sent into outside, then by next finger Making PC values, branch instruction PC values, the branch that will be fed into PC management modules are pre- as the branch instruction PC values for being sent into PC management modules Survey correctness information, branch instruction redirects direction, branch instruction jump target addresses are sent into PC management modules.
- 2. a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures according to claim 1, it is special Sign is：The branch instruction predictions of return type, which have used, in described branch instruction predictions module carries dynamic configuration counter Return address storehouse RAS；Return address storehouse RAS with dynamic configuration counter, storehouse when dynamic configuration counter is not used Pointer will not point to any stack of the storehouse in the storehouse RAS of return address, the only counter in the storehouse RAS of return address When use, counter is just locked, and the storehouse of counter is used in the sensing return address storehouse RAS that stack pointer is fixed That stack.
- 3. a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures according to claim 1, it is special Sign is, the prediction conditional branch target cache CBTB of described branch instruction predictions module conditional branch instruction renewal Use and redirected tri-state transfer algorithm partially：It is branch prediction state in conditional branch instructions prediction conditional branch target cache CBTB to redirect tri-state transfer algorithm partially Flag bit Tag state transition algorithms, branch prediction state flag bit Tag be used for record branch instruction it is upper once predict it is correct Property, 0 is correctly remained, mistake puts 1, and redirecting tri-state transfer algorithm partially there are three states, is represented with a bit register, when condition point When branch target cache CBTB list items n initial Tag states are 0, state is protected when writing the branch instruction information redirected for the first time Hold as 0, when Tag states after first time are 0, if not having to redirect when the branch instruction of record is performing next time Tag states are set to 1, otherwise remain 0, when Tag states after first time are 1, if the branch instruction of record is next time Do not have to redirect during execution, then empty the information of this list item n records, be reset to original state, otherwise Tag states are set to 0.
- 4. a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures according to claim 1, it is special Sign is, in described branch instruction predictions result judge module, jump forecasting result determining device Arbiter_T evaluation algorithms are such as Under：If next instruction PC value, inquires about in information of forecasting table (PIT) and does not have described in branch instruction predictions result judge module There are the next instruction PC values, then branch instruction performs mistake, is judged as branch misprediction；If the next instruction PC values are inquired about in information of forecasting table (PIT) the next instruction PC values, then branch instruction performs correct, is judged as that branch is pre- Survey correct；Jump forecasting result determining device Arbiter_N evaluation algorithms are not as follows：If next instruction PC value, inquires about in information of forecasting table (PIT) and does not have described in branch instruction predictions result judge module There are the next instruction PC values, then branch instruction performs correct, is judged as that branch prediction is correct；If the next instruction PC values are inquired about in information of forecasting table (PIT) occurrence, then branch instruction performs mistake, is judged as branch misprediction.
- 5. a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures according to claim 1, it is special Sign is：The numerical value of N of the fixation determines according to the treatable command length of processor institute of operation branch predicting system.
- 6. a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures according to claim 1, it is special Sign is：The numerical value of N of the fixation takes one of 1 or 4 or 8.
- 7. a kind of sort-type mixed branch forecasting system based on SPARC V8 architectures according to claim 1, it is special Sign is：The next instruction PC values, the branch instruction sent using branch instruction predictions result judge module redirect direction, Branch instruction jump target addresses information to unconditional branch target cache UBTB, conditional branching target cache CBTB, indirectly point Corresponding information in branch target cache IBTB, pattern history table PHT, information of forecasting table (PIT) is updated, and the method for renewal is root The next instruction PC values sent according to branch instruction predictions result judge module, branch instruction predictions result judge module The branch instruction jump target addresses sent replace to correspond in UBTB, CBTB, IBTB divides corresponding to the next instruction PC values Zhi Zhiling jump target addresses, the next instruction PC values sent according to branch instruction predictions result judge module, PIT Described in next instruction PC values corresponding to branch instruction predictions information deletion, sent according to branch instruction predictions result judge module The branch instruction that branch instruction predictions result judge module is sent, is redirected direction and replaced by the next instruction PC values come Branch instruction corresponding to the next instruction PC values are corresponded in PHT redirects direction.
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| CN111176729A (en) * | 2018-11-13 | 2020-05-19 | 深圳市中兴微电子技术有限公司 | Information processing method and device and computer readable storage medium |
| US11182166B2 (en) | 2019-05-23 | 2021-11-23 | Samsung Electronics Co., Ltd. | Branch prediction throughput by skipping over cachelines without branches |
| CN111124493A (en) * | 2019-12-17 | 2020-05-08 | 天津国芯科技有限公司 | Method and circuit for reducing program jump overhead in CPU |
| CN111258649B (en) * | 2020-01-21 | 2022-03-01 | Oppo广东移动通信有限公司 | Processor, chip and electronic equipment |
| CN111459551B (en) * | 2020-04-14 | 2022-08-16 | 上海兆芯集成电路有限公司 | Microprocessor with highly advanced branch predictor |
| CN112035170B (en) * | 2020-08-20 | 2021-06-29 | 海光信息技术股份有限公司 | Method and system for branch predictor |
| CN112905242B (en) | 2021-03-23 | 2022-12-06 | 浙江大华技术股份有限公司 | Branch path jumping method, device, storage medium and electronic device |
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