CN105718241A - SPARC V8 system structure based classified type mixed branch prediction system - Google Patents
SPARC V8 system structure based classified type mixed branch prediction system Download PDFInfo
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- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/35—Indirect addressing
Abstract
The invention discloses an SPARC V8 system structure based classified type mixed branch prediction system. Firstly, a branch target buffer is queried according to PC values of instructions at an instruction fetching stage to obtain branch instruction types; the branch instructions are dispatched to respective prediction modules; a return address stack (RAS) with a dynamic configuration counter is used in skip branch prediction; a complementary prediction method is used in indirect branch prediction; a tag recording correctness of previous branch prediction in a conditional branch target buffer (CBTB) adopts a partial skip three-state conversion algorithm in conditional branch prediction; decoding result information of the instructions are recorded in a prediction information table (PIT) at a decoding stage; a judgment is made at an execution stage; if a prediction result of the branch instructions is that the skip occurs, the result judgment is made by using a skip prediction result arbiter Arbiter_T; and if the prediction result of the branch instructions is that the skip does not occur, the result judgment is made by using a non-skip prediction result arbiter Arbiter_N. Therefore, the instruction delay influence of the branch instructions on an assembly line is eliminated and the execution efficiency of a processor is improved.
Description
Technical field
The present invention relates to a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture, give a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture especially for space industry wide variety of SPARC processor, namely adopt the mixed branch prediction scheme of instruction classification formula.
Background technology
In field of processors, SPARC architecture, as one of the classical representative of risc processor, occupies highly important status.Microprocessor based on SPARC framework is with good expansibility, and has been widely used in aviation, communication and various Embedded Application field at present.Therefore develop there is higher performance can have good application prospect towards the SPARC processor of various target customer's application demands.
The research of current processor architecture achieves very big development, pipelining greatly enhances instruction level parallelism (InstructionLevelParallelism), but being as the continuous complicated of application demand, the research of high-performance processor remains the focus of academia research.It is a variety of because have that constraint high-performance processor develops, and wherein the research about instruction level parallelism is one of key factor of exploitation high-performance processor, and the key factor affecting instruction level parallelism is exactly the branch instruction existed in program.
The execution of processor pipeline Program is had material impact by branch instruction, the branch instruction redirected will change the direction of instruction stream in streamline again, this will introduce more bubble (bubble) in a pipeline, in modern processor architectures, hardware cost and power consumption penalty that branch instruction is brought increase also with the increase of the width (issuewidth) of pipeline depth and streamline firing order.Therefore one of study hotspot being always up hot topic about the research of branch prediction techniques.
Branch prediction techniques is to improve the important means of processor performance, and its purpose is to weaken the control dependence (controldependence) between instruction, thus improving instruction level parallelism, improves processor performance.The increase of pipeline depth will deepen the branch instruction impact on track performance, add the application of instruction multi-emitting technology (MultipleInstructionLaunch), the impact of track performance is increased by branch instruction further, and therefore the development of branch prediction techniques is a kind of inevitable.
The principal element promoting branch prediction techniques development has: 1, the appearance of new opplication and the proposition of new processor structure need to be suitable for their new forecasting mechanism.2, along with the development of deep submicron process, the problem of power consumption of processing unit is more and more important, and this is accomplished by weighing between the efficiency and power consumption of processor branch prediction.3, the application of the new technique such as super flowing water and superscale makes processor that the demand of branch prediction accuracies is still very big.
Branch prediction techniques not only to consider its prediction accuracy, it is also contemplated that the impact of hardware spending that it brings to processor and clock delay, existing branch prediction techniques is often due to hardware size is too big, prediction algorithm is excessively complicated, the not high reason of branch prediction accuracy constrains processor performance improve.
Summary of the invention
The technology of the present invention solves problem: overcome the deficiencies in the prior art, a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture is proposed, namely can improve the accuracy of branch instruction predictions, hardware size can be reduced again, not make prediction algorithm excessively complicated.
The technical solution of the present invention is:
The present invention is made up of following module: PC manages module, branch instruction enquiry module, branch instruction predictions module, branch instruction information logging modle, branch instruction predictions result judge module, unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), conditional branching target cache CBTB (ConditionalBranchTargetBuffer), return address storehouse RAS (ReturnAddressStack), indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer), pattern history table PHT (PatterHistoryTable), information of forecasting table (PIT) (PredictionInfoTable)；
Unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) stores the branch instruction type information that unconditional jump branch instruction PC value is corresponding and the jump target addresses that unconditional jump branch instruction PC value is corresponding；
Conditional branching target cache CBTB (ConditionalBranchTargetBuffer) stores the branch instruction type information that conditional jump branch instruction PC value is corresponding and the jump target addresses that conditional jump branch instruction PC value is corresponding；
Return address storehouse RAS (ReturnAddressStack) stores and returns the return destination address that branch instruction PC value is corresponding；
Indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer) stores the jump target addresses that indirect branch instruction PC value is corresponding；
The branch that pattern history table PHT (PatterHistoryTable) stores indirect branch instruction PC value corresponding redirects direction；
Information of forecasting table (PIT) (PredictionInfoTable) stores the information of forecasting that branch instruction PC value is corresponding；
PC manages module, the branch prediction results feedback information that branch prediction results, renewal and the correction module that the reception instruction PC value of externally input, branch instruction predictions module are sent here is sent here.The branch prediction results that wherein branch instruction predictions module is sent here, including, whether branch instruction predictions redirects, branch instruction predictions jump target addresses, the branch prediction results feedback information that renewal and correction module are sent here, including branch instruction PC value, branch prediction results correctness, whether branch instruction redirects, branch instruction jump target addresses, when branch predicting system initial launch, PC manages module and calculates generation next instruction PC value according to externally input instruction PC value plus a fixing numerical value of N, this fixing numerical value of N is with the treatable command length of processor, and the branch prediction algorithms taked is relevant, then next instruction PC value is sent into branch instruction enquiry module；If branch prediction results mistake in the branch prediction results feedback information that renewal and correction module are sent here, then give up the branch prediction results that branch instruction predictions module is sent here, if then judging that in the branch prediction results feedback information that renewal and correction module are sent here, branch instruction redirects, then in branch prediction results feedback information renewal and correction module sent here, branch instruction jump target addresses sends into branch instruction enquiry module as next instruction PC value；If branch prediction results mistake in the branch prediction results feedback information that renewal and correction module are sent here, then give up the branch prediction results that branch instruction predictions module is sent here, if then judging that in the branch prediction results feedback information that renewal and correction module are sent here, branch instruction does not redirect, in the branch prediction results feedback information then renewal and correction module sent here, branch instruction PC value calculates plus fixing numerical value of N said before and produces next instruction PC value, and its feeding branch instruction enquiry module；If branch prediction results is correct in the branch prediction results feedback information that renewal and correction module are sent here, if then judging that in the branch prediction results that branch instruction predictions module is sent here, branch instruction predictions redirects, then in branch prediction results branch instruction predictions module sent here, branch instruction predictions jump target addresses sends into branch instruction enquiry module as next instruction PC value；If branch prediction results is correct in the branch prediction results feedback information that renewal and correction module are sent here, if then judging that in the branch prediction results that branch instruction predictions module is sent here, branch instruction predictions does not redirect, the instruction PC value then outside sent into calculates plus fixing numerical value of N said before and produces next instruction PC value, and it is sent into branch instruction enquiry module；Next instruction PC value is delivered to the outside instruction to this instruction PC value correspondence simultaneously decode, by the Instruction decoding information back branch instruction decoding information logging modle after decoding, the outside Instruction decoding information that this instruction PC value is corresponding is sent into external command performance element and is performed, and execution result information is sent into branch instruction predictions result judge module；
Branch instruction enquiry module, receive PC and manage the instruction PC value that module is sent here, according to the branch instruction type that unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) and conditional branching target cache CBTB (ConditionalBranchTargetBuffer) the instruction PC value stored is corresponding with this instruction PC value, obtain the branch instruction type information corresponding with the instruction PC value that PC management module is sent here, then instruction PC value and branch instruction type information are sent into branch instruction predictions module；
Branch instruction predictions module, receive instruction PC value and branch instruction type information that branch instruction enquiry module is sent here, if branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it is unconditional jump and branch target address is the branch instruction directly redirected, then this branch instruction predictions redirects, then pass through inquiry unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), obtain the branch instruction predictions jump target addresses corresponding with this instruction PC value, manage, plus PC, the fixing numerical value of N used in module according to this instruction PC value simultaneously and obtain the return address corresponding with this branch instruction, then return address is recorded in return address storehouse RAS (ReturnAddressStack)；If branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it is the branch instruction of return type, then from return address storehouse RAS (ReturnAddressStack), takes out the return address branch instruction predictions jump target addresses as this return type；If branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it it is indirect branch instruction, then the prediction of this indirect branch instruction redirects, then from indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer), read the branch instruction predictions jump target addresses that this instruction PC value is corresponding, without when reading branch instruction predictions jump target addresses corresponding to this instruction PC value and IBTB (IndirectBranchTargetBuffer) prediction of failure in indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer), then from unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), read the branch instruction predictions jump target addresses that this instruction PC value is corresponding, this mode is called supplements prediction；If branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it it is conditional branch instructions, then obtain the branch instruction predictions corresponding with this instruction PC value by query pattern history lists PHT (PatterHistoryTable) and redirect direction, then pass through querying condition branch target cache CBTB (ConditionalBranchTargetBuffer) and obtain the branch instruction predictions jump target addresses corresponding with this instruction PC value；The branch instruction predictions of the instruction PC value in branch instruction predictions module, this instruction PC value correspondence is redirected direction and branch instruction predictions jump target addresses sends into branch instruction information logging modle, the branch instruction predictions of the instruction PC value in branch instruction predictions module, this instruction PC value correspondence is redirected direction simultaneously and branch instruction predictions jump target addresses sends into PC management module；
Branch instruction information logging modle, receive the instruction PC value that branch instruction predictions module is sent here, the branch instruction predictions of this instruction PC value correspondence redirects direction and branch instruction predictions jump target addresses, receive the corresponding Instruction decoding information of instruction PC value of externally input, judge whether present instruction is branch instruction according to the Instruction decoding information that instruction PC value is corresponding, and whether have be carried out branch instruction and redirect direction and the prediction of branch instruction jump target addresses, and information record in information of forecasting table (PIT) (PredictionInfoTable), then the instruction PC value received is sent into branch instruction predictions result judge module；
Branch instruction predictions result judge module, receive the instruction PC value that branch instruction information logging modle is sent here, receive the execution result information of the instruction of externally input, wherein the execution result information of the instruction of externally input includes, branch instruction redirects direction, branch instruction jump target addresses, result and unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) is performed according to present instruction, in conditional branching target cache CBTB (ConditionalBranchTargetBuffer) and information of forecasting table (PIT) (PredictionInfoTable), the correctness of branch prediction results is judged by the information of record, if namely in the execution result information of the instruction of externally input, branch instruction direction redirects, jump forecasting result diagnosis apparatus Arbiter_T is then used to carry out the correction judgement of branch prediction results, if branch instruction direction does not redirect in the execution result information of the instruction of externally input, not jump forecasting result diagnosis apparatus Arbiter_N is then used to carry out the correction judgement of branch prediction results, obtain branch prediction correctness information, then present instruction PC value, branch prediction correctness information, branch instruction redirects direction, branch instruction jump target addresses is sent to renewal and correction module；
Update and correction module, receive the instruction PC value that branch instruction predictions result judge module is sent here, branch prediction correctness information, branch instruction redirects direction, branch instruction jump target addresses, if branch prediction is correct, then utilizes the instruction PC value that branch instruction predictions result judge module is sent here, branch instruction redirects direction, branch instruction jump target addresses information is to unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), conditional branching target cache CBTB (ConditionalBranchTargetBuffer), return address storehouse RAS (ReturnAddressStack), indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer), pattern history table PHT (PatterHistoryTable), corresponding information in information of forecasting table (PIT) (PredictionInfoTable) is updated, then by instruction PC value, branch prediction correctness information, branch instruction redirects direction, branch instruction jump target addresses is sent into PC and is managed module；If branch prediction results mistake, then error correcting signal is sent into outside, processor pipeline will be carried out error correcting according to error correcting signal by outside, then instruction PC value, branch prediction correctness information, branch instruction be redirected direction, branch instruction jump target addresses feeding PC management module；
Wherein in branch instruction predictions module, the branch instruction predictions of return type employs with return address storehouse RAS (ReturnAddressStack) dynamically configuring enumerator:
With return address storehouse RAS (ReturnAddressStack) dynamically configuring enumerator, in the dynamic any one configuring the storehouse that will not point in enumerator is not used in return address storehouse RAS (ReturnAddressStack), only when enumerator uses, enumerator is just locked, uses that of storehouse of enumerator in fixing sensing return address storehouse RAS (ReturnAddressStack)；
Wherein the renewal of prediction conditional branch target cache CBTB (ConditionalBranchTargetBuffer) of branch instruction predictions module conditional branch instruction employs and partially redirects tri-state transfer algorithm:
Partially redirecting tri-state transfer algorithm is branch prediction state flag bit Tag state transition algorithm in conditional branch instructions prediction conditional branch target cache CBTB (ConditionalBranchTargetBuffer), branch prediction state flag bit Tag is used for recording branch instruction in the upper correctness once predicted, correctly remain 0, mistake puts 1, partially redirect tri-state transfer algorithm and have three states, represent with a bit register, for conditional branching target cache CBTB (ConditionalBranchTargetBuffer) list item n, initial Tag state is 0, when writing the branch instruction information redirected for the first time, state remains 0.When Tag state is 0, if record branch instruction upper once perform time do not redirect; Tag state is set to 1, otherwise remains 0.When Tag state is 1, if record branch instruction upper once perform time do not redirect, then empty this list item n record information, be reset to original state, otherwise Tag state is set to 0；
Wherein in branch instruction enquiry module, inquire about the branch instruction type that the instruction PC value prestored in unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) or conditional branching target cache CBTB (ConditionalBranchTargetBuffer) is corresponding with this instruction PC value according to instruction PC；
Wherein in branch instruction predictions result judge module, jump forecasting result diagnosis apparatus Arbiter_T evaluation algorithm is as follows:
If instruction PC value in branch instruction predictions result judge module, do not have occurrence in inquiry information of forecasting table (PIT) (PredictionInfoTable), then branch instruction performs mistake, it is judged that for branch misprediction；If having occurrence in instruction PC value inquiry information of forecasting table (PIT) (PredictionInfoTable), then branch instruction performs correct, it is judged that correct for branch prediction；
Jump forecasting result diagnosis apparatus Arbiter_N evaluation algorithm is not as follows:
If instruction PC value in branch instruction predictions result judge module, do not have occurrence in inquiry information of forecasting table (PIT) (PredictionInfoTable), then branch instruction performs correct, it is judged that correct for branch prediction；If having occurrence in instruction PC value inquiry information of forecasting table (PIT) (PredictionInfoTable), then branch instruction performs mistake, it is judged that for branch misprediction；
The present invention compared with prior art provides the benefit that:
(1) it has been designed with sort-type mixed branch Forecasting Methodology, by branch instruction is classified, better can take more excellent branch prediction schemes for different branch instructions, improve the coverage to branch instruction predictions.
(2) mode supplementing prediction is taken for indirect branch instruction, when IBTB (IndirectBranchTargetBuffer) prediction of failure, from UBTB (UnconditionalBranchTargetBuffer), reading jump target addresses last time is predicted as a supplement, can further improve branch prediction accuracy.
(3) for redirecting branch and returning branch instruction, employ with return address storehouse RAS (ReturnAddressStack) dynamically configuring enumerator, with the less more branch instruction information of hardware resource record, resource utilization, less hardware cost can be improved.
(4) use in conditional jump branch instruction predictions and partially redirect tri-state transfer algorithm, can better coordinate PHT, get rid of branch prediction redundancy interference information in time, improve the accuracy of prediction.
(5) in branch instruction enquiry module, unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) separately or conditional branching target cache CBTB (ConditionalBranchTargetBuffer) is employed, different classes of branch instruction is made individually to store, reduce relevant interference information, improve the accuracy of prediction.
(6) employ in branch instruction predictions result judge module jump forecasting result diagnosis apparatus Arbiter_T and not jump forecasting result diagnosis apparatus Arbiter_N to the separately performed judgement of branch prediction results, more accurately branch prediction results can be judged, be conducive to error correcting, improve processor performance.
Accompanying drawing explanation
Fig. 1 is branch predicting system design architecture of the present invention.
Fig. 2 is that the present invention redirects branch prediction partial design framework.
Fig. 3 is that the present invention returns branch prediction partial design framework.
Fig. 4 is indirect branch predicted portions design architecture of the present invention.
Fig. 5 is conditional branch prediction partial design framework of the present invention.
Fig. 6 is that in CBTB of the present invention (ConditionalBranchTargetBuffer), Tag state redirects tri-state transfer algorithm partially.
Fig. 7 is the dynamically configuration enumerator allocation algorithm of RAS of the present invention (ReturnAddressStack).
Fig. 8 be the present invention predict the outcome inspection correct flow process.
Fig. 9 is that the present invention predicts the outcome evaluation algorithm.
Figure 10 is function structure chart of the present invention.
Detailed description of the invention
The basic ideas of the present invention are: a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture, first inquire about branch target cache in fetching level according to instruction PC and obtain branch instruction type, branch instruction is assigned to respective prediction module, redirect branch prediction and use with return address storehouse RAS (ReturnAddressStack) dynamically configuring enumerator, indirect branch prediction employs the method supplementing prediction, when indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer) prediction of failure, from unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), reading jump target addresses last time is predicted as a supplement, conditional branch prediction flag bit Tag of record branch prediction last time correctness in conditional branching target cache CBTB (ConditionalBranchTargetBuffer) adopts and partially redirects tri-state transfer algorithm, decoding level according to the decoding object information record of instruction in information of forecasting table (PIT) (PredictionInfoTable), the correctness of branch prediction results is judged according to present instruction execution result performing level, if branch instruction predict the outcome as redirecting, jump forecasting result diagnosis apparatus Arbiter_T is then used to carry out result judgement, if branch instruction predict the outcome as not redirecting, not jump forecasting result diagnosis apparatus Arbiter_N is then used to carry out result judgement, solve the instruction delay impact that streamline is caused by branch instruction, improve the execution efficiency of processor.
Below in conjunction with Figure of description, the detailed description of the invention of the embodiment of the present invention is described in more detail.Below with reference to accompanying drawing describe embodiment by exemplary, be only used for explaining invention, and be not construed as limiting the claims.
The present invention is a kind of mixed branch Predictive Design Method based on instruction classification mode, as shown in Figure 10, and including:
In fetching level according to instruction PC inquiry unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) or conditional branching target cache CBTB (ConditionalBranchTargetBuffer), obtain branch instruction type, branch instruction is assigned to respective prediction module；
Redirecting branch prediction is to unconditional jump and prediction that branch target address is the branch instruction directly redirected, redirect branch's class branch instruction predictions to redirect, branch prediction jump target addresses is obtained, simultaneously return address record with in return address storehouse RAS (ReturnAddressStack) dynamically configuring enumerator by inquiring about unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer)；
Returning branch prediction is to the prediction that unconditional jump and branch target address are the subroutine call return instruction indirectly redirected, return branch's class branch prediction to redirect, and from return address storehouse RAS (ReturnAddressStack), obtain branch prediction jump target addresses；
Indirect branch prediction is to unconditional jump and prediction that branch target address is the branch instruction indirectly redirected, indirect branch class branch prediction redirects, from indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer), read branch prediction jump target addresses, predict as a supplement from unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), middle reading jump target addresses last time when indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer) prediction of failure；
Conditional branch prediction is to conditional branching and prediction that branch target address is the branch instruction directly redirected, conditional branching class instruction redirects direction by pattern history table PHT (PatterHistoryTable) prediction, jump target addresses is predicted by conditional branching target cache CBTB (ConditionalBranchTargetBuffer) predicted branches, wherein in conditional branching target cache CBTB (ConditionalBranchTargetBuffer), branch prediction state flag bit Tag adopts and partially redirects tri-state transfer algorithm, can better record the relevant information redirecting branch instruction；
Judge whether present instruction is branch instruction in decoding level according to the decoding result of instruction, and whether have be carried out branch instruction and redirect direction and the prediction of branch instruction jump target addresses, and information record in information of forecasting table (PIT) (PredictionInfoTable)；
Result and unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) is performed according to present instruction performing level, in conditional branching target cache CBTB (ConditionalBranchTargetBuffer) and information of forecasting table (PIT) (PredictionInfoTable), the correctness of branch prediction results is judged by the information of record, if branch instruction predict the outcome as redirecting, jump forecasting result diagnosis apparatus Arbiter_T is then used to carry out result judgement, if branch instruction predict the outcome as not redirecting, not jump forecasting result diagnosis apparatus Arbiter_N is then used to carry out result judgement；
If branch instruction predictions result is correct, then streamline continues fetching execution, mistake occurs if predicted the outcome, then cancel false command in this stage, goes out again fetching from correct destination address and performs.
It is illustrated in figure 1 branch predicting system design architecture, unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) records the jump target addresses of unconditional jump branch instruction, conditional branching target cache CBTB (ConditionalBranchTargetBuffer) records the jump target addresses of conditional jump branch instruction, return address storehouse RAS (ReturnAddressStack) is return address storehouse, record the jump target addresses of return type branch instruction, global branch history depositor GBHR (GlobalBranchHistoryRegister) records the history jump information of branch instruction.Pattern history table PHT (PatterHistoryTable) records the direction prediction information of conditional jump branch instruction.Indirect branch target buffer memory IBTB (IndirectBranchTargetBuffer) records the jump target addresses that indirect branch instruction PC value is corresponding.
In fetching level according to instruction PC inquiry unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) or conditional branching target cache CBTB (ConditionalBranchTargetBuffer), obtain branch instruction type, branch instruction is assigned to respective prediction module.Redirecting branch prediction is to unconditional jump and prediction that branch target address is the branch instruction directly redirected, redirect branch's class branch instruction predictions to redirect, obtain jump target addresses by inquiring about unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer), return address is recorded in return address storehouse RAS (ReturnAddressStack) simultaneously；Returning branch prediction is to the prediction that unconditional jump and branch target address are the subroutine call return instruction indirectly redirected, return branch's class branch prediction to redirect, and from return address storehouse RAS (ReturnAddressStack), obtain jump target addresses；Indirect branch prediction is to unconditional jump and prediction that branch target address is the branch instruction indirectly redirected, indirect branch class branch prediction redirects, reading jump target addresses from IBTB (IndirectBranchTargetBuffer), when IBTB (IndirectBranchTargetBuffer) prediction of failure, from UBTB (UnconditionalBranchTargetBuffer), reading jump target addresses last time is predicted as a supplement；Conditional branch prediction is to conditional branching and prediction that branch target address is the branch instruction directly redirected, conditional branching class instruction redirects direction by pattern history table PHT (PatterHistoryTable) prediction, predicts jump target addresses by CBTB (ConditionalBranchTargetBuffer).
It is illustrated in figure 2 and redirects branch prediction partial design framework, branch's jump target addresses of CallPC is recorded in UBTB (UnconditionalBranchTargetBuffer), inquiry UBTB (UnconditionalBranchTargetBuffer) form obtains branch target address T_addr, and the PC address of next instruction is recorded in storehouse RAS (ReturnAddressStack) form of return address simultaneously, it is because after compiling, having delay groove after Call instruction at specific implementation process Program used here as 8, comprise a delay instruction, therefore the PC value of next instruction that When subroutine return instruction performs after returning is CallPC+8.
It is illustrated in figure 3 return branch prediction partial design framework, when running into a RET or RETL instruction, by inquiring about unconditional branch target cache UBTB (UnconditionalBranchTargetBuffer) or conditional branching target cache CBTB (ConditionalBranchTargetBuffer) it is known that this is a subroutine return instruction, it is therefore desirable to take out the instruction branch jump target addresses T_addr as return instruction from return address storehouse RAS (ReturnAddressStack).
It is illustrated in figure 4 indirect branch predicted portions design architecture, when running into a JMPL instruction, generate search terms retrieval IBTB (IndirectBranchTargetBuffer) by index module Indexmodule and find the branch target address T_addr of current branch instruction, UBTB (UnconditionalBranchTargetBuffer) also can retrieve one T_addr of generation simultaneously, one of them is selected to perform as the branch target address fetching of prediction by T_addrselect module, UBTB (UnconditionalBranchTargetBuffer) preserves be current branch instruction JMPL upper once perform time branch target address, the branch target address that first-selected IBT produces, when the jump target addresses information that can not find relative branch instruction in IBTB (IndirectBranchTargetBuffer), then relevant information is informed T_addrselect module, select branch's jump target addresses that in UBTB (UnconditionalBranchTargetBuffer), the last time performs as predicting the outcome.
Being illustrated in figure 5 conditional branch prediction partial design framework, GBHR is global branch history shift register, be used for recording recently generation branch instruction redirect historical information, represent that branch redirects with 1, represent that branch does not redirect with 0.Whether PHT (PatterHistoryTable) records conditional branch instructions historical information, and redirected by these information prediction current branch instruction.When running into a conditional branching and after branch target address is the branch instruction directly redirected, search terms retrieval branch history pattern table PHT (PatterHistoryTable) is generated by index module Indexmodule, what obtain whether current branch redirect predicts the outcome, select according between this result address when CBTB (ConditionalBranchTargetBuffer) the branch's jump target addresses provided and branch do not redirect, as next proceeding to the address that fetching performs.
If Fig. 6 is that in CBTB (ConditionalBranchTargetBuffer), Tag state redirects tri-state transfer algorithm partially.Branch target cache CBTB (ConditionalBranchTargetBuffer) is specifically used to record condition and redirects the jump target addresses information of branch instruction.CBTB (ConditionalBranchTargetBuffer) uses in conditional branch prediction.CBTB (ConditionalBranchTargetBuffer) have recorded branch's jump target addresses of conditional branching.Owing to it is separate with UBTB (UnconditionalBranchTargetBuffer), and the branch instruction of only record condition branch pattern, therefore branch pattern mark B_type position need not be set, but owing to it is conditional branching, it is thus desirable to arrange flag bit Tag to assist CBTB (ConditionalBranchTargetBuffer) to update, Tag is used for recording the correctness that corresponding branch instruction was predicted in last time, correctly remains 0, and mistake puts 1.Partially redirect tri-state transfer algorithm and have three states, represent with a bit register, three states are for CBTB (ConditionalBranchTargetBuffer) list item n, and initial Tag state is 0, and when writing the branch instruction information redirected for the first time, state remains 0.When Tag state is 0, if record branch instruction upper once perform time do not redirect; Tag state is set to 1, otherwise remains 0.When Tag state is 1, if record branch instruction upper once perform time do not redirect, then empty this list item n record information, be reset to original state, otherwise Tag state is set to 0.
In the prediction of this kind of branch instruction of conditional branching, it is necessary to PHT (PatterHistoryTable) and CBTB (ConditionalBranchTargetBuffer) has cooperated to branch instruction and redirected the prediction of direction and jump target addresses.PHT (PatterHistoryTable) is for the direction of predicted condition branch instruction, and CBTB (ConditionalBranchTargetBuffer) carrys out jump target addresses when predicted condition branch instruction redirects.Because being the prediction that same branch instruction is made, therefore their search terms must be consistent, use same by branch history and branch address by the Indexmodule index entry generated.PHT (PatterHistoryTable) namely makes the prediction that branch instruction does not redirect, make again the prediction that branch instruction redirects, and the jump target addresses of the branch instruction that PHT (PatterHistoryTable) prediction redirects only is made a prediction by CBTB (ConditionalBranchTargetBuffer), therefore will necessarily there is certain deviation in corresponding relation between the two, is embodied in:
1. PHT (PatterHistoryTable) predicting branch instructions redirects, and does not have the jump target addresses of respective branch instructions in CBTB (ConditionalBranchTargetBuffer)；
2. PHT (PatterHistoryTable) predicting branch instructions redirects, and has the jump target addresses of respective branch instructions in CBTB (ConditionalBranchTargetBuffer)；
3. PHT (PatterHistoryTable) predicting branch instructions does not redirect, and does not have the jump target addresses of respective branch instructions in CBTB (ConditionalBranchTargetBuffer)；
4. PHT (PatterHistoryTable) predicting branch instructions does not redirect, and has the jump target addresses of respective branch instructions in CBTB (ConditionalBranchTargetBuffer).
In above four kinds of states, the state that 2., 3. state has been, 1., 4. state is belonging to the state to correct in time devious, if PHT (PatterHistoryTable) prediction is correct, 1. state can be negatively affected to branch prediction, and 4. branch prediction is had no adverse effect by state.
If 1. the prediction of conditional branching is in state, then continue fetching according to the order originally not occurring branch to redirect to perform, because PHT (PatterHistoryTable) exists the possibility of prediction error, then the instruction that continuation order fetching performs is likely located in correct instruction execution path.If 4. the prediction of conditional branching is in state, then continue fetching execution according to the order that branch redirects that do not occur of prediction.
What in PHT (PatterHistoryTable), the renewal of predicted state adopted is two saturated counters algorithms, when state is in saturation time, only twice prediction of failure just can change the result of branch prediction, therefore can well record the information always redirecting, always do not redirect and have the branch instruction strongly redirecting skewed popularity.What the renewal of CBTB (ConditionalBranchTargetBuffer) adopted is partially redirect tri-state transfer algorithm, and this algorithm can well record the relevant information redirecting branch instruction.If 1. the prediction of conditional branching is in state, and PHT (PatterHistoryTable) prediction is correct, CBTB (ConditionalBranchTargetBuffer) then records when next time is predicted the jump target addresses of dependent instruction, has jumped out state 1..If 4. the prediction of certain branch instruction is in state by conditional branch prediction, then double at most it is in state 4., CBTB (ConditionalBranchTargetBuffer) will remove relevant record information.
It is illustrated in figure 7 the dynamically configuration enumerator allocation algorithm of RAS (ReturnAddressStack), enumerator certain list item when not using and in unfixed sensing RAS (ReturnAddressStack), only when enumerator uses, enumerator is just locked, fixing sensing RAS (ReturnAddressStack) uses the list item of enumerator, it is therefore an objective to the utilization rate in order to improve enumerator saves resource simultaneously.RAS_index is the list item pointer of RAS (ReturnAddressStack), and what Counter_index was that the list item pointer-digit of enumerator Counter represents is RAS (ReturnAddressStack) the pointer RAS_index list item label pointed to.RAS_index original state points to 0 position, Counter_index points to first enumerator 1, need the address contents of a upper list item in the write branch target address T_addr of return instruction and this destination address and RAS (ReturnAddressStack) unequal when running into a subroutine call branch instruction, so RAS_index pointer adds 1, if the flag flag bit of a upper list item is 1, so illustrate that a list item employs enumerator, some subfunction of polyphony of attaching most importance to, and finish to repeat to call in current PC, start to have invoked another subfunction, Counter_index pointer adds 1.If it is equal to need to write the address contents of a upper list item in the branch target address of return instruction and RAS (ReturnAddressStack), current RAS (ReturnAddressStack) list item flag is put 1, the counter contents that Counter_index points to adds 1, and RAS_index pointer remains unchanged.When running into a subroutine call return instruction, it is necessary to read the branch target address in the RAS_index list item pointed to, if flag corresponding to this list item is 0, then after reading, RAS_index pointer subtracts 1.If the flag that this list item is corresponding is 1, then after reading, Counter_index pointer subtracts 1, if Counter_index pointer becomes 0 after subtracting 1, in addition it is also necessary to flag corresponding for this table is set to 0.If RAS (ReturnAddressStack) writes full, return original state and restart.Counter_index writes and returns first enumerator covering write after completely.
It is illustrated in figure 8 the inspection that predicts the outcome and corrects flow process, BPM (BranchPredictModule) records the historical information of the branch instruction currently redirected, record the information of branch instruction in current pipeline in information of forecasting table (PIT) (PredictionInfoTable) form, the result of branch prediction is carried out checking renewal by two modules of Arbiter_N, Arbiter_T.For the PC value obtained in fetching level, first pass through BPM (BranchPredictModule) prediction, if prediction hit, then think that this instruction is branch instruction and once occurred, then perform from new address fetching according to BPM (BranchPredictModule) branch target address predicted, and the PC of this branch instruction is recorded in information of forecasting table (PIT) (PredictionInfoTable) table.Without hit, then think that this is not the branch instruction not occurred before branch instruction or, then need to use decoding logic to judge, if present instruction is branch instruction, by its record in information of forecasting table (PIT) (PredictionInfoTable) table.After branch instruction is finished, inquire about information of forecasting table (PIT) (PredictionInfoTable) form, if the current PC performed is in BranchPC form, then proceed branch outcome checking.If this branch instruction result is not for occur, then uses Arbiter_N module to be predicted result and judge, if this branch instruction result is for occurring, then uses Arbiter_T module to be predicted result and judge.
If Fig. 9 is the evaluation algorithm that predicts the outcome, if this branch instruction result is not for occur, then uses Arbiter_N module to be predicted result and judge, if this branch instruction result is for occurring, then uses Arbiter_T module to be predicted result and judge.In Arbiter_N module, if the current PC value performed is not hit in information of forecasting table (PIT) (PredictionInfoTable), then branch instruction performs correct, if the hit in information of forecasting table (PIT) (PredictionInfoTable) of the current PC value performed, show that this branch instruction performs mistake, then remove related streams waterline, updating information of forecasting table (PIT) (PredictionInfoTable) form, PCmanagemodule goes out again fetching execution from correct PC address simultaneously.In Arbiter_T module, if the current PC value performed is not hit in information of forecasting table (PIT) (PredictionInfoTable), show that branch instruction performs mistake, then remove related streams waterline, updating information of forecasting table (PIT) (PredictionInfoTable) table, PCmanagemodule goes out again fetching execution from correct PC address simultaneously.If the hit in information of forecasting table (PIT) (PredictionInfoTable) of the current PC value performed, and target address prediction is correct, then branch instruction performs correct, update information of forecasting table (PIT) (PredictionInfoTable) table, if destination address is incorrect, then branch instruction performs mistake, then remove related streams waterline, updating information of forecasting table (PIT) (PredictionInfoTable) table, PCmanagemodule goes out again fetching execution from correct PC address simultaneously.
In sum, the present invention devises a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture, by branch instruction is classified, better can take more excellent branch prediction schemes for different branch instructions, it is possible to less hardware resource, improve branch prediction accuracy, the present invention has been applied in SPARC associative processor, by improving branch prediction accuracy, improve the performance of processor, be widely used at space industry.
Claims (7)
1. the sort-type mixed branch prognoses system based on SPARCV8 architecture, it is characterized in that, including: PC manages module, branch instruction enquiry module, branch instruction predictions module, branch instruction information logging modle, branch instruction predictions result judge module, renewal and correction module, unconditional branch target cache UBTB, conditional branching target cache CBTB, return address storehouse RAS, indirect branch target buffer memory IBTB, pattern history table PHT, information of forecasting table (PIT)；
Unconditional branch target cache UBTB, stores the branch instruction type information that unconditional jump branch instruction PC value is corresponding and the jump target addresses that unconditional jump branch instruction PC value is corresponding；
Conditional branching target cache CBTB, stores the branch instruction type information that conditional jump branch instruction PC value is corresponding and the jump target addresses that conditional jump branch instruction PC value is corresponding；
Return address storehouse RAS, stores and returns the return destination address that branch instruction PC value is corresponding；
Indirect branch target buffer memory IBTB, stores the jump target addresses that indirect branch instruction PC value is corresponding；
Pattern history table PHT, the branch storing indirect branch instruction PC value corresponding redirects direction；
Information of forecasting table (PIT), stores the information of forecasting that branch instruction PC value is corresponding；
PC manages module, the branch prediction results feedback information that branch prediction results, renewal and the correction module that the reception instruction PC value of externally input, branch instruction predictions module are sent here is sent here, the branch prediction results that wherein branch instruction predictions module is sent here, including, whether branch instruction predictions redirects, branch instruction predictions jump target addresses；Update and the branch prediction results feedback information sent here of correction module, whether redirect including branch instruction PC value, branch prediction results correctness, branch instruction, branch instruction jump target addresses；When branch predicting system initial launch, if branch prediction results mistake in the branch prediction results feedback information that renewal and correction module are sent here, then give up the branch prediction results that branch instruction predictions module is sent here, if then judging that in the branch prediction results feedback information that renewal and correction module are sent here, branch instruction redirects, then in branch prediction results feedback information renewal and correction module sent here, branch instruction jump target addresses sends into branch instruction enquiry module as next instruction PC value；If branch prediction results mistake in the branch prediction results feedback information that renewal and correction module are sent here, then give up the branch prediction results that branch instruction predictions module is sent here, if then judging that in the branch prediction results feedback information that renewal and correction module are sent here, branch instruction does not redirect, in the branch prediction results feedback information then renewal and correction module sent here, branch instruction PC value calculates plus described fixing numerical value of N and produces next instruction PC value, and next instruction PC value sends into branch instruction enquiry module this；If branch prediction results is correct in the branch prediction results feedback information that renewal and correction module are sent here, if then judging that in the branch prediction results that branch instruction predictions module is sent here, branch instruction predictions redirects, then in branch prediction results branch instruction predictions module sent here, branch instruction predictions jump target addresses sends into branch instruction enquiry module as next instruction PC value；If branch prediction results is correct in the branch prediction results feedback information that renewal and correction module are sent here, if then judging that in the branch prediction results that branch instruction predictions module is sent here, branch instruction predictions does not redirect, the instruction PC value then outside sent into calculates plus described fixing numerical value of N and produces next instruction PC value, and it is sent into branch instruction enquiry module；Next instruction PC value is delivered to the outside instruction to this instruction PC value correspondence simultaneously decode, by the Instruction decoding information back branch instruction decoding information logging modle after decoding, after the outside Instruction decoding information and executing that this instruction PC value is corresponding, obtain execution result information and send into branch instruction predictions result judge module；
Branch instruction enquiry module, receive PC and manage described next instruction PC value that module is sent here, according to the branch instruction type that unconditional branch target cache UBTB and the conditional branching target cache CBTB instruction PC value stored is corresponding with next instruction PC value this described, obtain the branch instruction type information corresponding with the instruction PC value that PC management module is sent here, then instruction PC value and branch instruction type information are sent into branch instruction predictions module；
Branch instruction predictions module, receive instruction PC value and branch instruction type information that branch instruction enquiry module is sent here, if branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it is unconditional jump and branch target address is the branch instruction directly redirected, then this branch instruction predictions redirects, then pass through inquiry unconditional branch target cache UBTB, obtain the branch instruction predictions jump target addresses corresponding with this instruction PC value, manage, plus PC, the fixing numerical value of N used in module according to next instruction PC value this described simultaneously and obtain the return address corresponding with this branch instruction, then this return address is recorded in the storehouse RAS of return address；If branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it is the branch instruction of return type, then from the storehouse RAS of return address, takes out in the storehouse RAS of return address a return address of stack top as the branch instruction predictions jump target addresses of this return type；If branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it it is indirect branch instruction, then the prediction of this indirect branch instruction redirects, then from indirect branch target buffer memory IBTB, read the branch instruction predictions jump target addresses that this instruction PC value is corresponding, without when reading branch instruction predictions jump target addresses corresponding to this instruction PC value and IBTB prediction of failure in indirect branch target buffer memory IBTB, then from unconditional branch target cache UBTB, read the branch instruction predictions jump target addresses that this instruction PC value is corresponding, this mode is defined as supplements prediction；If branch instruction type information shows the branch instruction that present instruction PC value is corresponding, it it is conditional branch instructions, then obtain the branch instruction predictions corresponding with this instruction PC value by query pattern history lists PHT and redirect direction, branch instruction predictions redirects direction and whether branch instruction predictions redirects, and then passes through querying condition branch target cache CBTB and obtains the branch instruction predictions jump target addresses corresponding with next instruction PC value this described；Branch instruction predictions corresponding to next instruction PC value described in branch instruction predictions module, this described next instruction PC value is redirected direction and branch instruction predictions jump target addresses sends into branch instruction information logging modle, branch instruction predictions corresponding to next instruction PC value described in branch instruction predictions module, this described next instruction PC value is redirected direction and branch instruction predictions jump target addresses feeding PC management module simultaneously；
Branch instruction information logging modle, receive described next instruction PC value that branch instruction predictions module is sent here, the branch instruction predictions of this described next instruction PC value correspondence redirects direction and branch instruction predictions jump target addresses, receive the corresponding Instruction decoding information of described next instruction PC value of externally input, judge whether present instruction is branch instruction according to the Instruction decoding information that described next instruction PC value is corresponding, and whether have be carried out branch instruction and redirect direction and the prediction of branch instruction jump target addresses, and judged result information record in information of forecasting table (PIT), then next instruction PC value described in receiving is sent into branch instruction predictions result judge module；
Branch instruction predictions result judge module, including: jump forecasting result diagnosis apparatus Arbiter_T and not jump forecasting result diagnosis apparatus Arbiter_N；
Branch instruction predictions result judge module, receive the instruction PC value that branch instruction information logging modle is sent here, receive the execution result information of the instruction of externally input, wherein the execution result information of the instruction of externally input includes, branch instruction redirects direction, branch instruction jump target addresses, in the instruction execution result corresponding according to next instruction PC value described in receiving and information of forecasting table (PIT), the correctness of branch prediction results is judged by the information of record, if namely in the execution result information of instruction, branch instruction redirects direction is redirect, the jump forecasting result diagnosis apparatus Arbiter_T in branch instruction predictions result judge module is then used to carry out the correction judgement of branch prediction results, if branch instruction redirects direction for not redirect in the execution result information of instruction, the not jump forecasting result diagnosis apparatus Arbiter_N in branch instruction predictions result judge module is then used to carry out the correction judgement of branch prediction results, branch prediction correctness information is obtained after judgement, then described next instruction PC value, branch prediction correctness information, branch instruction redirects direction, branch instruction jump target addresses is sent to renewal and correction module；
Update and correction module, receive the instruction PC value that branch instruction predictions result judge module is sent here, branch prediction correctness information, branch instruction redirects direction, branch instruction jump target addresses, if branch prediction is correct, then utilize described next instruction PC value that branch instruction predictions result judge module is sent here, branch instruction redirects direction, branch instruction jump target addresses information is to unconditional branch target cache UBTB, conditional branching target cache CBTB, , indirect branch target buffer memory IBTB, pattern history table PHT, corresponding information in information of forecasting table (PIT) is updated, then by instruction PC value, branch prediction correctness information, whether branch instruction redirects, branch instruction jump target addresses is sent into PC and is managed module；If branch prediction results mistake, then, after producing error correcting signal, this error correcting signal is sent into outside, then instruction PC value, branch prediction correctness information, branch instruction are redirected direction, branch instruction jump target addresses feeding PC management module.
2. a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture according to claim 1, it is characterised in that: in described branch instruction predictions module, the branch instruction predictions of return type employs with the return address storehouse RAS dynamically configuring enumerator；
With the return address storehouse RAS dynamically configuring enumerator, when dynamically configuration enumerator is not used, stack pointer will not point to any stack of the storehouse in the storehouse RAS of return address, in only the enumerator in the storehouse RAS of return address uses, enumerator is just locked, that stack pointing to the storehouse using enumerator in the storehouse RAS of return address that stack pointer is fixing.
3. a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture according to claim 1, it is characterized in that, the renewal of the prediction conditional branch target cache CBTB of described branch instruction predictions module conditional branch instruction employs and partially redirects tri-state transfer algorithm:
Partially redirecting tri-state transfer algorithm is branch prediction state flag bit Tag state transition algorithm in conditional branch instructions prediction conditional branch target cache CBTB, branch prediction state flag bit Tag is used for recording branch instruction in the upper correctness once predicted, correctly remain 0, mistake puts 1, partially redirect tri-state transfer algorithm and have three states, represent with a bit register, when the initial Tag state of conditional branching target cache CBTB list item n is 0, when writing the branch instruction information redirected for the first time, state remains 0, when after first time, Tag state is 0, if record branch instruction upper once perform time do not redirect, Tag state is set to 1, otherwise remain 0, when after first time, Tag state is 1, if record branch instruction upper once perform time do not redirect, then empty the information of this list item n record, it is reset to original state, otherwise Tag state is set to 0.
4. a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture according to claim 1, it is characterised in that in described branch instruction predictions result judge module, jump forecasting result diagnosis apparatus Arbiter_T evaluation algorithm is as follows:
If next instruction PC value described in branch instruction predictions result judge module, in information of forecasting table (PIT), inquiry does not have this described next instruction PC value, then branch instruction performs mistake, it is judged that for branch misprediction；If described next instruction PC value is inquired about in information of forecasting table (PIT) this described next instruction PC value, then branch instruction performs correct, it is judged that correct for branch prediction；
Jump forecasting result diagnosis apparatus Arbiter_N evaluation algorithm is not as follows:
If next instruction PC value described in branch instruction predictions result judge module, in information of forecasting table (PIT), inquiry does not have this described next instruction PC value, then branch instruction performs correct, it is judged that correct for branch prediction；If described next instruction PC value is inquired about in information of forecasting table (PIT) occurrence, then branch instruction performs mistake, it is judged that for branch misprediction.
5. a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture according to claim 1, it is characterised in that: described fixing numerical value of N is determined according to the treatable command length of processor running branch predicting system.
6. a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture according to claim 1, it is characterised in that: described fixing numerical value of N one of takes in 1 or 4 or 8.
7. a kind of sort-type mixed branch prognoses system based on SPARCV8 architecture according to claim 1, it is characterized in that: utilize described next instruction PC value that branch instruction predictions result judge module is sent here, branch instruction redirects direction, branch instruction jump target addresses information is to unconditional branch target cache UBTB, conditional branching target cache CBTB, indirect branch target buffer memory IBTB, pattern history table PHT, corresponding information in information of forecasting table (PIT) is updated, update method according to branch instruction predictions result judge module send here described in next instruction PC value, the branch instruction jump target addresses that branch instruction predictions result judge module is sent here replaces UBTB, CBTB, the branch instruction jump target addresses that in IBTB, corresponding described next instruction PC value is corresponding, according to branch instruction predictions result judge module send here described in next instruction PC value, the branch instruction predictions information deletion that next instruction PC value described in PIT is corresponding, according to branch instruction predictions result judge module send here described in next instruction PC value, the branch instruction that branch instruction predictions result judge module is sent here redirects the branch instruction replacing described next instruction PC value of correspondence in PHT corresponding in direction and redirects direction.
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