CN105702699A - Magnetic tunnel junction (MTJ) access member and spin transfer torque magnetoresistive random access memory (STT-MRAM) unit comprising MTJ - Google Patents

Magnetic tunnel junction (MTJ) access member and spin transfer torque magnetoresistive random access memory (STT-MRAM) unit comprising MTJ Download PDF

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CN105702699A
CN105702699A CN201610169367.5A CN201610169367A CN105702699A CN 105702699 A CN105702699 A CN 105702699A CN 201610169367 A CN201610169367 A CN 201610169367A CN 105702699 A CN105702699 A CN 105702699A
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layer
bottom electrode
potential barrier
pinning layer
hole
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顾时群
升·H·康
朱晓春
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/82—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of the magnetic field applied to the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Abstract

A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, (150) a pinned layer (160) adjacent to the bottom electrode layer, a dielectric layer (70) encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier (190) adjacent to the pinned layer, a free layer (200) adjacent to the tunneling barrier, and a top electrode (210) adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell is disclosed.

Description

MTJ (MTJ) memory element and spin transfer torque magnetoresistive random access memory (STT-MRAM) unit with MTJ
The relevant information of divisional application
This case is divisional application。Female case of this division is the applying date to be on February 2nd, 2010, application number be 201080005027.X, denomination of invention are the application for a patent for invention case of " MTJ (MTJ) memory element and have spin transfer torque magnetoresistive random access memory (STT-MRAM) unit of MTJ "。
Technical field
Disclosed embodiment relates to spin transfer torque magnetoresistive random access memory (STT-MRAM) unit and its forming method。More particularly, one exemplary embodiment is for MTJ (MTJ) memory element that can be used in STT-MRAM cell and its forming method。
Background technology
Magnetoresistive RAM (MRAM) is the non-volatile memory technologies using magnetics。For example, spin transfer torque magnetoresistive random access memory (STT-MRAM) uses when electronics obtains the electronics of spin polarization through thin film (spin filter) time-varying。STT-MRAM is also known as spin transfer torque RAM (STT-RAM), spinning moment transfer magnetization switching RAM (Spin-RAM) and spin momentum transfer (SMT-RAM)。
Fig. 1 illustrates conventional STT-MRAM bit cell 100。Described STT-MRAM bit cell 100 includes MTJ (MTJ) memory element 105, transistor 110, bit line 120 and wordline 130。As illustrated in Figure 1, described MTJ storage element be by (such as) by insulation (tunneling potential barrier) layer separate pinning layer and free layer formed, described pinning layer and each in described free layer can keep magnetic field or polarization。The polarization of described free layer can be reversed so that described pinning layer and the polarity of described free layer in general alignment with or contrary。The alignment of the polarization depending on described pinning layer and free layer is changed by the resistance through the power path of described MTJ。As it is known, this resistance variations can be used for programming and read institute's bitcell 100。Described STT-MRAM bit cell 100 also includes source electrode line 140, sense amplifier 150, read/write circuits 160 and bit line benchmark 170。Being understood by those skilled in the art that, operation and the structure of described memory cell 100 are known in the art。For example, about the additional detail of this type of memory cell be provided in M.Hosomi et al. " there is the novel nonvolatile memory of spin transfer torque magnetoresistive magnetization switch: spin RAM (ANovelNonvolatileMemorywithSpinTransferTorqueMagnetoresi stiveMagnetizationSwitching:Spin-RAM) " (The procceedings of IEDM meeting(2005), in), its full content is incorporated herein by reference。
Referring to Fig. 2 (a) to Fig. 2 (c), conventional MTJ storage element is formed typically via following steps: first pattern bottom fixed layer；Form single inlay structure；Deposit tunneling potential barrier/free layer/top electrodes stacking；And perform chemically mechanical polishing (CMP) step。
For example, as shown in Figure 3, conventional MTJ storage element is stacking and formed at metal layer at top (such as, M3) the upper deposition MTJ of metal stack (such as, cross tie part 40) and hard mask layer typically via using physical vapour deposition (PVD) (PVD)。Described MTJ and hard mask layer stacking generally include can (such as) formed by tantalum bottom electrode layer 50, pinning layer 60, tunneling barrier layer 90, free layer 100 and can (such as) hard mask of being formed by Ta/TaN or Ti/TiN or top electrode layer 110。
In conventional method, first step generally includes deposited bottom electrode layer 50 (such as, Ta), pinning layer 60, tunneling potential barrier 90, free layer 100 and hard mask layer (Ta/TaN, Ti/TN)。Pinning layer 60 can include one or more layers or film (such as, pinning layer is stacking)。It follows that make described MTJ stack stand magnetic annealing technique in a vacuum。It is then used by photoetching technique and pattern is applied to described MTJ stack。Described patterned cell size can more than final size。Each in aforementioned layers can comprise one or more layers or film。
It follows that etch described MTJ stack。Etch process includes: finishing photoresist size and pattern hard mask, peels off photoresist, etches free layer 100, and etches pinning layer 60 and bottom electrode layer 50。It follows that clean described MTJ stack。Described cleaning procedure is generally compatible with low k and MTJ cleaning。It follows that deposit passivation layer is to protect MTJ storage element and interlayer dielectric 70。It is likely to need combination stacked and low deposition temperature to protect MTJ and to promote the bonding between MTJ and ILD。Finally, less rodent chemically mechanical polishing (CMP) is used to polish MTJ and ILD to prevent layering。
As it is shown on figure 3, the conventional STT-MRAM bit cell formed according to conventional methods includes substrate 10, wordline 20 and and VSSThe contact 30 of (not shown)。Bottom electrode layer 50 is formed in the metal layer at top of cross tie part 40。Pinning layer 60, tunneling barrier layer 90, free layer 100 and top electrodes 110 are formed in bottom electrode layer 50。ILD layer 70 is formed in MTJ cell。
Summary of the invention
One exemplary embodiment is for spin transfer torque magnetoresistive random access memory (STT-MRAM) unit and its forming method。More particularly, embodiment relates to MTJ (MTJ) memory element and its forming method of STT-MRAM cell。
For example, one exemplary embodiment is that it has MTJ (MTJ) memory element, and described MTJ storage element comprises: bottom electrode for a kind of storage arrangement；Pinning layer, it is adjacent to described bottom electrode；Dielectric layer, it encapsulates a part for described bottom electrode and described pinning layer, and wherein said dielectric layer includes the sidewall defining the hole of the part being adjacent to described pinning layer；Tunneling potential barrier, it is adjacent to described pinning layer；Free layer, it is adjacent to described tunneling potential barrier；And top electrodes, it is adjacent to described free layer, wherein said bottom electrode and/or described pinning layer width in a first direction more than the width in said first direction of the contact area between described pinning layer and described tunneling potential barrier。
Another one exemplary embodiment is for a kind of method forming storage arrangement, and described storage arrangement has MTJ (MTJ) memory element, and described method comprises: form bottom electrode on substrate；Described bottom electrode is formed pinning layer；Dielectric layer deposition on described bottom electrode and described pinning layer；In described dielectric layer, patterning has the hole of sidewall and described hole is etched down to described pinning layer；The Part I in described hole deposits tunneling barrier layer to produce tunneling potential barrier on described pinning layer；The Part II in described hole deposits free layer so that described free layer is positioned in described tunneling potential barrier；And on described free layer, deposit top layers。
One exemplary embodiment is that it has MTJ (MTJ) memory element, and described MTJ storage element comprises for a kind of storage arrangement: for electrically connecting the bottom conductive device of described MTJ storage element；For keeping the first magnetic devices of the first polarization, described first magnetic devices is adjacent to described bottom conductive device；For encapsulating the first seal of a part for described bottom conductive device and described first magnetic devices, wherein said first seal includes the sidewall defining the hole of the part being adjacent to described first magnetic devices；For keeping the second magnetic devices of the second polarization, wherein said second polarization is reversible；For making the second seal that the electric current of flowing is tunneling between described first magnetic devices and described second magnetic devices, described second seal separates described first magnetic devices and described second magnetic devices；And for electrically connecting the top conductive device of described MTJ storage element, described top conductive device is adjacent to described second magnetic devices, wherein said bottom conductive device and/or described first magnetic devices width in a first direction more than the width in said first direction of the contact area between described first magnetic devices and described second seal。
Another one exemplary embodiment comprises a kind of method forming storage arrangement, and described storage arrangement has MTJ (MTJ) memory element, and described method comprises: for forming the step of bottom electrode on substrate；For forming the step of pinning layer on described bottom electrode；For the step of dielectric layer deposition on described bottom electrode and described pinning layer；There is the hole of sidewall for patterning in described dielectric layer and described hole is etched down to the step of described pinning layer；For depositing tunneling barrier layer in the Part I in described hole to produce the step of tunneling potential barrier on described pinning layer；For depositing free layer in the Part II in described hole so that described free layer is positioned at the step in described tunneling potential barrier；And for depositing the step of top layers on described free layer。
Accompanying drawing explanation
Present accompanying drawing to assist description embodiment, and provide accompanying drawing to be merely to illustrate described embodiment but not it is any limitation as。
Fig. 1 illustrates conventional Spin Transfer Torque magnetoresistive RAM (STT-MRAM) cell array。
The cross-sectional view that Fig. 2 (a) is conventional STT-MRAM cell。
Fig. 2 (b) is the enlarged drawing of a part for the conventional STT-MRAM cell according to Fig. 2 (a)。
Fig. 2 (c) is the enlarged drawing of the conventional MTJ cell according to Fig. 2 (a)。
Fig. 3 is the schematic cross section of conventional STT-MRAM bit cell。
Fig. 4 to Fig. 7 is the schematic cross section of the STT-MRAM bit cell during the various fabrication stages。
Fig. 8 is the schematic cross section of STT-MRAM bit cell。
Fig. 9 is the flow chart showing the exemplary method forming STT-MRAM bit cell。
Figure 10 is the schematic cross section of the MTJ storage element of STT-MRAM bit cell。
Figure 11 is the schematic cross section of the MTJ storage element of STT-MRAM bit cell。
Figure 12 is the schematic cross section of the MTJ storage element of STT-MRAM bit cell。
Figure 13 is the schematic cross section of the MTJ storage element of STT-MRAM bit cell。
Detailed description of the invention
For specific embodiment be described below and correlative type disclose the present invention exemplary in。Alternate embodiment can be designed when not necessarily departing from the scope of the present invention。Additionally, will not be discussed in detail maybe by omit embodiment well-known element not obscure the correlative detail of described embodiment。
Word " exemplary " is in this article in order to refer to " serving as an example, example or explanation "。There is no need to be construed to more preferred or favourable than other embodiments by any embodiment here depicted as " exemplary "。Equally, term " embodiment " is not required for feature, advantage or the operator scheme that all embodiments all include discussing。Term used herein only for the purpose of describing particular embodiments, and is not intended to limit embodiment。
As used herein, singulative " " and " described " are intended to also include plural form, unless the context clearly indicates otherwise。Should be further understood that, specify the existence of feature, entirety, step, operation, element and/or the assembly stated when term " comprises " and/or " including " is used herein, but be not excluded for existence or the interpolation of one or more further features, entirety, step, operation, element, assembly and/or its group。
Disclosed embodiment is recognized, under conventional approaches, it may be difficult to control the etch-stop on the bottom electrode of MTJ。And, after etching, cleaning is likely to stay on MTJ sidewall that polymer residues, some of which are likely conduction and can produce leakage paths comprehensively, and then reduces magnetic resistance (MR) ratio。Additionally, the barrier oxide layer near MTJ sidewall is likely to be subject to technological process (that is, ashing and cleaning procedure) impact, and then near MTJ sidewall, produce thicker tunneling potential barrier。The impact of thicker tunneling potential barrier will be significant for scaled feature。
One exemplary embodiment advantageously allows for reducing the number of the mask used in production technology。For example, two photomasks can be used to replace three masks。And, according to described embodiment, for critical sizes such as the interfaces between such as pinning layer and tunneling potential barrier and between free layer and tunneling potential barrier, it is not necessary to heavy metal etch process。Additionally, the leakage path (leakagepass) that lateral wall polymer longeron (stringer) brings out can be reduced or eliminate。
Additionally, according to described embodiment, the tunneling potential barrier of MTJ is not exposed to ashing and cleaning procedure。Additionally, described embodiment can provide bigger bottom fixed layer compared with conventional method, this can minimize the bottom fixed layer astray field influence to top free layer。
Referring to Fig. 4 to Figure 11, the existing embodiment by the one exemplary embodiment and STT-MRAM cell that describe the method forming spin transfer torque magnetoresistive random access memory (STT-MRAM) unit。
Fig. 4 shows the schematic cross section of the part STT-MRAM bit cell formed according to one exemplary embodiment。Described STT-MRAM bit cell has contact 30 and the cross tie part 40 of substrate 10, wordline 20 and Vss (not shown), cross tie part 40 includes metal level M1, M2 and the M3 (such as, Cu or W) that (such as) is serially connected by through-hole interconnection part V1, V2 and V3。Electrolyte (such as, oxide skin(coating)) is filled in around each layer of cross tie part 40。(such as) use chemically mechanical polishing (CMP) technology that the metal layer at top M3 of described cross tie part 40 is polished。Those skilled in the art will realize that and any level of metal level or through hole can be polished for being formed on described MTJ storage element。
As it is shown in figure 5, described one exemplary embodiment includes forming MTJ bottom electrode by (such as) deposited bottom electrode layer 150 (such as, Ta) and pinning layer 160 on the polished metal layer at top M3 of cross tie part 40。Described pinning layer 160 includes layer stack folded (that is, multiple layers)。It follows that make bottom electrode layer 150 and pinning layer 160 stand magnetic annealing technique in a vacuum。It is then used by photoetching technique and pattern is applied to described MTJ electrode。It follows that bottom electrode layer 150 and pinning layer 160 are etched down to oxide skin(coating), and then it is cleaned forming indivedual bottom electrode, as shown in Figure 5。Bottom electrode layer 150 and pinning layer 160 are illustrated as and offset with described cross tie part 40。But, it is possible to provide other is arranged。For example, bottom electrode layer 150 and pinning layer 160 can be directed at cross tie part 40。The size of bottom electrode layer 150, pinning layer 160 and cross tie part 40 is also not necessarily limited to illustrated layout。For example, the big I of bottom electrode layer 150 and pinning layer 160 more than, less than or equal to the size of cross tie part 40。
According to an one exemplary embodiment, do not apply photoetching and etching technique to form any critical size of described MTJ storage element。Namely, tunneling potential barrier 190 (such as, seeing Fig. 7) and pinning layer 160 (such as, seeing Fig. 5) and free layer 200 is (such as, see Fig. 7) interface be not exposed to any etching or cleaning, avoid some in the foregoing problems of conventional method whereby。
It follows that as shown in Figure 6, interlayer dielectric (ILD) 70 is deposited on bottom electrode layer 150 and pinning layer 160, and hole 180 is patterned and is etched in described ILD70 downwards up to described pinning layer 160。Can more than the size X2 of the contact area between pinning layer 160 and tunneling potential barrier 190 referring to Figure 10, the size X1 of bottom electrode layer 150 and pinning layer 160, this allows the bigger tolerance limit when being patterned and etched in ILD70 in hole 180。ILD70 can be identical or different with the electrolyte being filled in around cross tie part 40。
Fig. 7 illustrates to form tunneling potential barrier 190, free layer 200 and top electrodes 210 on ILD70 and hole 180。In particular, as it is shown in fig. 7, tunneling potential barrier 190 is formed on ILD70 and hole 180, so that a part for tunneling potential barrier 190 is placed on the sidewall in hole 180 and is perpendicular to described bottom electrode (such as, bottom electrode layer 150 and pinning layer 160)。Free layer 200 is subsequently formed in tunneling potential barrier 190, so that a part for free layer 200 is also perpendicularly to bottom electrode layer 150 and pinning layer 160。Top electrodes 210 be formed at the free layer 200 that is placed in hole 180 at least some of on, at least fill the remainder in hole 180 whereby。As it is shown in fig. 7, top electrodes 210 can be formed on whole free layer 200。
It follows that some parts that exemplary method (such as) is placed in tunneling potential barrier 190 above hole 180, free layer 200 and top electrodes 210 by polishing (such as, chemically mechanical polishing (CMP)) to remove。As shown in Figure 8, the STTMRAM bit location with MTJ storage element is formed。
One exemplary embodiment advantageously allows for reducing the number of the photomask used in process。For example, two photomasks can be used to replace three masks。And, according to described embodiment, for critical size, it is not necessary to heavy metal etch process。Additionally, the leakage path that lateral wall polymer longeron brings out can be reduced or eliminate。
Additionally, according to described embodiment, the tunneling potential barrier of MTJ is not exposed to ashing and cleaning procedure。Additionally, described embodiment can provide bigger bottom fixed layer compared with conventional method, this can make bottom fixed layer that the astray field influence of top free layer is minimized。
Fig. 9 is the flow chart showing the exemplary method forming STT-MRAM bit cell according to an embodiment。Described method includes: deposited bottom electrode layer and pinning layer (such as, 910) on the metal layer, and is patterned and etched into described bottom electrode layer and described pinning layer to form the bottom electrode (such as, 920) of described MTJ storage element。It follows that described method includes: dielectric layer deposition (such as, 930) in described bottom electrode layer and described pinning layer, and in described dielectric layer, pattern a hole and described hole is etched down to described pinning layer (such as, 940)。Described method further includes at and deposits tunneling potential barrier, free layer and top electrodes on described hole, a part for one in wherein said tunneling potential barrier and described free layer is along the sidewall in described hole and is perpendicular to described bottom electrode layer and described pinning layer and disposes (such as, 950)。Additionally, described method includes the some parts (such as, 960) removing the described tunneling potential barrier of the overthe openings being placed in described hole, described free layer and described top electrodes。
According to exemplary method, it is possible to provide through the MTJ storage element of isolation。As explained above, one exemplary embodiment advantageously allows for reducing the number of the photomask used in process。For example, two photomasks can be used to replace three masks。And, according to described one exemplary embodiment, for critical size, it is not necessary to heavy metal etch process。Additionally, the leakage path that lateral wall polymer longeron brings out can be reduced or eliminate。
Additionally, according to described embodiment, the tunneling potential barrier of MTJ is not exposed to ashing and cleaning procedure。Additionally, described embodiment can provide bigger bottom fixed layer compared with conventional method, this can minimize the bottom fixed layer astray field influence to top free layer。
For example, as shown in Figure 10, an embodiment of MTJ (MTJ) memory element includes bottom electrode layer 150 and pinning layer 160, and pinning layer 160 is adjacent to bottom electrode layer 150 (such as, in bottom electrode layer 150 above and over)。Dielectric layer 70 encapsulates bottom electrode layer 150 and a part for pinning layer 160, wherein dielectric layer 70 include defining be adjacent to pinning layer 160 a part (such as, above a part for pinning layer 160 or expose the part of pinning layer 160) the sidewall in hole 180 (such as, seeing Fig. 6)。Tunneling potential barrier 190 is adjacent to pinning layer 160 (such as, in pinning layer 160 above and over)。Free layer 200 is adjacent to tunneling layer 190 (such as, in tunneling layer 190 above and over)。Top electrodes 210 is adjacent to free layer 200 (such as, in free layer 200 above and over)。
As seen in the embodiment shown in fig. 10, the size X1 of bottom electrode layer 150 and/or pinning layer 160 can more than the size X2 of the contact area between pinning layer 160 and tunneling potential barrier 190, and this allows the bigger tolerance limit when being patterned and etched in ILD70 by hole 180 for the tunneling potential barrier 190 of storage, free layer 200 and top electrodes 210。And, as shown in Figure 10, a part for the one in tunneling potential barrier 190 and free layer 200 is along the sidewall in hole 180 and is perpendicular to bottom electrode layer 150 and pinning layer 160 and disposes。Top electrodes 210 fills the part being adjacent to free layer 200 (such as, in free layer 200 above and over) in hole 180。
Those skilled in the art will realize that in other embodiments, the size of bottom electrode layer 150 and/or pinning layer 160 can equal to or less than tunneling potential barrier 190, as Figure 11 exemplarily shows。As shown in figure 11, a part for the one in tunneling potential barrier 190 and free layer 200 along the sidewall in hole 180 and is perpendicular to bottom electrode layer 150 and pinning layer 160 and disposes。Top electrodes 210 fills the part being adjacent to free layer 200 (such as, in described free layer 200 above and over) in hole 180。
Comparatively speaking, in conventional MTJ storage element and its forming method, bottom electrode layer 50, pinning layer 60, tunneling barrier layer 90, free layer 100 and top electrodes 110 stand patterning and etching, this causes that each in bottom electrode layer 50, pinning layer 60, tunneling barrier layer 90, free layer 100 and top electrodes 110 has same size X0, as shown in figure 12。And, in conventional MTJ storage element, the barrier oxide layer near MTJ sidewall is likely to be subject to technological process (that is, ashing and cleaning procedure) impact, and then produces thicker tunneling potential barrier 90 near MTJ sidewall, as shown in figure 13。The impact of thicker tunneling potential barrier 90 will be significant for scaled feature。
According to exemplary method, it is possible to provide through the MTJ storage element of isolation。As explained above, one exemplary embodiment advantageously allows for reducing the number of the photomask used in process。For example, two photomasks can be used to replace three masks。And, according to described one exemplary embodiment, for critical size, it is not necessary to heavy metal etch process。Additionally, the leakage path that lateral wall polymer longeron brings out can be reduced or eliminate。
Additionally, according to described embodiment, the tunneling potential barrier of MTJ is not exposed to ashing and cleaning procedure, reduce or avoid tunneling potential barrier thickening of adjacent sidewalls at described MTJ whereby。Additionally, described embodiment can provide bigger bottom fixed layer compared with conventional method, this can make bottom fixed layer that the astray field influence of top free layer is minimized。
Should be appreciated that, storage arrangement including MTJ storage element described herein can be included in the portable data units such as mobile phone, portable computer, handheld personal communication systems (PCS) unit, such as personal digital assistant (PDA), have the fixed position data cell such as the device of GPS function, guider, Set Top Box, music player, video player, amusement unit, such as meter reading equipment or other device any of storage or retrieval data or computer instruction, or in its any combination。Therefore, embodiments of the invention can be applied to including in any device of efficient integrated circuit (it memorizer including having MTJ storage element as disclosed herein) suitably。
Aforementioned disclosed apparatus and method can be designed and can be configured to GDSII and the GERBER computer documents being stored on computer-readable media。These files are provided to again the manufacture disposer manufacturing device based on these files。Products obtained therefrom is semiconductor wafer, and it is then cut into semiconductor die and is packaged in semiconductor chip。Described chip is then used in said apparatus。
Therefore, embodiment can include the machine-readable medium or the computer-readable media that comprise instruction, described instruction when being performed by processor, described processor and other collaboration elements any are changed into for perform by as described in described herein functional machine of realizing of instruction。
Although foregoing disclosure shows illustrative embodiment, it should be noted that can be variously modified in this article when not necessarily departing from the scope of the present invention defined such as appended claims and revise。Without being performed in any particular order the function of claim to a method item according to embodiment described herein, step and/or action。Although additionally, be likely to be described or claimed in the element of described embodiment with odd number, but being limited to odd number unless specifically stated, otherwise it is also contemplated that plural number。

Claims (37)

1. having a storage arrangement for MTJ (MTJ) memory element, described MTJ storage element comprises: bottom electrode；
Pinning layer, it is adjacent to described bottom electrode；
Dielectric layer, it encapsulates a part for described bottom electrode and described pinning layer, and wherein said dielectric layer includes the sidewall defining the hole of the part being adjacent to described pinning layer；
Tunneling potential barrier, it is adjacent to described pinning layer；
Free layer, it is adjacent to described tunneling potential barrier, a part for one in wherein said tunneling potential barrier and described free layer is along the sidewall in described hole and is perpendicular to described bottom electrode and described pinning layer and disposes, and the remainder of the one in described tunneling potential barrier and described free layer is parallel to described bottom electrode and described pinning layer and disposes, wherein said pinning layer laterally attaches to described bottom electrode, so that described pinning layer is separating with described tunneling potential barrier and described free layer in the described sidewall direction in described hole；And
Top electrodes, it is adjacent to described free layer,
Wherein said bottom electrode and/or described pinning layer width in a first direction are more than the width in said first direction of the contact area between described pinning layer and described tunneling potential barrier。
2. storage arrangement according to claim 1, wherein said top electrodes fills a described hole part above described free layer。
3. storage arrangement according to claim 1, wherein said tunneling potential barrier has a U-shaped cross-section with the first and second supporting legs, and wherein said first supporting leg extends along the described sidewall in described hole。
4. storage arrangement according to claim 3, wherein said free layer has U-shaped cross-section and is nested in the tunneling potential barrier of described U-shaped。
5. storage arrangement according to claim 1, wherein said storage arrangement is applied to wherein be integrated with in the electronic installation of described storage arrangement, the group of described electronic installation choosing freely following thing composition: Set Top Box, music player, video player, amusement unit, guider, communicator, personal digital assistant (PDA), fixed position data cell and computer。
6. storage arrangement according to claim 1, wherein said storage arrangement is spin transfer torque magnetoresistive random access memory (STT-MRAM)。
7. the method that formation has the storage arrangement of MTJ (MTJ) memory element, described method comprises: form bottom electrode on substrate；
Described bottom electrode is formed pinning layer；
Dielectric layer deposition on described bottom electrode and described pinning layer；
In described dielectric layer, patterning has the hole of sidewall and described hole is etched down to described pinning layer；
The Part I in described hole deposits tunneling barrier layer to produce tunneling potential barrier on described pinning layer；
The Part II in described hole deposits free layer so that described free layer is positioned in described tunneling potential barrier, wherein along the described sidewall in described hole and be perpendicular to described bottom electrode and described pinning layer and form a part for one in described tunneling potential barrier and described free layer, and the remainder of the one in described tunneling potential barrier and described free layer is parallel to described bottom electrode and described pinning layer and disposes, wherein said pinning layer laterally attaches to described bottom electrode, so that described pinning layer is separating with described tunneling potential barrier and described free layer in the described sidewall direction in described hole；And
Described free layer deposits top layers。
8. method according to claim 7, wherein said bottom electrode and/or described pinning layer width in a first direction are more than the width in said first direction of the contact area between described pinning layer and described tunneling potential barrier。
9. method according to claim 7, wherein said top electrodes fills the remainder in described hole on described free layer。
10. method according to claim 7, wherein said tunneling potential barrier has a U-shaped cross-section with the first and second supporting legs, and wherein said first supporting leg extends along the described sidewall in described hole。
11. method according to claim 10, wherein said free layer has U-shaped cross-section and is nested in the tunneling potential barrier of described U-shaped。
12. method according to claim 7, it comprises further:
Described bottom electrode layer and described pinning layer was cleaned before the described dielectric layer of described deposition。
13. method according to claim 12, it comprises further:
Described bottom electrode and described pinning layer it was patterned and etched into before described cleaning。
14. method according to claim 13, it comprises further:
Described be patterned and etched into described bottom electrode and described pinning layer before make described bottom electrode and described pinning layer stand magnetic annealing technique in a vacuum。
15. method according to claim 7, wherein described tunneling potential barrier, described free layer and described top electrodes are deposited on described dielectric layer and described hole。
16. method according to claim 7, they some parts including removing the described tunneling potential barrier of the overthe openings being placed in described hole, described free layer and described top electrodes。
17. method according to claim 16, the wherein said described some parts removing described tunneling potential barrier, described free layer and described top electrodes include described some parts of the described tunneling potential barrier of the described overthe openings being placed in described hole, described free layer and described top electrodes are carried out chemically mechanical polishing。
18. method according to claim 7, wherein it is applied to wherein be integrated with in the electronic installation of described storage arrangement by described storage arrangement, the group of described electronic installation choosing freely following thing composition: Set Top Box, music player, video player, amusement unit, guider, communicator, personal digital assistant (PDA), fixed position data cell and computer。
19. method according to claim 7, wherein said storage arrangement is spin transfer torque magnetoresistive random access memory (STT-MRAM)。
20. have a storage arrangement for MTJ (MTJ) memory element, described MTJ storage element comprises:
For electrically connecting the bottom conductive device of described MTJ storage element；
For keeping the first magnetic devices of the first polarization, described first magnetic devices is adjacent to described bottom conductive device；
For encapsulating the first seal of a part for described bottom conductive device and described first magnetic devices, wherein said first seal includes the sidewall defining the hole of the part being adjacent to described first magnetic devices；
For keeping the second magnetic devices of the second polarization, wherein said second polarization is reversible；
For making the second seal that the electric current of flowing is tunneling between described first magnetic devices and described second magnetic devices, described second seal separates described first magnetic devices and described second magnetic devices, a part for one in wherein said second seal and described second magnetic devices is along the sidewall in described hole and is perpendicular to described bottom conductive device and described first magnetic devices and disposes, and the remainder of the one in described second seal and described second magnetic devices is parallel to described bottom conductive device and described first magnetic devices and disposes, wherein said first magnetic devices laterally attaches to described bottom conductive device, so that described first magnetic devices is separating with described second seal and described second magnetic devices in the described sidewall direction in described hole；And
For electrically connecting the top conductive device of described MTJ storage element, described top conductive device is adjacent to described second magnetic devices,
Wherein said bottom conductive device and/or described first magnetic devices width in a first direction are more than the width in said first direction of the contact area between described first magnetic devices and described second seal。
21. storage arrangement according to claim 20, wherein said top conductive device fills a described hole part above described second magnetic devices。
22. storage arrangement according to claim 20, wherein said second seal has a U-shaped cross-section with the first and second supporting legs, and wherein said first supporting leg extends along the described sidewall in described hole。
23. storage arrangement according to claim 22, wherein said second magnetic devices has U-shaped cross-section and is nested in described U-shaped the second seal。
24. storage arrangement according to claim 20, wherein said storage arrangement is applied to wherein be integrated with in the electronic installation of described storage arrangement, the group of described electronic installation choosing freely following thing composition: Set Top Box, music player, video player, amusement unit, guider, communicator, personal digital assistant (PDA), fixed position data cell and computer。
25. storage arrangement according to claim 20, wherein said storage arrangement is spin transfer torque magnetoresistive random access memory (STT-MRAM)。
26. formation has a method for the storage arrangement of MTJ (MTJ) memory element, described method comprises:
For forming the step of bottom electrode on substrate；
For forming the step of pinning layer on described bottom electrode；
For the step of dielectric layer deposition on described bottom electrode and described pinning layer；
There is the hole of sidewall for patterning in described dielectric layer and described hole is etched down to the step of described pinning layer；
For depositing tunneling barrier layer in the Part I in described hole to produce the step of tunneling potential barrier on described pinning layer；
For depositing free layer in the Part II in described hole so that described free layer is positioned at the step in described tunneling potential barrier, wherein along the described sidewall in described hole and be perpendicular to described bottom electrode and described pinning layer and form a part for one in described tunneling potential barrier and described free layer, and the remainder of the one in described tunneling potential barrier and described free layer is parallel to described bottom electrode and described pinning layer and disposes, wherein said pinning layer laterally attaches to described bottom electrode, so that described pinning layer is separating with described tunneling potential barrier and described free layer in the described sidewall direction in described hole；And
For depositing the step of top layers on described free layer。
27. method according to claim 26, wherein said bottom electrode and/or described pinning layer width in a first direction are more than the width in said first direction of the contact area between described pinning layer and described tunneling potential barrier。
28. method according to claim 26, wherein said top electrodes fills described hole remainder above described free layer。
29. method according to claim 26, wherein said tunneling potential barrier has a U-shaped cross-section with the first and second supporting legs, and wherein said first supporting leg extends along the described sidewall in described hole。
30. method according to claim 29, wherein said free layer has U-shaped cross-section and is nested in the tunneling potential barrier of described U-shaped。
31. method according to claim 26, it comprises further: for cleaning described bottom electrode layer and the step of described pinning layer before the described dielectric layer of described deposition。
32. method according to claim 31, it comprises further:
For being patterned and etched into the step of described bottom electrode and described pinning layer before described cleaning。
33. method according to claim 32, it comprises further:
For described be patterned and etched into described bottom electrode and described pinning layer before make described bottom electrode and described pinning layer stand magnetic annealing technique in a vacuum step。
34. method according to claim 26, wherein described tunneling potential barrier, described free layer and described top electrodes are deposited on described dielectric layer and described hole。
35. method according to claim 26, it includes the step of the some parts for removing the described tunneling potential barrier of the overthe openings being placed in described hole, described free layer and described top electrodes。
36. method according to claim 26, wherein it is applied to wherein be integrated with in the electronic installation of described storage arrangement by described storage arrangement, the group of described electronic installation choosing freely following thing composition: Set Top Box, music player, video player, amusement unit, guider, communicator, personal digital assistant (PDA), fixed position data cell and computer。
37. method according to claim 26, wherein said storage arrangement is spin transfer torque magnetoresistive random access memory (STT-MRAM)。
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