CN105680687A - Inverse time-delay booster circuit - Google Patents
Inverse time-delay booster circuit Download PDFInfo
- Publication number
- CN105680687A CN105680687A CN201610024695.6A CN201610024695A CN105680687A CN 105680687 A CN105680687 A CN 105680687A CN 201610024695 A CN201610024695 A CN 201610024695A CN 105680687 A CN105680687 A CN 105680687A
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- pmos
- booster circuit
- circuit
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
Abstract
The invention provides an inverse time-delay booster circuit for the boosting requirements of chip integrated circuits. The inverse time-delay booster circuit is characterized by comprising a PMOS tube Q1, an NMOS tube Q2, a PMOS tube Q3, an NMOS tube Q4 and an inverter T1, wherein the PMOS tube Q1 is connected with the NMOS tube Q2 in series between a first power supply terminal and a ground terminal; grids of the PMOS tube Q1 and the NMOS tube Q2 are connected to an input end of a circuit; a series joint of the PMOS tube Q1 and the NMOS tube Q2 is connected to the input end of the inverter T1; the PMOS tube Q3 is connected to the NMOS tube Q4 in series between a second power supply terminal and the ground terminal; the grids of the PMOS tube Q3 and the NMOS tube Q4 are connected to an output end of the inverter T1; the series joint of the PMOS tube Q3 and the NMOS tube Q4 is connected to the output end of the circuit; and the voltage of the second power supply terminal is greater than that of the first power supply terminal. The inverse time-delay booster circuit can provide stable boost for the chip integrated circuit, meets the driving force requirements on a follow-up circuit, and has the characteristics of being simple in structure, stable in driving force, small in volume, excellent in voltage resistance and the like.
Description
Technical field
The present invention relates to a kind of anti-phase time delay booster circuit being applied in chip integrated circuit.
Background technology
Commonly use boost function in the middle of chip integrated circuit, low level voltage upgrade conversion is become required high level voltage output, to meet the requirement of driving force. Boosting means conventional in circuit common are flyback boosting circuits, being made up of elements such as switch member, inductance and electric capacity, and inductance element is applied to increase in the middle of chip the difficulty of circuit design, one is that inductance volume is bigger,, two is that oscillating electromotive force is easily damaged chip circuit. It practice, chip integrated circuit is it is desirable that boost smoothly, its output voltage need to not significantly high yet.
Summary of the invention
For the boosting demand of chip integrated circuit, the present invention proposes a kind of anti-phase time delay booster circuit, and its concrete technical scheme is as follows:
A kind of anti-phase time delay booster circuit, including PMOS Q1, NMOS tube Q2, PMOS Q3, NMOS tube Q4 and phase inverter T1, described PMOS Q1 and NMOS tube Q2 is connected in series between the first power end and ground end, the grid of the two is commonly connected to the input of circuit, and the series connection Node connectedness of the two is connected to the input of described phase inverter T1; Described PMOS Q3 and NMOS tube Q4 is connected in series between second source end and ground end, and the grid of the two is commonly connected to the outfan of phase inverter T1, and the series connection Node connectedness of the two is connected to the outfan of circuit; The voltage of described second source end is more than the voltage of the first power end.
In the middle of one or more embodiments of the invention, the source electrode of described PMOS Q1 connects described first power end, and its drain electrode connects the source electrode of described NMOS tube Q2, and the drain electrode of described NMOS tube Q2 connects earth terminal; The source electrode of described PMOS Q3 connects described second source end, and its drain electrode connects the source electrode of described NMOS tube Q4, and the drain electrode of described NMOS tube Q4 connects earth terminal.
In the middle of one or more embodiments of the invention, the outfan of described phase inverter T1 is provided with filter capacitor C1, and the outfan of described anti-phase time delay booster circuit is provided with filter capacitor C2.
In the middle of one or more embodiments of the invention, the voltage of described first power end is+5V, and the voltage of described second source end is+10V to+25V.
The present invention can provide boosting smoothly for chip integrated circuit, meets the driving force demand to subsequent conditioning circuit, and circuit output is compared to the former delayed half period of clock square wave, produces the driving signal anti-phase with the clock cycle. Circuit structure of the present invention is simple, and driving force is steady, and has the features such as little, the pressure excellent performance of volume.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of the anti-phase time delay booster circuit of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing 1, the application scheme is further described:
A kind of anti-phase time delay booster circuit, including PMOS Q1, NMOS tube Q2, PMOS Q3, NMOS tube Q4 and phase inverter T1, described PMOS Q1 and NMOS tube Q2 is connected in series between the first power end and ground end, the grid of the two is commonly connected to the input of circuit, and the series connection Node connectedness of the two is connected to the input of described phase inverter T1; Described PMOS Q3 and NMOS tube Q4 is connected in series between second source end and ground end, and the grid of the two is commonly connected to the outfan of phase inverter T1, and the series connection Node connectedness of the two is connected to the outfan of circuit; The voltage of described second source end is more than the voltage of the first power end.
The source electrode of described PMOS Q1 connects described first power end, and its drain electrode connects the source electrode of described NMOS tube Q2, and the drain electrode of described NMOS tube Q2 connects earth terminal; The source electrode of described PMOS Q3 connects described second source end, and its drain electrode connects the source electrode of described NMOS tube Q4, and the drain electrode of described NMOS tube Q4 connects earth terminal.
The outfan of described phase inverter T1 is provided with filter capacitor C1, and the outfan of described anti-phase time delay booster circuit is provided with filter capacitor C2.
The voltage of described first power end is+5V, and the voltage of described second source end is+15V, produces to delay the high voltage output of half period.
Above-mentioned preferred implementation should be regarded as the illustration of the application scheme embodiment, all identical with the application scheme, approximate or make based on this technology deduction, replacement, improvement etc., be regarded as the protection domain of this patent.
Claims (4)
1. an anti-phase time delay booster circuit, it is characterized in that: include PMOS Q1, NMOS tube Q2, PMOS Q3, NMOS tube Q4 and phase inverter T1, described PMOS Q1 and NMOS tube Q2 is connected in series between the first power end and ground end, the grid of the two is commonly connected to the input of circuit, and the series connection Node connectedness of the two is connected to the input of described phase inverter T1; Described PMOS Q3 and NMOS tube Q4 is connected in series between second source end and ground end, and the grid of the two is commonly connected to the outfan of phase inverter T1, and the series connection Node connectedness of the two is connected to the outfan of circuit; The voltage of described second source end is more than the voltage of the first power end.
2. anti-phase time delay booster circuit according to claim 1, it is characterised in that: the source electrode of described PMOS Q1 connects described first power end, and its drain electrode connects the source electrode of described NMOS tube Q2, and the drain electrode of described NMOS tube Q2 connects earth terminal; The source electrode of described PMOS Q3 connects described second source end, and its drain electrode connects the source electrode of described NMOS tube Q4, and the drain electrode of described NMOS tube Q4 connects earth terminal.
3. anti-phase time delay booster circuit according to claim 2, it is characterised in that: the outfan of described phase inverter T1 is provided with filter capacitor C1, and the outfan of described anti-phase time delay booster circuit is provided with filter capacitor C2.
4. the anti-phase time delay booster circuit according to claim 1 or 2 or 3, it is characterised in that: the voltage of described first power end is+5V, and the voltage of described second source end is+10V to+25V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610024695.6A CN105680687A (en) | 2016-01-15 | 2016-01-15 | Inverse time-delay booster circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610024695.6A CN105680687A (en) | 2016-01-15 | 2016-01-15 | Inverse time-delay booster circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105680687A true CN105680687A (en) | 2016-06-15 |
Family
ID=56300849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610024695.6A Pending CN105680687A (en) | 2016-01-15 | 2016-01-15 | Inverse time-delay booster circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105680687A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4758743A (en) * | 1986-09-26 | 1988-07-19 | Motorola, Inc. | Output buffer with improved di/dt |
| US4797579A (en) * | 1987-07-27 | 1989-01-10 | Raytheon Company | CMOS VLSI output driver with controlled rise and fall times |
| US4958086A (en) * | 1989-05-08 | 1990-09-18 | Motorola, Inc. | Low di/dt output buffer with improved speed |
| US5397940A (en) * | 1992-07-14 | 1995-03-14 | U.S. Philips Corporation | Buffer system with reduced interference |
| US5500610A (en) * | 1993-10-08 | 1996-03-19 | Standard Microsystems Corp. | Very high current integrated circuit output buffer with short circuit protection and reduced power bus spikes |
| EP1143451A1 (en) * | 2000-03-29 | 2001-10-10 | STMicroelectronics S.r.l. | Low-consumption charge pump for a nonvolatile memory |
| CN101053157A (en) * | 2004-09-08 | 2007-10-10 | 皇家飞利浦电子股份有限公司 | Fast switching circuit with input hysteresis |
| CN103795396A (en) * | 2014-02-24 | 2014-05-14 | 中山芯达电子科技有限公司 | Circuit structure for eliminating short circuit currents |
| CN203813657U (en) * | 2014-03-24 | 2014-09-03 | 上海智浦欣微电子有限公司 | Power supply self-adaptive charge pump device |
-
2016
- 2016-01-15 CN CN201610024695.6A patent/CN105680687A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4758743A (en) * | 1986-09-26 | 1988-07-19 | Motorola, Inc. | Output buffer with improved di/dt |
| US4797579A (en) * | 1987-07-27 | 1989-01-10 | Raytheon Company | CMOS VLSI output driver with controlled rise and fall times |
| US4958086A (en) * | 1989-05-08 | 1990-09-18 | Motorola, Inc. | Low di/dt output buffer with improved speed |
| US5397940A (en) * | 1992-07-14 | 1995-03-14 | U.S. Philips Corporation | Buffer system with reduced interference |
| US5500610A (en) * | 1993-10-08 | 1996-03-19 | Standard Microsystems Corp. | Very high current integrated circuit output buffer with short circuit protection and reduced power bus spikes |
| EP1143451A1 (en) * | 2000-03-29 | 2001-10-10 | STMicroelectronics S.r.l. | Low-consumption charge pump for a nonvolatile memory |
| CN101053157A (en) * | 2004-09-08 | 2007-10-10 | 皇家飞利浦电子股份有限公司 | Fast switching circuit with input hysteresis |
| CN103795396A (en) * | 2014-02-24 | 2014-05-14 | 中山芯达电子科技有限公司 | Circuit structure for eliminating short circuit currents |
| CN203813657U (en) * | 2014-03-24 | 2014-09-03 | 上海智浦欣微电子有限公司 | Power supply self-adaptive charge pump device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160615 |
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| RJ01 | Rejection of invention patent application after publication |