CN105677951B - A kind of fast square root integrated circuit - Google Patents
A kind of fast square root integrated circuit Download PDFInfo
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- CN105677951B CN105677951B CN201511021266.5A CN201511021266A CN105677951B CN 105677951 B CN105677951 B CN 105677951B CN 201511021266 A CN201511021266 A CN 201511021266A CN 105677951 B CN105677951 B CN 105677951B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F30/39—Circuit design at the physical level
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Abstract
The invention discloses a kind of fast square root integrated circuit, including eight bit signal input terminal, evolution data prediction circuit, Maclaurin expansion computing circuit, signal output end and result output circuit for being shifted to Maclaurin expansion computing circuit output result；The present invention is not necessarily to iteration, and arithmetic speed is fast.
Description
Technical field
The invention belongs to IC design fields, are related to a kind of fast square root integrated circuit.
Background technique
With the high speed development of large scale integrated circuit and digital communication, more and more Digital Signal Processing require to open flat
The hardware of the operations such as side is realized.As the operations such as extracting operation and addition, multiplication, complementation, being all must can not in Industrial Engineering
Few a part.Realize that the algorithm of extraction of square root mainly has Newton iteration method, by turn round-robin algorithm etc. at present.The realization of these algorithms
It is mostly by software program, arithmetic speed is far below specific integrated circuit.The hardware circuit of even special extraction of square root,
Also Newton iteration method or by turn round-robin algorithm etc. are substantially used.Such circuit is required to interative computation, and speed is relatively slow.
Summary of the invention
It is an object of the invention to overcome the above-mentioned prior art, a kind of fast square root integrated circuit is provided, it should
Circuit is not necessarily to iteration, and arithmetic speed is fast.
In order to achieve the above objectives, fast square root integrated circuit of the present invention includes eight bit signal input terminal, evolution number
Data preprocess circuit, Maclaurin expansion computing circuit, signal output end and for Maclaurin expansion operation electricity
The result output circuit that road output result is shifted；
The evolution data prediction circuit includes eight the first triggers, eight the second triggers, four inputs or door
Circuit, three input OR circuits, two input OR circuits, AND gate circuit, three output counters, clock signal input terminal and eight
Position data output end, eight bit signal input terminal is connected with the first input end in eight the first triggers respectively, and previous the
The output end of two triggers is connected with the second input terminal in the first trigger of the latter, the output of the first trigger of first four
End is connected with four input terminals of four input OR circuits respectively, the output end of the 5th the first trigger, the 6th the
Three input terminal phases that the output end of the output end of one trigger and the 7th the first trigger inputs OR circuits with three respectively
The output end of connection, the output end of four input OR circuits and three input OR circuits respectively with two input OR circuits two
A input terminal is connected, the output with clock signal input terminal and two input OR circuits respectively of two input terminals of AND gate circuit
End is connected, and the output end of AND gate circuit and input end of clock, the clock of eight the second triggers of eight the first triggers are defeated
The input terminal for entering end and three output counters is connected；
The output end of 8th the first trigger is connected with the input terminal of first the second trigger, previous second touching
The output end of hair device is connected with the input terminal of the second trigger of the latter, and eight bit data output end is triggered with eight second respectively
The output end of device is connected, and eight bit data output end is connected with the input terminal of Maclaurin expansion computing circuit, and three defeated
The output end of the output end of counter and Maclaurin expansion computing circuit is connected with the input terminal of result output circuit out,
As a result the output end of output circuit is connected with signal output end.
The Maclaurin expansion computing circuit includes squarer, cube device, the first shift circuit, the second displacement electricity
The input terminal of road, third shift circuit and adder, eight bit data output end and the first shift circuit, the input terminal of squarer and
The input terminal of cube device is connected, and the output end of squarer is connected with the input terminal of the second shift circuit, the output of cube device
End is connected with the input terminal of third shift circuit, the output end of the first shift circuit, the output end of the second shift circuit and the
The output end of three shift circuits is connected with the input terminal of adder, the output end of adder and the input terminal of result output circuit
It is connected.
The result output circuit includes not circuit, third trigger, the 4th trigger, the 5th trigger, the 4th shifting
Position circuit, the 5th shift circuit, multiplier and selector, three output ends of three output counters respectively with third trigger
Input terminal, the input terminal of the 4th trigger and the input terminal of the 5th trigger be connected, the output end of third trigger and
The output end of the output end of four triggers and the 5th trigger be connected after with the enable signal input terminal of the 4th shift circuit, non-
The input terminal of gate circuit and the control terminal of selector are connected, the enable signal of the output end of not circuit and the 5th shift circuit
Input terminal is connected, and the output end of the 4th shift circuit and the output end of the 5th shift circuit are connected with the input terminal of selector
It connects, the output end of selector is connected with signal output end.
It further include 38 decoders for carrying out the output of accuracy flag position, three road input terminals of 38 decoders are respectively with first
The output end of the second trigger of the output end of a second trigger, the output end of second the second trigger and third is connected
It connects.
The course of work of Maclaurin expansion computing circuit are as follows: set the output signal of evolution data prediction circuit as x,
X becomes x through the first shift circuit becomes x through cube device and third displacement after squarer and the second shift circuit
Becoming adder output information after circuit is k, wherein
As a result the specific work process of output circuit are as follows: to the lowest order of the shift amount m of three output counters output
Value judged, when the lowest order of shift amount m is 0, then the k phase that Maclaurin expansion computing circuit exports is shifted left m/
2, and the result after displacement is output in signal output end；When the lowest order of shift amount m is 1, then by Maclaurin exhibition
Open type computing circuit output k phase shift left (m-1)/2, then again through multiplier multiplied byAfter be output to signal output end
In.
The invention has the following advantages:
Fast square root integrated circuit of the present invention during carrying out data operation, using Maclaurin expansion into
Row extracting operation is not necessarily to iteration, greatly improves the speed of operation, under 8 input data circuits of processing on an equal basis, relative to
Cyclic shift root circuit, arithmetic speed improves 4 times or more, while in practical application, can extend to the input of more multidigit
The superiority of data, speed will be bigger.
Further, accuracy flag position is provided by 38 decoders, provides precision digit for user, be more convenient to use.
Detailed description of the invention
Fig. 1 is the principle of the present invention figure；
Fig. 2 is the schematic diagram of evolution data prediction circuit 1 in the present invention；
Fig. 3 is the schematic diagram of Maclaurin expansion computing circuit 2 in the present invention；
Fig. 4 is the schematic diagram of result output circuit 3 in the present invention.
Wherein, 1 be evolution data prediction circuit, 2 be Maclaurin expansion computing circuit, 3 be result output circuit,
11 be the first trigger, 12 be the second trigger, 13 be four input OR circuits, 14 be three input OR circuits, 15 be two
Input OR circuit, 16 be AND gate circuit, 17 be 38 decoders, 18 be three output counters, 21 be squarer, 22 be cube
Device, 23 for the first shift circuit, 24 be the second shift circuit, 25 be third shift circuit, 26 be adder, 31 be third triggering
Device, 32 for the 4th trigger, 33 be the 5th trigger, 34 be not circuit, 35 be the 5th shift circuit, 36 be the 4th displacement electricity
Road, 37 be multiplier, 38 be selector.
Specific embodiment
The invention will be described in further detail with reference to the accompanying drawing:
Referring to Figure 1 and Figure 2, fast square root integrated circuit of the present invention includes eight bit signal input terminal, evolution data
It pre-processes circuit 1, Maclaurin expansion computing circuit 2, signal output end and is used for Maclaurin expansion operation electricity
Road 2 exports the result output circuit 3 that result is shifted；The evolution data prediction circuit 1 includes eight the first triggers
11, eight the second triggers, 12, four input OR circuits 13, three input OR circuit 14, two and input OR circuit 15 and door
16, three output counters 18 of circuit, clock signal input terminal and eight bit data output end, eight bit signal input terminal is respectively with eight
First input end in a first trigger 11 is connected, and the output end and the latter first of previous second trigger 12 trigger
The second input terminal in device 11 is connected, the output end of the first trigger of first four 11 respectively with four input OR circuits 13
Four input terminals are connected, the output end and the 7th of the output end of the 5th the first trigger 11, the 6th the first trigger 11
The output end of a first trigger 11 is connected with three input terminals of three input OR circuits 14 respectively, four inputs or door electricity
The output end of the output end on road 13 and three input OR circuits 14 is connected with two input terminals of two input OR circuits 15 respectively
It connects, two input terminals of AND gate circuit 16 are connected with the output end of clock signal input terminal and two input OR circuits 15 respectively
It connects, the output end of AND gate circuit 16 and input end of clock, the clock of eight the second triggers 12 of eight the first triggers 11 are defeated
The input terminal for entering end and three output counters 18 is connected；The output end of 8th the first trigger 11 and first second touching
The input terminal of hair device 12 is connected, the input terminal phase of the output end and the second trigger of the latter 12 of previous second trigger 12
Connection, eight bit data output end are connected with the output end of eight the second triggers 12 respectively, eight bit data output end and Mike
The input terminal of labor woods expansion computing circuit 2 is connected, the output end and Maclaurin expansion fortune of three output counters 18
The output end for calculating circuit 2 is connected with the input terminal of result output circuit 3, and as a result the output end of output circuit 3 and signal export
End is connected.
With reference to Fig. 3, the Maclaurin expansion computing circuit 2 includes squarer 21, cube device 22, the first shift circuit
23, the second shift circuit 24, third shift circuit 25 and adder 26, eight bit data output end are defeated with the first shift circuit 23
The input terminal for entering end, the input terminal of squarer 21 and cube device 22 is connected, the output end of squarer 21 and the second shift circuit
24 input terminal is connected, and the output end of cube device 22 is connected with the input terminal of third shift circuit 25, the first shift circuit
The input terminal phase of the output end of 23 output end, the output end of the second shift circuit 24 and third shift circuit 25 and adder 26
Connection, the output end of adder 26 are connected with the input terminal of result output circuit 3.
With reference to Fig. 4, the result output circuit 3 includes not circuit 34, third trigger 31, the 4th trigger 32, the
Five triggers 33, the 4th shift circuit 36, the 5th shift circuit 35, multiplier 37 and selector 38, three output counters 18
Three output ends it is defeated with the input terminal of third trigger 31, the input terminal of the 4th trigger 32 and the 5th trigger 33 respectively
Enter end to be connected, the output end of third trigger 31 and the output end of the 4th trigger 32 and the output end phase of the 5th trigger 33
After connection with the control terminal phase of the enable signal input terminal of the 4th shift circuit 36, the input terminal of not circuit 34 and selector 38
Connection, the output end of not circuit 34 are connected with the enable signal input terminal of the 5th shift circuit 35, the 4th shift circuit 36
Output end and the output end of the 5th shift circuit 35 be connected with the input terminal of selector 38, the output end and letter of selector 38
Number output end is connected.
In addition, the invention also includes three tunnels of 38 decoder, 17,38 decoder 17 for carrying out the output of accuracy flag position
Input terminal respectively with the output end of first the second trigger 12, the output end of second the second trigger 12 and third second
The output end of trigger 12 is connected.
The course of work of Maclaurin expansion computing circuit 2 are as follows: set the output signal of evolution data prediction circuit 1 as
X, x become through the first shift circuit 23X becomes after squarer 21 and the second shift circuit 24X passes through cube device 22
And become after third shift circuit 2526 output information of adder is k, wherein
As a result the specific work process of output circuit 3 are as follows: to three output counters 18 output shift amount m it is minimum
Place value judged, when the lowest order of shift amount m is 0, is then moved to left the k phase that Maclaurin expansion computing circuit 2 exports
Position m/2, and the result after displacement is output in signal output end；When the lowest order of shift amount m is 1, then by Mike's labor
Woods expansion computing circuit 2 export k phase shift left (m-1)/2, then again through multiplier 37 multiplied byAfter be output to signal
In output end.
The first trigger 11 is integer part in Fig. 2, and each second trigger 12 indicates data fractional part, circuit input
8 bits " t ", it latches outer input data " t ", and right shift processing is carried out in 11 chain of the first trigger, makes t
It is reduced into " 1.x ", that is, is " 1 " after moving to right to the last one second trigger 12 of integer part, high 7 are " 0 ", expire data
Sufficient operation requirement, the control of right shift are the output valve progress OR operations by high 7 the first triggers 11, and defeated by two
Enter 15 output valve of OR circuit and clock CLK is carried out and operation, if had " 1 " in high 7, clock can normally be conveyed to each touching
It sends out device and carries out right shift, if high 7 are " 0 ", clock will not be transported to each first trigger 11 and the second trigger
In 12, stops right shift, have the advantages that scale is very small and fireballing, while three output counters 18 are to shift amount
M is recorded, in conveying m value to result generation and output circuit.
Embodiment one
This circuit input data is 8 binary integers are asked by taking input " 17 " as an example
First trigger 11 and the second trigger 12 are the trigger of double-width grinding, Single-end output, " S " of the trigger
When end is " 0 ", i.e. low level, flip/flops latch " D0 " end data is equal to one by D0 input, the common triggering of the end Q output
Device；When end " S " of the trigger is " 1 ", i.e. high level, flip/flops latch " D1 " end data；When there is data input, selection
End " S " is placed in 0, i.e., 8 input datas is latched by D0, for example, 17=8 ' b00010001, it will in 8 triggers successively
" 0,0,0,1,0,0,0,1 ", data latch finishes, and end " S " is selected to be placed in 1, then starts to move to operate for latch.
Since the data of high 7 flip/flops latch are not all 0, as a result process or door operation are necessarily 1, by this result and
Clock CLK phase with so clock can pass through this and door at this time, then data move right, so by 6 clock cycle
Afterwards, high 7 triggers are all " 0 ", then pass through or door exports " 0 ", prevent clock from providing to the first trigger 11 and second
In trigger 12, displacement stopped, and the last one first trigger 11 centainly latches 1, at this time 8 the first triggers 11 and 8
The value that a second trigger 12 latches is followed successively by that " 0,0,0,0,0,0,0,1,0,0,0,1,0,0,0,0 ", first 8 are integer portion
Point, latter 8 are fractional part, i.e., the value that trigger is deposited at this time is metric " 1.0625 ", reduce 16 times compared to initial value.
Fractional part in pretreatment circuit will be delivered to Maclaurin expansion computing circuit 2, Maclaurin expansion
The output of computing circuit 2 1.03077, the as a result output of output circuit 3 4.1230 are similar to 4.1231 height of actual operation result.
Claims (4)
1. a kind of fast square root integrated circuit, which is characterized in that including eight bit signal input terminal, evolution data prediction circuit
(1), Maclaurin expansion computing circuit (2), signal output end and for Maclaurin expansion computing circuit (2)
The result output circuit (3) that output result is shifted；
The evolution data prediction circuit (1) include eight the first triggers (11), eight the second triggers (12), four it is defeated
Enter OR circuit (13), three inputs OR circuit (14), two inputs OR circuit (15), AND gate circuit (16), three output meters
Number device (18), clock signal input terminal and eight bit data output end, eight bit signal input terminal respectively with eight the first triggers
(11) first input end in is connected, in the output end and the first trigger of the latter (11) of previous first trigger (11)
The second input terminal be connected, the output end of the first trigger of first four (11) respectively with four input OR circuits (13) four
A input terminal is connected, the output end of the 5th the first trigger (11), the 6th the first trigger (11) output end and
The output end of seven the first triggers (11) is connected with three input terminals of three inputs OR circuit (14) respectively, four inputs
The output end of OR circuit (13) and the output end of three inputs OR circuit (14) input the two of OR circuit (15) with two respectively
A input terminal is connected, and two input terminals of AND gate circuit (16) input OR circuits with clock signal input terminal and two respectively
(15) output end is connected, the input end of clock of the output end of AND gate circuit (16) and eight the first triggers (11), eight
The input end of clock of second trigger (12) and the input terminal of three output counters (18) are connected；
The output end of 8th the first trigger (11) is connected with the input terminal of first the second trigger (12), and previous
The output end of two triggers (12) is connected with the input terminal of the second trigger of the latter (12), eight bit data output end respectively with
The output end of eight the second triggers (12) is connected, eight bit data output end and Maclaurin expansion computing circuit (2)
Input terminal is connected, the output end of the output ends of three output counters (18) and Maclaurin expansion computing circuit (2) with
As a result the input terminal of output circuit (3) is connected, and as a result the output end of output circuit (3) is connected with signal output end；
The Maclaurin expansion computing circuit (2) include squarer (21), cube device (22), the first shift circuit (23),
Second shift circuit (24), third shift circuit (25) and adder (26), eight bit data output end and the first shift circuit
(23) the input terminal of input terminal, squarer (21) and the input terminal of cube device (22) is connected, the output end of squarer (21)
It is connected with the input terminal of the second shift circuit (24), the output end of cube device (22) and the input terminal of third shift circuit (25)
It is connected, the output end of the first shift circuit (23), the output end of the second shift circuit (24) and third shift circuit (25)
Output end is connected with the input terminal of adder (26), the output end of adder (26) and the input terminal of result output circuit (3)
It is connected；
The course of work of Maclaurin expansion computing circuit (2) are as follows: set the output signal of evolution data prediction circuit (1) as
X, x become through the first shift circuit (23)X becomes after squarer (21) and the second shift circuit (24)X is through vertical
Become after square device (22) and third shift circuit (25)Adder (26) output information is k, wherein
2. fast square root integrated circuit according to claim 1, which is characterized in that the result output circuit (3) includes
Not circuit (34), third trigger (31), the 4th trigger (32), the 5th trigger (33), the 4th shift circuit (36),
Five shift circuits (35), multiplier (37) and selector (38), three output ends of three output counters (18) are respectively with
The input terminal of the input terminal of three triggers (31), the input terminal of the 4th trigger (32) and the 5th trigger (33) is connected, the
After the output end of three triggers (31) is connected with the output end of the output end of the 4th trigger (32) and the 5th trigger (33)
With the control terminal phase of the enable signal input terminal of the 4th shift circuit (36), the input terminal of not circuit (34) and selector (38)
Connection, the output end of not circuit (34) are connected with the enable signal input terminal of the 5th shift circuit (35), the 4th displacement electricity
The output end of the output end on road (36) and the 5th shift circuit (35) is connected with the input terminal of selector (38), selector (38)
Output end be connected with signal output end.
3. fast square root integrated circuit according to claim 1, which is characterized in that further include for carrying out accuracy flag position
38 decoders (17) of output, the output with first the second trigger (12) respectively of three road input terminals of 38 decoders (17)
The output end at end, the output end of second the second trigger (12) and third the second trigger (12) is connected.
4. fast square root integrated circuit according to claim 1, which is characterized in that the specific work of result output circuit (3)
Make process are as follows: judge the lowest-order values of the shift amount m of three output counters (18) output, when shift amount m's
Lowest order is 0, then by k shifted left m/2 of Maclaurin expansion computing circuit (2) output, and by the result after displacement
It is output in signal output end；When the lowest order of shift amount m is 1, then by Maclaurin expansion computing circuit (2) output
K shifted left (m-1)/2, then again through multiplier (37) multiplied byAfter be output in signal output end.
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| CN201511021266.5A CN105677951B (en) | 2015-12-30 | 2015-12-30 | A kind of fast square root integrated circuit |
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| CN105677951B true CN105677951B (en) | 2019-04-09 |
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| CN104038187A (en) * | 2014-06-27 | 2014-09-10 | 南开大学 | Integration series hybrid operation SPWM generator and achievement method |
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| US8271223B2 (en) * | 2006-11-22 | 2012-09-18 | Parkervision, Inc. | Multi-dimensional error definition, error measurement, error analysis, error function generation, error information optimization, and error correction for communications systems |
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|---|---|---|---|---|
| CN104038187A (en) * | 2014-06-27 | 2014-09-10 | 南开大学 | Integration series hybrid operation SPWM generator and achievement method |
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| Minimum component high frequency Gm-C wavelet filters based on Maclaurin series and multiple loop feedback;W. Zhao等;《ELECTRONICS LETTERS》;20100107;第46卷(第1期);全文 |
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