CN105657298B - A kind of digitalized snapshot-type infrared focal plane read-out circuit of column - Google Patents
A kind of digitalized snapshot-type infrared focal plane read-out circuit of column Download PDFInfo
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- CN105657298B CN105657298B CN201511019009.8A CN201511019009A CN105657298B CN 105657298 B CN105657298 B CN 105657298B CN 201511019009 A CN201511019009 A CN 201511019009A CN 105657298 B CN105657298 B CN 105657298B
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- adc
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/30—Transforming light or analogous information into electric information
- H04N5/33—Transforming infrared radiation
Abstract
The invention discloses a kind of digitalized snapshot-type infrared focal plane read-out circuits of column, relative to traditional infrared focal plane read-out circuit, the present invention substitutes column grade processing circuit and output buffer stage column grade analog/digital conversion circuit (ADC), direct output digit signals, i.e. realization on piece digitization system.And use two sets of clock pulses and two sets of power supplys, wherein low speed pulse and high power supply are used for pixel array processing unit and ADC pretreatment unit, the whole signal-to-noise ratio for advantageously reducing power consumption, increasing the amplitude of oscillation, improving reading circuit, and high-speed pulse and lower power supply are conducive to further decrease power consumption and read-out speed are greatly improved for arranging grade ADC processing unit.Finally, being different from traditional infrared circuit of focal plane readout parity rows series read-out, in such a way that odd row, even row are read respectively, read-out speed can be doubled again.
Description
Technical field
The present invention relates to detector technology field more particularly to a kind of digitalized snapshot-type infrared focal plane readout electricity of column
Road.
Background technique
Infrared Focal Plane Detection Technology have spectral response wide waveband, can get more land object informations, can work round the clock
The remarkable advantages such as work, are widely used in the tune of early warning detection, intelligence reconnaissance, Damage Effect Assessment and farming and animal husbandry, the forest reserves
It looks into, weather forecast, geothermal distribution, earthquake, colcanism, the military affairs such as space astrosurveillance and civil field.Stride into 21 century with
Come, Infrared Focal plane Array Technologies rapid development, forward direction ultra high density is integrated at present, high-performance, miniaturization and intelligence etc.
Direction is developed, and current traditional processing mode is to be read the analog signal of pixel by fixed read frequency.Meanwhile
Analog-to-digital conversion is carried out to the analog signal read out with the monolithic ADC outside a piece according to same read frequency, to realize
The digitlization of image element information, to facilitate next algorithm process etc..But this kind of mode with infrared focus plane scale not
It is disconnected to increase, very high requirement can be proposed to the conversion rate of ADC, while in circuit board level transmission process, it also can be to simulation
Signal brings certain interference, to reduce the signal-to-noise ratio of signal.
Summary of the invention
In view of above-mentioned analysis, the present invention is intended to provide a kind of arrange digitalized snapshot-type infrared focal plane read-out circuit,
Conversion rate to solve the problems, such as infrared focal plane read-out circuit ADC in the prior art is low.
To solve the above problems, the present invention is mainly achieved through the following technical solutions:
The present invention provides a kind of digitalized snapshot-type infrared focal plane read-out circuit of column, which includes:
Pixel array processing unit completes conversion, integral and the reset processing of photosignal for receiving optical signal, and
Signal after reset processing is sent respectively to odd row ADC pretreatment unit according to odd row, even row and idol row ADC pre-processes list
Member；
The surprise row ADC pretreatment unit and the even row ADC pretreatment unit, for pixel array processing is single
The signal that member is sent is handled, and the charge signal obtained after processing is converted to voltage signal, and by the voltage signal
It is sent respectively to odd row ADC processing unit and even row ADC processing unit；
The surprise row ADC processing unit and the even row ADC processing unit, for being believed simulation according to the voltage signal
It number is converted into digital signal and is exported by column；
The array scale of the pixel array processing unit is N × M, the surprise row ADC pretreatment unit and the even row
The array scale of ADC pretreatment unit is N × 1, the array of the surprise row ADC processing unit and the even row ADC processing unit
Scale is N × 1.
Preferably, the pixel array processing unit, the odd row ADC pretreatment unit and idol row ADC pretreatment
The low-speed clock control signal that unit is generated using low-speed clock control signal generating circuit is controlled；
The surprise row ADC processing unit and the even row ADC processing unit are using high-frequency clock control signal generating circuit
The high-frequency clock control signal of generation is controlled, and is powered by low power supply.
Preferably, the input of low-speed clock control signal generating circuit is low speed pulse and integral control signal INT,
And a series of internal clock control signal of circuit work, the internal clock control signal packet are generated based on the two signals
Include: row selection signal, column grade ADC work enable signal start_ADC, wherein row selection signal controls the pixel array processing
The signal of unit is sent respectively to odd row ADC pretreatment unit and even row ADC pretreatment unit, column grade ADC according to odd row, even row
The enable signal start_ADC control that the works odd row ADC processing unit and the even row ADC processing unit carry out modulus and turn
It changes；
The input of the high-frequency clock control signal generating circuit is high-speed pulse and column grade ADC work enable signal
Start_ADC generates the internal signal of the control odd row ADC processing unit and the even row ADC processing unit work.
Preferably, the high-speed pulse is 20-40MHz, and the low speed pulse is 1-5MHz.
Preferably, the pixel array processing unit, the odd row ADC pretreatment unit and idol row ADC pretreatment
Unit is powered by high power supply.
Preferably, the voltage of the high power supply is 3-5V.
Preferably, the odd row ADC processing unit and the even row ADC processing unit are powered by low power supply.
Preferably, the voltage of the low power supply is 1.8-3V.
The present invention has the beneficial effect that:
Relative to traditional infrared focal plane read-out circuit, the present invention is by column grade processing circuit and exports buffer stage column grade
Analog/digital conversion circuit (ADC) substitution, direct output digit signals, i.e. realization on piece digitization system.And use two sets of clocks
Pulse and two sets of power supplys, wherein low speed pulse and high power supply are used for pixel array processing unit and ADC pretreatment unit, are conducive to
The whole signal-to-noise ratio for reducing power consumption, increasing the amplitude of oscillation, improving reading circuit, and high-speed pulse and lower power supply are for arranging at grade ADC
Unit is managed, is conducive to further decrease power consumption and read-out speed is greatly improved.Finally, being different from the reading of traditional infrared focal plane
Circuit parity rows series read-out out can again double read-out speed in such a way that odd row, even row are read respectively.
Other features and advantages of the present invention will illustrate in the following description, and partial become from specification
It is clear that understand through the implementation of the invention.The objectives and other advantages of the invention can by written specification,
Specifically noted structure is achieved and obtained in claims and attached drawing.
Detailed description of the invention
Fig. 1 is the entire block diagram of the digitalized snapshot-type infrared focal plane read-out circuit of column of the invention.
Fig. 2 is the cycle timing diagram of one frame of reading circuit of the invention.
Specific embodiment
Specifically describing the preferred embodiment of the present invention with reference to the accompanying drawing, wherein attached drawing constitutes the application a part, and
Together with embodiments of the present invention for illustrating the principle of the present invention.For purpose of clarity and simplification, when it may make the present invention
Theme it is smudgy when, illustrating in detail for known function and structure in device described herein will be omitted.
Conversion rate in order to solve the problems, such as prior art infrared focal plane read-out circuit ADC is low, the present invention provides
A kind of digitalized snapshot-type infrared focal plane read-out circuit of column, below in conjunction with attached drawing and several embodiments, to the present invention into
Row is further described.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, this is not limited
Invention.
A kind of digitalized snapshot-type infrared focal plane read-out circuit of column provided in an embodiment of the present invention, referring to Fig. 1, the electricity
Road includes:
Pixel array processing unit completes conversion, integral and the reset processing of photosignal for receiving optical signal, and
Signal after reset processing is sent respectively to odd row ADC pretreatment unit according to odd row, even row and idol row ADC pre-processes list
Member；
The surprise row ADC pretreatment unit and the even row ADC pretreatment unit, for pixel array processing is single
The signal that member is sent is handled, and the charge signal obtained after processing is converted to voltage signal, and by the voltage signal
It is sent respectively to odd row ADC processing unit and even row ADC processing unit；
The surprise row ADC processing unit and the even row ADC processing unit, for being believed simulation according to the voltage signal
It number is converted into digital signal and is exported by column；
The array scale of the pixel array processing unit is N × M, the surprise row ADC pretreatment unit and the even row
The array scale of ADC pretreatment unit is N × 1, the array of the surprise row ADC processing unit and the even row ADC processing unit
Scale is N × 1.
Relative to traditional infrared focal plane read-out circuit, the present invention is by column grade processing circuit and exports buffer stage column grade
Analog/digital conversion circuit (ADC) substitution, direct output digit signals, i.e. realization on piece digitization system.And use two sets of clocks
Pulse and two sets of power supplys, wherein low speed pulse and high power supply are used for pixel array processing unit and ADC pretreatment unit, are conducive to
The whole signal-to-noise ratio for reducing power consumption, increasing the amplitude of oscillation, improving reading circuit, and high-speed pulse and lower power supply are for arranging at grade ADC
Unit is managed, is conducive to further decrease power consumption and read-out speed is greatly improved.Finally, being different from the reading of traditional infrared focal plane
Circuit parity rows series read-out out can again double read-out speed in such a way that odd row, even row are read respectively.
It should be noted that pixel array processing unit described in the embodiment of the present invention, the odd row ADC pretreatment unit and
The idol row ADC pretreatment unit is controlled using the low speed pulse that low-speed clock control signal generating circuit generates；
The surprise row ADC processing unit and the even row ADC processing unit are using high-frequency clock control signal generating circuit
The high-speed pulse of generation is controlled, and is powered by low power supply.
That is, the pixel array processing unit, the odd row ADC pretreatment unit and the even row ADC pretreatment unit
Using low speed pulse and high power supply；The surprise row ADC processing unit and the even row ADC processing unit are using high-speed pulse and low
Power supply.
Wherein, the high-speed pulse is 20-40MHz, and the low speed pulse is 1-5MHz, and the voltage of the high power supply is 3-
5V, the voltage of the low power supply are 1.8-3V.
When it is implemented, high-speed pulse, low speed pulse, the voltage of high power supply and low power supply voltage can be according to specific
Flow technique is selected, it should be noted that and high power supply of the present invention and low power supply are an opposite voltage values, if
When setting, it is only necessary to which the voltage value for the low power supply of ratio that the voltage value of high power supply is arranged is high, when it is implemented, the present invention uses
The voltage of high power supply be 5V, the voltage of low power supply is 3V, and realizing proves, circuit of the present invention can greatly improve circuit
Read-out speed.
The input that low-speed clock of the embodiment of the present invention controls signal generating circuit is low speed master clock MLclk and integration control
Signal INT, and a series of internal clock control signal that circuits work, the internal clocking control are generated based on the two signals
Signal includes: row selection signal, column grade ADC work enable signal start_ADC, and wherein row selection signal controls the pixel battle array
The signal of column processing unit is sent respectively to odd row ADC pretreatment unit and even row ADC pretreatment unit according to odd row, even row,
The column grade ADC work enable signal start_ADC control odd row ADC processing unit and the even row ADC processing unit carry out
Analog-to-digital conversion.
The input that high-frequency clock of the embodiment of the present invention controls signal generating circuit is high speed master clock MHclk and column grade ADC
What work enable signal start_ADC, the generation control odd row ADC processing unit and the even row ADC processing unit worked
Internal signal.
In actual design, since the scale of infrared focus plane is increasing, K grades of array to want in frame frequency easily
When asking relatively high, reading circuit analog signal has to transmitting to approach the frequency of even more than 100M Hz and be transmitted
Signal can be made to be very easy in the process disturbed, the signal-to-noise ratio of signal is caused to be deteriorated, for infrared detector, detection
Infrared signal is natively weaker, is easy by noise jamming, so the deterioration of signal-to-noise ratio is for the application of infrared detector
Be it is unacceptable, frame frequency high in this way brings very big pressure to the circuit design before circuit especially column grade ADC.So originally setting
Meter is using two sets of clock pulses are used, and wherein low speed pulse is used for pixel array processing unit and ADC pretreatment unit, is conducive to
Simplifying design reduces power consumption and improves the whole signal-to-noise ratio of reading circuit, and high-speed pulse is greatly improved for arranging grade ADC
Read-out speed, and then adapt to the application of high frame frequency.
Pixel array processing unit and ADC pretreatment unit use high power supply simultaneously, and such design improves circuit letter
Number the amplitude of oscillation, but since this several partial circuit is not the major consuming areas of power consumption, and low frequency operation is used, so power consumption
Increase be not obvious.And power consumption can be further decreased in the case where not influencing function using low power supply by arranging grade ADC.
Shown in referring to Fig.1, entire circuit includes following several parts:
1. the element circuit array of N × M scale receives optical signal, completes conversion, integral, the reset of photosignal.This
Circuit uses low speed pulse and high power supply.
2. the ADC pretreatment unit of two scales of N × 1, for the charge signal obtained after integral to be converted to voltage letter
Number, the input signal that this voltage signal is handled as subsequent column grade ADC, parity rows respectively use the ADC of a scale of N × 1 to locate in advance
Manage unit.This circuit uses low speed pulse and high power supply.
3. the column ADC processing unit of two scales of N × 1 is completed using the output signal of ADC pretreatment unit as input
The work for converting digital signal for analog signal and exporting by column, parity rows respectively use the ADC of the scale of N × 1 to pre-process
Unit.This circuit uses high-speed pulse and low power supply.
4. low-speed clock controls signal generating circuit, input is low speed master clock MLclk and integral control signal INT,
And the two signals are based on, a series of necessary internal clock control signal of circuits work is generated, these signals include: capable selection
Signal, column grade ADC work enable signal start_ADC etc..
5. high-frequency clock controls signal generating circuit, input is the enabled letter of high speed master clock MHclk and column grade ADC work
Number start_ADC generates a series of necessary internal signal of control column grade adc circuits work.
The reading method of reading circuit of the invention includes:
For circuit using a frame as the duplicate duty cycle, a frame includes: the integral of N × M pixel, first in cell array
It goes to the successively gating of M row.
The period timing of one frame is as shown in Figure 2: first integrating to N × M pixel unit in cell array；Integral terminates
Afterwards, the row selection signal RSW of the 1st row to M row is successively effective, here due to odd row idol row concurrent working, so RSW signal is total
There are M/2.
The timing of every a line is as shown in Figure 2: after the row selection signal RSW of every a line is effective, the signal in the row pixel turns
It moves on in ADC pretreatment unit, then start_ADC signal is effective, and column grade ADC starts to work, and completes signal analog/digital conversion simultaneously
And the digital signal being converted to is sequentially output from the 1st column to m column；After all signal Serial outputs of the row, column grade ADC into
Row resets.Two groups of ADC concurrent workings.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Subject to enclosing.
Claims (5)
1. a kind of digitalized snapshot-type infrared focal plane read-out circuit of column characterized by comprising
Pixel array processing unit completes conversion, integral and the reset processing of photosignal, and will answer for receiving optical signal
Position treated signal is sent respectively to odd row ADC pretreatment unit and even row ADC pretreatment unit according to odd row, even row；
The surprise row ADC pretreatment unit and the even row ADC pretreatment unit, for sending out the pixel array processing unit
The signal sent is handled, and obtained charge signal is converted to voltage signal, and the voltage signal is sent respectively to
Odd row ADC processing unit and even row ADC processing unit；
The surprise row ADC processing unit and the even row ADC processing unit, for being turned analog signal according to the voltage signal
It turns to digital signal and is exported by column；
The array scale of the pixel array processing unit is N × M, and the surprise row ADC pretreatment unit and the even row ADC are pre-
The array scale of processing unit is N × 1, and the array scale of the surprise row ADC processing unit and the even row ADC processing unit is
N×1；
The pixel array processing unit, the odd row ADC pretreatment unit and the even row ADC pretreatment unit use low speed
The low speed pulse that clock control signal generation circuit generates is controlled；
The surprise row ADC processing unit and the even row ADC processing unit are generated using high-frequency clock control signal generating circuit
High-speed pulse controlled, and be powered by low power supply；
The pixel array processing unit, the odd row ADC pretreatment unit and the even row ADC pretreatment unit pass through high electricity
Source is powered.
2. circuit according to claim 1, which is characterized in that
The input of low-speed clock control signal generating circuit is low speed pulse and integral control signal INT, and based on this two
The internal clock control signal of a signal generating circuit work, the internal clock control signal includes: row selection signal, column grade
ADC work enable signal start_ADC, wherein row selection signal controls the signal of the pixel array processing unit according to surprise
Row, even row are sent respectively to odd row ADC pretreatment unit and even row ADC pretreatment unit, column grade ADC work enable signal
The start_ADC control odd row ADC processing unit and the even row ADC processing unit carry out analog-to-digital conversion；
The input of the high-frequency clock control signal generating circuit is high-speed pulse and column grade ADC work enable signal start_
ADC generates the internal signal of the control odd row ADC processing unit and the even row ADC processing unit work.
3. circuit according to claim 1 or 2, which is characterized in that
The high-speed pulse is 20-40MHz, and the low speed pulse is 1-5MHz.
4. circuit according to claim 1, which is characterized in that
The voltage of the high power supply is 3-5V.
5. circuit according to claim 4, which is characterized in that
The voltage of the low power supply is 1.8-3V.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511019009.8A CN105657298B (en) | 2015-12-29 | 2015-12-29 | A kind of digitalized snapshot-type infrared focal plane read-out circuit of column |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511019009.8A CN105657298B (en) | 2015-12-29 | 2015-12-29 | A kind of digitalized snapshot-type infrared focal plane read-out circuit of column |
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| CN105657298A CN105657298A (en) | 2016-06-08 |
| CN105657298B true CN105657298B (en) | 2019-02-05 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103402063A (en) * | 2013-08-16 | 2013-11-20 | 上海集成电路研发中心有限公司 | CMOS imaging sensor and image data transmission method thereof |
| CN103795414A (en) * | 2014-01-27 | 2014-05-14 | 无锡艾立德智能科技有限公司 | Infrared focal plane array reading circuit with even-numbered line and odd-numbered line multiplex function |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8969774B2 (en) * | 2012-12-27 | 2015-03-03 | Omnivision Technologies, Inc. | Conversion circuitry for reducing pixel array readout time |
| US9410850B2 (en) * | 2013-09-20 | 2016-08-09 | Vlad Joseph Novotny | Infrared imager readout electronics |
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2015
- 2015-12-29 CN CN201511019009.8A patent/CN105657298B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103402063A (en) * | 2013-08-16 | 2013-11-20 | 上海集成电路研发中心有限公司 | CMOS imaging sensor and image data transmission method thereof |
| CN103795414A (en) * | 2014-01-27 | 2014-05-14 | 无锡艾立德智能科技有限公司 | Infrared focal plane array reading circuit with even-numbered line and odd-numbered line multiplex function |
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| Publication number | Publication date |
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| CN105657298A (en) | 2016-06-08 |
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