CN105656478A - Method for achieving low jitter and wide locking range of optimized phase-locked loop structure - Google Patents
Method for achieving low jitter and wide locking range of optimized phase-locked loop structure Download PDFInfo
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- CN105656478A CN105656478A CN201410642214.9A CN201410642214A CN105656478A CN 105656478 A CN105656478 A CN 105656478A CN 201410642214 A CN201410642214 A CN 201410642214A CN 105656478 A CN105656478 A CN 105656478A
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Abstract
The invention discloses a method for achieving low jitter and a wide locking range of an optimized phase-locked loop structure. The method comprises the following steps of firstly starting a phase-lock loop A with a high gain voltage-controlled oscillator to work, and taking the advantage that the high gain voltage-controlled oscillator is wide in coverage frequency range to lock a frequency point; and after the frequency point is locked, switching the phase-lock loop A with the high gain voltage-controlled oscillator to a phase-lock loop B with a low gain voltage-controlled oscillator, and taking the advantage that the low gain voltage-controlled oscillator is low in gain to ensure the low jitter. According to the method, the phase-lock loop A with the high gain voltage-controlled oscillator is used for locking the frequency point, and then switched to the phase-lock loop B with the low gain voltage-controlled oscillator for ensuring the low jitter, thus the purpose that the phase-locked loop is low in jitter and wide in locking range is achieved.
Description
Technical field
The present invention relates to a kind of method optimizing the wide lock-in range low jitter of phase-locked loop structures realization.
Background technology
Conventional phase locked loops road only one of which loop, including five modules, respectively: phase frequency detector, electric charge pump, low pass filter, voltage controlled oscillator and frequency divider, mainly realizes the frequency multiplication to input reference frequency signal.
Traditional phaselocked loop signal processing is as shown in Figure 1, phase frequency detector produces the pulse-modulated signal of different in width according to two differences inputting square-wave signal, the pulse-modulated signal output current impulse according to input of the electric charge pump, current impulse is integrated and filters by low pass filter, complete the electric current transformation to voltage, the voltage controlled oscillator frequency signal according to above-mentioned voltage output correspondence, this frequency signal is divided by frequency divider. Frequency-the voltage transfer curve of voltage controlled oscillator is as shown in Figure 2, because the gain of voltage controlled oscillator is the slope at certain frequency of locking of the curve shown in Fig. 2, so when effectively input controls corresponding necessary covering frequence range delta f within the scope of voltage �� V, this �� f is more big, then this slope of a curve is also more big. Considering technique, supply voltage, the deviation of temperature, in order to effectively cover �� f, it is necessary to strengthening frequency coverage, the slope of curve at this moment is just very big, usually reaches the order of magnitude of GHZ/V. Above way has been to ensure that the covering to wide frequency ranges, but the gain of high voltage controlled oscillator, and the obvious drawback brought is exactly that input is controlled the sensitivity of noise on voltage by voltage controlled oscillator, is degrading jitter performance. From the angle improving jitter performance, in fact it is desirable to the gain of a low voltage controlled oscillator. From the above, it can be seen that traditional phase-locked loop structures exists the contradiction between wide lock-in range and low voltage controlled oscillator gain.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, thering is provided a kind of and optimize the method that phase-locked loop structures realizes wide lock-in range low jitter, the method also achieves while realizing wideband lock function and utilizes low voltage controlled oscillator gain to reach the purpose of low jitter.
It is an object of the invention to be achieved through the following technical solutions: a kind of optimize the method that phase-locked loop structures realizes wide lock-in range low jitter, it comprises the following steps:
(1) first enable the phase-locked loop A with high-gain voltage controlled oscillator to work, utilize the advantage of the covering frequence wide ranges of high-gain voltage controlled oscillator to carry out locked frequency point;
(2) after locked frequency point, switch with the phase-locked loop A to the phase-locked loop B with low-gain voltage-controlled oscillator of high-gain voltage controlled oscillator, utilize the low advantage of the gain of low-gain voltage-controlled oscillator to ensure low jitter.
Described phaselocked loop includes phase-locked loop A, phase-locked loop B and logic judgment module, input reference clock signal is connected with the input of phase-locked loop A, phase-locked loop B and logic judgment module respectively, and logic judgment module is connected with phase-locked loop A and phase-locked loop B respectively.
When described logic judgment module judges phase-locked loop A locked frequency point, close phase-locked loop A, be simultaneously switching to phase-locked loop B.
The invention has the beneficial effects as follows:
Utilize the phase-locked loop A with high-gain voltage controlled oscillator to carry out locked frequency point, then switch to the phase-locked loop B with low-gain voltage-controlled oscillator to ensure low jitter, make phaselocked loop realize the purpose of wide lock-in range low jitter.
Accompanying drawing explanation
Fig. 1 is traditional phaselocked loop Organization Chart;
Fig. 2 is the frequency-voltage transfer curve figure of voltage controlled oscillator;
Fig. 3 is the flow chart of the present invention;
Fig. 4 is the schematic block circuit diagram of the present invention;
Fig. 5 is the frequency-voltage transfer curve synoptic diagram of the frequency-voltage transfer curve of high-gain voltage controlled oscillator and low-gain voltage-controlled oscillator;
Fig. 6 is the Organization Chart of one embodiment of the present of invention.
Detailed description of the invention
Below in conjunction with accompanying drawing, technical scheme is described in further detail, but protection scope of the present invention is not limited to the following stated.
Optimizing, as it is shown on figure 3, a kind of, the method that phase-locked loop structures realizes wide lock-in range low jitter, it comprises the following steps:
(1) first enable the phase-locked loop A with high-gain voltage controlled oscillator to work, utilize the advantage of the covering frequence wide ranges of high-gain voltage controlled oscillator to carry out locked frequency point;
(2) after locked frequency point, switch with the phase-locked loop A to the phase-locked loop B with low-gain voltage-controlled oscillator of high-gain voltage controlled oscillator, utilize the low advantage of the gain of low-gain voltage-controlled oscillator to ensure low jitter.
As shown in Figure 4, a kind of method optimizing the wide lock-in range low jitter of phase-locked loop structures realization, phase-locked loop circuit includes phase-locked loop A, phase-locked loop B and logic judgment module, input reference clock signal is connected with the input of phase-locked loop A, phase-locked loop B and logic judgment module respectively, and logic judgment module is connected with phase-locked loop A and phase-locked loop B respectively.
Fig. 5 is the present invention to demonstrate wide lock-in range and the frequency-voltage transfer curve synoptic diagram of the frequency-voltage transfer curve of high voltage controlled oscillator that low voltage controlled oscillator gain effect provides and low voltage controlled oscillator, as shown in Figure 5, such as purpose is just locked out this frequency of f1 and has the performance of low jitter, that has just started phase-locked loop A work, frequency-voltage transfer the curve of corresponding voltage controlled oscillator is this curve shown in A, it can be seen that this slope of a curve is big, it is possible to complete locking in very wide frequency range. when phase-locked loop A locks f1 frequency, logic judgment module can be switched to phase-locked loop B loop, frequency-voltage transfer the curve of corresponding voltage controlled oscillator is this curve shown in B, it can be seen that this slope of a curve is little, the locking of very wide frequency range can not be completed, but phase-locked loop A has been completed this task of locking of very wide frequency range, it is not required to phase-locked loop B and also there is this function, the function of phase-locked loop B is on the basis of phase-locked loop A, after phase-locked loop A catches frequency, it is switched to phase-locked loop B, it is just passable that the frequency of the voltage controlled oscillator that phase-locked loop B is corresponding-voltage transfer curve only need to deal with voltage temperature fluctuation corresponding during this frequency, so the frequency range needed is not wide, so now the gain of voltage controlled oscillator is low, just it is beneficial to the raising of jitter performance, because the low gain of voltage controlled oscillator is the key point improving jitter performance.
As shown in Figure 6, as one embodiment of the present of invention, it includes two voltage controlled oscillator gain height different phase-locked loop A and phase-locked loop B, and a logic judgment module, phase-locked loop A is made up of phase frequency detector A, electric charge pump A, low pass filter A, voltage controlled oscillator and frequency divider, phase-locked loop B is made up of phase frequency detector B, electric charge pump B, low pass filter B, voltage controlled oscillator and frequency divider, and phase-locked loop A and phase-locked loop B has shared voltage controlled oscillator and frequency divider, input reference clock signal respectively with logic judgment module, phase frequency detector A and phase frequency detector B connects, the output of phase frequency detector A and phase frequency detector B is connected with electric charge pump A and electric charge pump B respectively, the output of electric charge pump A and electric charge pump B is connected with low pass filter A and low pass filter B respectively, the output of low pass filter A and low pass filter B is connected with two inputs of voltage controlled oscillator respectively, the output of voltage controlled oscillator is connected with the input of frequency divider, the output of frequency divider respectively with logic judgment module, phase frequency detector A and phase frequency detector B connects, the output of logic judgment module respectively with phase frequency detector A, phase frequency detector B, electric charge pump A and electric charge pump B connects.
Described phase frequency detector A and phase frequency detector B, produces the pulse-modulated signal of different in width respectively according to two differences inputting square-wave signal.
Described electric charge pump A and electric charge pump B, respectively the pulse-modulated signal output current impulse according to input.
Described low pass filter A and low pass filter B, is integrated current impulse respectively and filters, and completes the electric current transformation to voltage, output voltage signal.
Described voltage controlled oscillator, the signal according to different input voltage output different frequencies.
Described frequency divider, divides the frequency of input signal.
Described logic judgment module is used for judging whether high-gain phase-locked loop locks or approach locking, in this way, then turns off this high-gain loop and is output as high resistant by electric charge pump, in order to preserves the electric charge on low pass filter, is simultaneously switching to the phase-locked loop of low gain.
The gain of voltage controlled oscillator corresponding in described phase-locked loop A is high-gain, and the gain of voltage controlled oscillator corresponding in phase-locked loop B is low gain; It is phase-locked loop A work when just starting, when logic judgment module judges loop-locking or approach locking according to the two paths of signals of input, it is switched to phase-locked loop B work, electric charge pump A output is arranged to high-impedance state simultaneously, so that the electric charge preserved on low pass filter A, phase-locked loop B is assisted to complete last locking.
Claims (3)
1. one kind optimizes the method that phase-locked loop structures realizes wide lock-in range low jitter, it is characterised in that: it comprises the following steps:
(1) first enable the phase-locked loop A with high-gain voltage controlled oscillator to work, utilize the advantage of the covering frequence wide ranges of high-gain voltage controlled oscillator to carry out locked frequency point;
(2) after locked frequency point, switch with the phase-locked loop A to the phase-locked loop B with low-gain voltage-controlled oscillator of high-gain voltage controlled oscillator, utilize the low advantage of the gain of low-gain voltage-controlled oscillator to ensure low jitter.
2. a kind of method optimizing the wide lock-in range low jitter of phase-locked loop structures realization according to claim 1, it is characterized in that: described phaselocked loop includes phase-locked loop A, phase-locked loop B and logic judgment module, input reference clock signal is connected with the input of phase-locked loop A, phase-locked loop B and logic judgment module respectively, and logic judgment module is connected with phase-locked loop A and phase-locked loop B respectively.
3. a kind of method optimizing the wide lock-in range low jitter of phase-locked loop structures realization according to claim 2, it is characterised in that: when described logic judgment module judges phase-locked loop A locked frequency point, close phase-locked loop A, be simultaneously switching to phase-locked loop B.
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| CN201410642214.9A CN105656478A (en) | 2014-11-14 | 2014-11-14 | Method for achieving low jitter and wide locking range of optimized phase-locked loop structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1595806A (en) * | 2003-09-05 | 2005-03-16 | 阿尔特拉公司 | Dual-gain loop circuitry for programmable logic device |
| US20090174446A1 (en) * | 2008-01-07 | 2009-07-09 | Qualcomm Incorporated | Systems and methods for calibrating the loop bandwidth of a phase-locked loop (pll) |
| CN101515913A (en) * | 2009-03-19 | 2009-08-26 | 北京理工大学 | Fixed loop control method based on additions and shifts |
| CN101588176A (en) * | 2009-06-18 | 2009-11-25 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer with loop gain calibration function |
-
2014
- 2014-11-14 CN CN201410642214.9A patent/CN105656478A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1595806A (en) * | 2003-09-05 | 2005-03-16 | 阿尔特拉公司 | Dual-gain loop circuitry for programmable logic device |
| US20090174446A1 (en) * | 2008-01-07 | 2009-07-09 | Qualcomm Incorporated | Systems and methods for calibrating the loop bandwidth of a phase-locked loop (pll) |
| CN101515913A (en) * | 2009-03-19 | 2009-08-26 | 北京理工大学 | Fixed loop control method based on additions and shifts |
| CN101588176A (en) * | 2009-06-18 | 2009-11-25 | 广州润芯信息技术有限公司 | Phase-locked loop frequency synthesizer with loop gain calibration function |
Non-Patent Citations (1)
| Title |
|---|
| 黄水龙 等: "快速建立时间的自适应锁相环", 《电子与信息学报》 * |
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Application publication date: 20160608 |