CN105656444A - Device for improving area utilization ratio of video graphics array - Google Patents
Device for improving area utilization ratio of video graphics array Download PDFInfo
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- CN105656444A CN105656444A CN201510876348.1A CN201510876348A CN105656444A CN 105656444 A CN105656444 A CN 105656444A CN 201510876348 A CN201510876348 A CN 201510876348A CN 105656444 A CN105656444 A CN 105656444A
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- semicondutor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
Abstract
The invention discloses a device for improving area utilization ratio of a video graphics array. The device comprises four levels of NMOSs; the control end of a first level NMOS is connected with a first input voltage; the input end is connected with a power supply voltage; the first level NMOS is taken as a load resistor; the control end of a second level NMOS is respectively connected with a positive voltage and a negative voltage; the input end is connected with the output end of the first level NMOS; the second level NMOS is used for outputting differential signals; the control end of a third level NMOS is connected with a control voltage; the input end is connected with the output end of the second level NMOS; the third level NMOS is used for outputting control signals; the control end of a fourth level NMOS is connected with a second input voltage; the input end is connected with the output end of the third level NMOS; and the output end is grounded. Through the device provided by the invention, the area utilization ratio of a VGA (video graphics array) circuit can be improved.
Description
Technical field
The present invention relates to circuit technical field, particularly relate to the device of a kind of raising based on Video Graphics Array (VGA, the VideoGraphicsArray) area utilization of Gilbert cell circuit.
Background technology
Gilbert (Gilbert) unit circuit controls the gain size of variable gain stages with control voltage.
As shown in Figure 1, input signal inputs Gilbert cell circuit respectively from the grid of MOS pipe M5 and M6, and the source electrode of M5 and M6 is connected to constant current source ISSOn, the drain electrode of M5 is received on the source electrode of M1 and M2, and the drain electrode of M6 is received on the source electrode of M3 and M4, and the drain electrode of M1, M2, M3 and M4 is connected respectively to two resistance RDOn, two resistance RDReceive power supply VDDOn.
In this Gilbert cell circuit, comprise two differential right, with contrary gain, input signal is amplified, wherein by making curent change direction contrary, just can make the gain monotone variation of variable gain amplifier.
But, although prior art reaches the object of gain control, introduce a large amount of resistance, and resistance takes up space very big in the layout design, although resistance can be folded, but the problem of the area utilization difference of VGA can be caused.
Owing to VGA has a wide range of applications, such as, in RF (radio frequency) receives, it is therefore desirable to VGA is optimized design.
Summary of the invention
In order to solve the problems of the technologies described above, a kind of device improving Video Graphics Array area utilization, it is possible to significantly improve the Video Graphics Array area utilization based on Gilbert cell circuit, the simultaneously immunity from interference of also significantly promotion signal transmission.
The present invention provides a kind of device improving Video Graphics Array area utilization, the circuit structure of described device is made up of N-type Metal-oxide-semicondutor unit, and at least comprise level Four N-type Metal-oxide-semicondutor unit, wherein, the control end of first step N-type Metal-oxide-semicondutor unit and the first input voltage connect, input terminus and voltage of supply connect, for as pull-up resistor; The control end of second stage N-type Metal-oxide-semicondutor unit connects difference voltage, and the output terminal of input terminus and described first step N-type Metal-oxide-semicondutor unit connects, for output difference sub-signal; The control end of third stage N-type Metal-oxide-semicondutor unit and control voltage connect, and the output terminal of input terminus and described second stage N-type Metal-oxide-semicondutor unit connects, for exporting control signal;The control end of fourth stage N-type Metal-oxide-semicondutor unit and the 2nd input voltage connect, the output terminal of input terminus and described third stage N-type Metal-oxide-semicondutor unit connects, output head grounding, for carrying out current control by the 2nd input voltage to difference signal.
Further, described first step N-type Metal-oxide-semicondutor unit comprises the first N-type Metal-oxide-semicondutor subelement and the 2nd N-type Metal-oxide-semicondutor subelement; The drain electrode of described first N-type Metal-oxide-semicondutor subelement and the 2nd N-type Metal-oxide-semicondutor subelement all connects with voltage of supply, and grid all with the first input voltage connects.
Further, conducting resistance after described first N-type Metal-oxide-semicondutor subelement and the 2nd N-type Metal-oxide-semicondutor subelement conducting is as pull-up resistor.
Further, described second stage N-type Metal-oxide-semicondutor unit comprises the 3rd N-type Metal-oxide-semicondutor subelement and the 4th N-type Metal-oxide-semicondutor subelement; The drain electrode of described 3rd N-type Metal-oxide-semicondutor subelement connects with the source electrode of the first N-type Metal-oxide-semicondutor subelement; The drain electrode of the 4th N-type Metal-oxide-semicondutor subelement connects with the source electrode of the 2nd N-type Metal-oxide-semicondutor subelement, and the grid of described 3rd N-type Metal-oxide-semicondutor subelement and described 4th N-type Metal-oxide-semicondutor subelement connects described difference.
Further, described 3rd N-type Metal-oxide-semicondutor subelement receives the transmission signal of the first N-type Metal-oxide-semicondutor subelement, the 4th N-type Metal-oxide-semicondutor subelement receive the 2nd N-type Metal-oxide-semicondutor subelement transmission signal; The transmission signal of input is carried out differential transfer and forms difference signal by the 3rd N-type Metal-oxide-semicondutor subelement and the 4th N-type Metal-oxide-semicondutor subelement.
Further, described third stage N-type Metal-oxide-semicondutor unit comprises the 5th N-type Metal-oxide-semicondutor subelement and the 6th N-type Metal-oxide-semicondutor subelement; The drain electrode of described 5th N-type Metal-oxide-semicondutor subelement connects with the source electrode of the 3rd N-type Metal-oxide-semicondutor subelement, and grid and control voltage connect; The drain electrode of the 6th N-type Metal-oxide-semicondutor subelement and the 4th N-type Metal-oxide-semicondutor subelement connect, and grid and control voltage connect.
Further, described 5th N-type Metal-oxide-semicondutor subelement and the 6th N-type Metal-oxide-semicondutor subelement receive third stage N-type Metal-oxide-semicondutor unit and the difference signal of fourth stage N-type Metal-oxide-semicondutor unit transmission, and difference signal is carried out voltage control.
Further, described fourth stage N-type Metal-oxide-semicondutor unit, comprises the 7th N-type Metal-oxide-semicondutor subelement; Drain electrode the respectively with five N-type Metal-oxide-semicondutor subelement of described 7th N-type Metal-oxide-semicondutor subelement and the source electrode of the 6th N-type Metal-oxide-semicondutor subelement connect, and grid and the 2nd input voltage connect, source ground.
Further, by changing the working current that the 7th N-type Metal-oxide-semicondutor unit described in the 2nd input voltage regulation provides.
Further, the circuit of described device also comprises: the isolation ring isolating described level Four N-type Metal-oxide-semicondutor unit.
Technical solution of the present invention by adopting the design of full NMOS tube in Video Graphics Array, can make to put NMOS tube is tightlier urged, the area utilization of chip is greatly improved, the volume of chip can be reduced like this, thus reduce chip and taken up space on PCB, meanwhile, the integrated level of chip have also been obtained very big lifting, has saved manufacturing cost; In addition, from the angle of manufacturing process, because the manufacturing process of resistance and MOS pipe is different, present invention employs the design of full NMOS tube, make manufacturing process become simple; In addition, from the interference between signal, adopt the design of strip resistance, it is necessary to resistance and the NMOS tube isolation ring that respectively adds, for isolating different signal, and have employed full NMOS tube, only need to providing a whole isolation ring, reduce process complexity, immunity from interference is enhanced, also it is easy to reach coupling simultaneously, makes ghost effect minimum. In typical Gilbert cell circuit, also can adopt this method equally, replace resistance with NMOS, by arranging the object that W/L reaches identical with resistance, make the area utilization of the Layout of Gilbert cell circuit reach very big lifting.
Accompanying drawing explanation
In order to the technical scheme being illustrated more clearly in the embodiment of the present application, below the accompanying drawing used required in embodiment being described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the application, for those of ordinary skill in the art, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings, wherein:
Fig. 1 is the schematic diagram of the Gilbert cell circuit that prior art provides;
Fig. 2 is the schematic diagram of the device of raising Video Graphics Array area utilization provided by the invention;
Fig. 3 is the schematic diagram of the device of raising Video Graphics Array area utilization provided by the invention.
Embodiment
Technical problem, technical scheme and useful effect in order to make the application solve clearly are understood, below in conjunction with drawings and Examples, the application are further elaborated. It is to be understood that specific embodiment described herein is only in order to explain the application, and it is not used in restriction the application.
NMOS is N-channel enhancement type MOS (Metal-oxide-semicondutor) pipe. NMOS has less geometrical dimension, is suitable for manufacturing large-scale integrated circuit. In addition, the structure of NMOS unicircuit is simple, is easy to use CAD (computer aided design (CAD)) to design, and does not use the resistance being difficult to manufacture in nmos circuit.
Fig. 2 is the circuit diagram of a kind of device improving Video Graphics Array area utilization provided by the invention. As shown in Figure 2, this device improving Video Graphics Array area utilization comprises level Four N-type Metal-oxide-semicondutor unit, and the N-type Metal-oxide-semicondutor unit of every one-level is all be made up of NMOS, wherein,
The control end of first step N-type Metal-oxide-semicondutor unit and the first input voltage connect, and input terminus and voltage of supply connect, and output terminal is connected with second stage N-type Metal-oxide-semicondutor unit, for as pull-up resistor;
The control end of second stage N-type Metal-oxide-semicondutor unit connects a difference voltage, the output terminal of input terminus and described first step N-type Metal-oxide-semicondutor unit connects, output terminal is connected to third stage N-type Metal-oxide-semicondutor unit, for passing through its output terminal to third stage N-type Metal-oxide-semicondutor unit output difference sub-signal;
The control end of third stage N-type Metal-oxide-semicondutor unit and control voltage connect, the output terminal of input terminus and described second stage N-type Metal-oxide-semicondutor unit connects, output terminal is connected to fourth stage N-type Metal-oxide-semicondutor unit, for receiving the difference signal that second stage N-type Metal-oxide-semicondutor unit transmission comes, and the control according to control voltage, export control signal to fourth stage N-type Metal-oxide-semicondutor unit;
The control end of fourth stage N-type Metal-oxide-semicondutor unit and the 2nd input voltage connect, the output terminal of input terminus and described third stage N-type Metal-oxide-semicondutor unit connects, output head grounding, for receiving the control signal that the transmission of third stage N-type Metal-oxide-semicondutor unit comes, and realized the gain control of whole circuit by the 2nd input voltage.
The N-type Metal-oxide-semicondutor unit of the present invention is all be made up of NMOS, also that is to say, select the NMOS of setting W/L parameter (channel width/channel length) to replace pull-up resistor in the present invention, reach the gain control similar with the resistance load of use in prior art. Because NMOS has less geometrical dimension and relatively simple for structure, the design of full NMOS tube, it is possible to make NMOS tube put and tightlier urge, thus the area utilization making VGA chip is greatly improved.
Specifically, referring to Fig. 3, it is the circuit diagram of a kind of device improving Video Graphics Array area utilization provided by the invention.
First step N-type Metal-oxide-semicondutor unit, comprises a NMOS subelement 21 and the 2nd NMOS subelement 22; Second stage N-type Metal-oxide-semicondutor unit, comprises the 3rd NMOS subelement 23 and the 4th NMOS subelement 24; Third stage N-type Metal-oxide-semicondutor unit, comprises the 5th NMOS subelement 25 and the 6th NMOS subelement 26; Fourth stage N-type Metal-oxide-semicondutor unit, comprises the 7th NMOS subelement 37.
One NMOS subelement 21 and the 2nd NMOS subelement 22 are for as pull-up resistor, wherein the drain electrode of a NMOS subelement 21 and the 2nd NMOS subelement 22 connects with power source voltage Vcc respectively, and grid respectively with the first input voltage V1 connects; Because having conducting resistance to exist after NMOS conducting, it is possible to as pull-up resistor.
3rd NMOS subelement 23 and the 4th NMOS subelement 24 are for receiving difference voltage, and to the 5th NMOS subelement 25 and the 6th NMOS subelement 26 output difference sub-signal, wherein the drain electrode of the 3rd NMOS subelement 23 connects with the source electrode of a NMOS subelement 21, and the positive voltage Vin+ of grid and difference voltage connects; The drain electrode of the 4th NMOS subelement 24 connects with the source electrode of the 2nd NMOS subelement 22, and the negative voltage Vin-of grid and difference voltage connects.
The drain electrode of the 5th NMOS subelement 25 and the 6th NMOS subelement 26 connects the 3rd NMOS subelement 23 and the source electrode of the 4th NMOS subelement 24 respectively, for receiving the 3rd NMOS subelement 23 and the difference signal of the 4th NMOS subelement 24 output. The grid of the 5th NMOS subelement 25 and the 6th NMOS subelement 26 is all connected to control voltage Voon. 5th NMOS subelement 25 and the 6th NMOS subelement 26 source electrode be connected to the 7th NMOS subelement 27, for providing control signal to the 7th NMOS subelement 27.
7th NMOS subelement 27 is for providing working current, and drain electrode the respectively with five NMOS subelement 25 of the 7th NMOS subelement 27 and the source electrode of the 6th NMOS subelement 26 connect, grid and the 2nd input voltage V0 of the 7th NMOS subelement 27 connect.7th NMOS subelement 27 utilizes the 5th NMOS subelement 25 to converge into control signal with the source voltage of the 6th NMOS subelement 26, and is controlled by the 2nd input voltage V0, and forms working current at its source electrode, and its source ground.
The circuit of the device of the raising Video Graphics Array area utilization shown in Fig. 3, its principle that can reach high gain control is as follows:
(4) formula is substituted in (3) formula and obtains:
Again because of id=iss/2(6)
(6) formula is substituted in (5) formula and can obtain:
Wherein, Rd is a NMOS subelement 21 and the pull-up resistor of the 2nd NMOS subelement 22, and iss is the working current of the 7th NMOS subelement 27 source electrode, and �� n and Cox is components and parts constant, and gm is circuit gain.
Knowing by (7) formula, changing the breadth-length ratio of NMOS (N-type Metal-oxide-semicondutor), iss and Rd, can change gain.
In addition, prior art adopts the design of strip resistance, it is necessary to resistance and the NMOS tube isolation ring that respectively adds, for isolating different signal.
Circuit diagram as shown in Figures 2 and 3, have employed full NMOS tube, therefore only need to provide a whole isolation ring, thus reduce process complexity, and immunity from interference is enhanced, and is also easy to reach coupling simultaneously, makes ghost effect minimum.
The VGA of prior art and the design of Gilbert cell, owing to have employed pull-up resistor, make the area utilization of domain very little. The present invention adopts NMOS replace pull-up resistor, greatly improve the area utilization of layout, improve the design of mask, saved the manufacturing cost of chip, also make the ghost effect of domain reduce simultaneously, improve the performance of domain.
Last it is noted that above embodiment is only in order to illustrate the technical scheme of the application, it is not intended to limit; Although with reference to previous embodiment to present application has been detailed description, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein part technology feature is carried out equivalent replacement; And these amendments or replacement, do not make the scope of the essence disengaging each embodiment technical scheme of the application of appropriate technical solution.
Claims (10)
1. one kind is improved the device of Video Graphics Array area utilization, it is characterised in that, the circuit of described device at least comprises level Four N-type Metal-oxide-semicondutor unit, wherein,
The control end of first step N-type Metal-oxide-semicondutor unit and the first input voltage connect, and input terminus and voltage of supply connect, for as pull-up resistor;
The control end of second stage N-type Metal-oxide-semicondutor unit connects a difference voltage, and the output terminal of input terminus and described first step N-type Metal-oxide-semicondutor unit connects, for output difference sub-signal;
The control end of third stage N-type Metal-oxide-semicondutor unit and control voltage connect, and the output terminal of input terminus and described second stage N-type Metal-oxide-semicondutor unit connects, for exporting control signal;
The control end of fourth stage N-type Metal-oxide-semicondutor unit and the 2nd input voltage connect, and the output terminal of input terminus and described third stage N-type Metal-oxide-semicondutor unit connects, output head grounding.
2. the device improving Video Graphics Array area utilization as claimed in claim 1, it is characterized in that, described first step N-type Metal-oxide-semicondutor unit comprises the first N-type Metal-oxide-semicondutor subelement and the 2nd N-type Metal-oxide-semicondutor subelement;
The drain electrode of described first N-type Metal-oxide-semicondutor subelement and the 2nd N-type Metal-oxide-semicondutor subelement all connects with voltage of supply, and grid all with the first input voltage connects.
3. the device improving Video Graphics Array area utilization as claimed in claim 2, it is characterized in that, the conducting resistance after described first N-type Metal-oxide-semicondutor subelement and the 2nd N-type Metal-oxide-semicondutor subelement conducting is as pull-up resistor.
4. the device improving Video Graphics Array area utilization as claimed in claim 3, it is characterized in that, described second stage N-type Metal-oxide-semicondutor unit comprises the 3rd N-type Metal-oxide-semicondutor subelement and the 4th N-type Metal-oxide-semicondutor subelement;
The drain electrode of described 3rd N-type Metal-oxide-semicondutor subelement connects with the source electrode of the first N-type Metal-oxide-semicondutor subelement, the drain electrode of the 4th N-type Metal-oxide-semicondutor subelement connects with the source electrode of the 2nd N-type Metal-oxide-semicondutor subelement, and the grid of described 3rd N-type Metal-oxide-semicondutor subelement and described 4th N-type Metal-oxide-semicondutor subelement connects described difference.
5. the device improving Video Graphics Array area utilization as claimed in claim 4, it is characterized in that, described 3rd N-type Metal-oxide-semicondutor subelement receives the transmission signal of the first N-type Metal-oxide-semicondutor subelement, the 4th N-type Metal-oxide-semicondutor subelement receive the 2nd N-type Metal-oxide-semicondutor subelement transmission signal;
The transmission signal of input is carried out differential transfer and forms difference signal by the 3rd N-type Metal-oxide-semicondutor subelement and the 4th N-type Metal-oxide-semicondutor subelement.
6. the device improving Video Graphics Array area utilization as claimed in claim 5, it is characterized in that, described third stage N-type Metal-oxide-semicondutor unit comprises the 5th N-type Metal-oxide-semicondutor subelement and the 6th N-type Metal-oxide-semicondutor subelement;
The drain electrode of described 5th N-type Metal-oxide-semicondutor subelement connects with the source electrode of the 3rd N-type Metal-oxide-semicondutor subelement, and grid and control voltage connect; The drain electrode of the 6th N-type Metal-oxide-semicondutor subelement and the 4th N-type Metal-oxide-semicondutor subelement connect, and grid and control voltage connect.
7. the device improving Video Graphics Array area utilization as claimed in claim 6, it is characterized in that, described 5th N-type Metal-oxide-semicondutor subelement and the 6th N-type Metal-oxide-semicondutor subelement receive third stage N-type Metal-oxide-semicondutor unit and the difference signal of fourth stage N-type Metal-oxide-semicondutor unit transmission, and difference signal is carried out voltage control.
8. the device improving Video Graphics Array area utilization as claimed in claim 7, it is characterised in that, described fourth stage N-type Metal-oxide-semicondutor unit, comprises the 7th N-type Metal-oxide-semicondutor subelement;
Drain electrode the respectively with five N-type Metal-oxide-semicondutor subelement of described 7th N-type Metal-oxide-semicondutor subelement and the source electrode of the 6th N-type Metal-oxide-semicondutor subelement connect, and grid and the 2nd input voltage connect, source ground.
9. the device improving Video Graphics Array area utilization as claimed in claim 8, it is characterised in that, by changing the working current that the 7th N-type Metal-oxide-semicondutor unit described in the 2nd input voltage regulation provides.
10. the device of raising Video Graphics Array area utilization as according to any one of claim 1��9, it is characterised in that, the circuit of described device also comprises: the isolation ring isolating described level Four N-type Metal-oxide-semicondutor unit.
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| CN1830139A (en) * | 2003-07-31 | 2006-09-06 | 斯盖沃克斯解决方案有限公司 | Variable gain amplifier system |
| US20090302946A1 (en) * | 2006-06-30 | 2009-12-10 | Fci Inc. | VARIABLE GAIN AMPLIFIER HAVING LINEAR-IN-dB GAIN CHARACTERISTIC |
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