CN105653828A - Friendliness checking method aimed at photoetching technology for layout design data revision - Google Patents
Friendliness checking method aimed at photoetching technology for layout design data revision Download PDFInfo
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- CN105653828A CN105653828A CN201610173339.0A CN201610173339A CN105653828A CN 105653828 A CN105653828 A CN 105653828A CN 201610173339 A CN201610173339 A CN 201610173339A CN 105653828 A CN105653828 A CN 105653828A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/82—Auxiliary processes, e.g. cleaning or inspecting
- G03F1/84—Inspecting
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
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- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The invention provides a friendliness checking method aimed at a photoetching technology for layout design data revision. The friendliness checking method comprises the following steps: preparing layout design data; conducting photoetching friendliness checking on the layout design data, and judging whether the layout design data are final decision or not, wherein the processing is finished when the layout design data are final decision; if the layout design data are not final decision, conducting reversion on part of the layout design data, then comparing the data before reversion and the data after reversion to obtain different zones between the data before reversion and the data after reversion, amplifying the different zones, and conducting photoetching friendliness checking on the layout design data obtained after reversion again aiming at the different zones.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is specifically related to manufacturability design DFM (DesignForManufacture) field, it is more particularly related to a kind of photoetching process friendliness for layout design data correcting checks (LithographyFriendlyDesignCheck) method.
Background technology
Integrated circuit has followed Moore's Law since being born always, and namely the characteristic size of chip shortens half in every 18 months. But after entrance immersion lithography, when exposure bench does not update, exposure figure size constantly reduces, can produce many to meet design rule and the poor litho pattern of actual process window. For avoiding layout design data that the figure that such lithographic process window is poor occurs, it is necessary to carry out photoetching process friendliness inspection after layout design data complete.
Fig. 1 show existing layout design photolithography process inspection. Layout data designer is typically in after layout design data complete 101 to carry out photoetching friendliness inspection. When photoetching process friendliness checks by 111, layout design design data flow process terminates, and enters layout data verdict (Tapeout) flow process. But, in actual design process, often complete in layout design data, photoetching process friendliness inspection is by judging at this whether layout design data decide on a verdict 121 after all completing. If decided on a verdict, process terminates, if unjelled, carries out part layout design data correcting 131. It is little much that the data volume of correcting generally compares original layout design data volume, but once correcting is necessary for again whole layout design data being carried out photoetching process friendliness inspection. This way can consume the substantial amounts of time for the layout design data light carving technology friendliness inspection after correcting.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that a kind of for the efficiency light carving technology friendliness inspection method after layout design data correcting.
In order to realize above-mentioned technical purpose, according to the present invention, it is provided that the friendliness inspection method of a kind of photoetching process for layout design data correcting, including: prepare layout design data; The photoetching friendliness performing layout design data checks, now judges whether layout design data decide on a verdict; If decided on a verdict, process terminates, if unjelled, carries out part layout design data correcting; Comparing before and after domain correcting is carried out after part layout design data correcting, to obtain diff area before and after correcting, it is amplified diff area before and after correcting subsequently processing, after being amplified diff area before and after correcting processing, again performs the photoetching friendliness inspection of layout design data for diff area before and after correcting.
Preferably, described after part layout design data correcting, carry out the step of comparing before and after domain correcting include: to data acquisition XOR before and after domain correcting, produce difference and be not less than the layout data diff area of 1 storage cell as diff area before and after correcting.
Preferably, when being amplified diff area before and after correcting processing, first judge the original size of diff area, subsequently diff area is amplified.
Preferably, when being amplified diff area before and after correcting processing, the amplification of processing and amplifying is 3 times of design key sizes.
Preferably, carry out comparing before and after domain correcting after the correcting of part layout design data to include: the data after the described part layout design data in the layout design data of preparation and described part layout design data correcting compared.
Preferably, the step of the described photoetching friendliness inspection again performing layout design data after being amplified diff area before and after correcting processing for diff area before and after correcting includes: extension preliminary dimension justice in diff area before and after the correcting after amplification is produced ring-band shape, as the auxiliary area that friendliness checks.
Preferably, preliminary dimension is 1.5 times of design key sizes.
Preferably, final photoetching process design review (check) (DR) result is that before checking generation result upper correcting after correcting, non-correcting range check generates result.
The invention provides a kind of for the photoetching process friendliness inspection method after layout design data correcting, the inefficiency problem that after solving the small change of traditional layout design data, photoetching process friendliness checks. In the process, mainly through the difference of layout design data before and after comparison correcting, adopting regional area photoetching friendliness inspection, it is greatly shortened the review time; Especially under high-end integrated circuit processing procedure, layout design data volume is huge, and the present invention more can play its odds for effectiveness.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 schematically shows existing layout design photoetching process check process.
Fig. 2 schematically shows the flow chart of the friendliness inspection method of photoetching process for layout design data correcting according to the preferred embodiment of the invention.
Fig. 3 represents the part sectional drawing of the first edition layout design data in the concrete example of the present invention.
Fig. 4 represent in the concrete example of the present invention based on the layout design data after Fig. 3 data correcting.
Fig. 5 represents the layout design first edition in the concrete example of the present invention and second edition Data Comparison result.
Fig. 6 represents that the photoetching process friendliness checking process region in the concrete example of the present invention divides.
Fig. 7 represents that the photoetching process friendliness in the concrete example of the present invention checks that result formation zone divides.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention. Note, represent that the accompanying drawing of structure is likely to be not necessarily drawn to scale. Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure clearly with understandable, below in conjunction with specific embodiments and the drawings, present disclosure is described in detail.
But need after the correcting small for solving above-mentioned layout design data to expend the plenty of time for photoetching process friendliness inspection, according to the preferred embodiment of the present invention, it is proposed that the flow chart of the friendliness inspection method of the photoetching process for layout design data correcting shown in Fig. 2.
As in figure 2 it is shown, the friendliness inspection method for the photoetching process of layout design data correcting includes according to the preferred embodiment of the invention:
Prepare layout design data (first step 201);The photoetching friendliness performing layout design data checks (second step 211), now judges whether layout design data decide on a verdict (third step 221), if decided on a verdict, process terminates, if unjelled, carries out part layout design data correcting (the 4th step 231), comparing is carried out before and after domain correcting (namely after part layout design data correcting, data after described part layout design data in the layout design data of preparation and described part layout design data correcting are compared), to obtain diff area before and after correcting (the 5th step 241), it is amplified diff area before and after correcting subsequently processing (the 6th step), again perform photoetching friendliness inspection (second step 211) of layout design data for diff area before and after correcting after being amplified diff area before and after correcting processing.
Preferably, described after part layout design data correcting, carry out the step of comparing before and after domain correcting include: to data acquisition XOR before and after domain correcting, produce difference and be not less than or beyond the layout data diff area of 1 storage cell as diff area before and after correcting.
Such as, when being amplified diff area before and after correcting processing, it is possible to first judge the original size of diff area, subsequently diff area is amplified.
Preferably, when being amplified diff area before and after correcting processing, the amplification of processing and amplifying is 3 times of design key sizes.
For example, it is possible to non-correcting range check generates result before inspection after correcting is generated result upper correcting, as final photoetching process design review (check) (DR) result.
Below in conjunction with concrete example, said method is illustrated.
Assuming that first edition layout design data are J1, generating second edition layout design data after correcting becomes J2, and the whole photoetching process friendliness inspection that the embodiment of the present invention is prominent can be summarized as following steps:
(1), after first edition layout design data J1 carries out the inspection of photoetching process friendliness, generate and check that result is A1.
(2) layout design data J2 and the J1 after correcting making XOR, screening operation result is more than the figure of 1 storage cell, i.e. J1 J2 > 1dbu. Difference layout design data before and after the correcting filtered out after representing process with J3.
(3) the difference layout design data J3 size filtered out is amplified a, a and be of a size of 3 times of design key sizes, i.e. J3*a. And these layout design data produced after amplifying are called J4.
(4) the layout design data J4 extension b after amplification producing ring-band shape (this ring-band shape region is only used as inspection auxiliary area), b is of a size of 1.5 times of design key sizes. The layout design data of ring-band shape are become J5.
(5) J4 being carried out photoetching process inspection, this checking process is with reference to the data in J5 region. Check that the result produced is B1. And first edition design data result A2 in J4 region represents.
(6) result of final second edition layout design data adopts A1-A2+B1 to represent.
Present invention achieves more rapid effective layout design photoetching process friendliness inspection.
After tested, certain layout design first edition data light carving technology design friendly checks 4.5h consuming time, adopts traditional layout design data light carving technology friendliness to check 4.6h consuming time after correcting. And adopt that the photoetching process friendliness check process of the present invention is consuming time is only 0.2h. Check that speed significantly promotes.
Fig. 3 to Fig. 7 illustrates a concrete example of the present invention.
What Fig. 3 represented is the part sectional drawing of first edition layout design data, and first edition layout design data D represents. First edition layout design data check through layout design data light carving technology friendliness, and the inspection result generated represents with F.
Layout design data after Fig. 3 data correcting that what Fig. 4 represented be based on. This edition territory design data E represents.
Coming comparison diagram 3 and Fig. 4 layout design data by XOR, XOR allows tolerance to be 1 storage cell, i.e. D E > 1dbu, generates new region. As Fig. 5 checks that this correcting relates to layout design altogether and changes 3 places, 501,502 and 503. Being amplified above-mentioned three place's differences processing, value of magnification is a, a value is 3 times of design key sizes, as shown in figure legend, must produce dashed region 511.
As shown in Figure 6, by 601 (equivalent regions 511) the outside extension b in each limit, region, producing endless belt 602 region. When new edition designs the photoetching process design friendly inspection of data E, 601 for checking main region, and 602 is then auxiliary area. This method can guarantee that the accuracy of photoetching process friendliness design review (check) (DR). The result generated after inspection represents with A, and the photoetching process friendliness of this main region of the first edition checks that result is C.
As it is shown in fig. 7, check the inspection result B before in result A upper other region of layout design in the photoetching process friendliness inspection result then diff area 701 of new edition layout design data. Check the result B inspection result C then being excluded in 701 regions by the result F of first edition photoetching process friendliness inspection. Namely after correcting, the result of photoetching process friendliness inspection is F-C+A.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the description such as the term in description " first ", " second ", " the 3rd " is used only for each assembly in differentiation description, element, step etc., rather than is used for logical relation or the ordering relation etc. that represent between each assembly, element, step.
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is not limited to the present invention. For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all may utilize the technology contents of the disclosure above and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations. Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (8)
1. the friendliness inspection method for the photoetching process of layout design data correcting, it is characterised in that including: prepare layout design data; The photoetching friendliness performing layout design data checks, now judges whether layout design data decide on a verdict; If decided on a verdict, process terminates, if unjelled, carries out part layout design data correcting; Comparing before and after domain correcting is carried out after part layout design data correcting, to obtain diff area before and after correcting, it is amplified diff area before and after correcting subsequently processing, after being amplified diff area before and after correcting processing, again performs the photoetching friendliness inspection of layout design data for diff area before and after correcting.
2. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 1, it is characterized in that, described after part layout design data correcting, carry out the step of comparing before and after domain correcting include: to data acquisition XOR before and after domain correcting, produce difference and be not less than the layout data diff area of 1 storage cell as diff area before and after correcting.
3. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 1 and 2, it is characterized in that, when being amplified diff area before and after correcting processing, first judge the original size of diff area, subsequently diff area is amplified.
4. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 1 and 2, it is characterised in that when being amplified diff area before and after correcting processing, the amplification of processing and amplifying is 3 times of design key sizes.
5. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 1 and 2, it is characterized in that, carry out comparing before and after domain correcting after part layout design data correcting and include: the data after the described part layout design data in the layout design data of preparation and described part layout design data correcting are compared.
6. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 1 and 2, it is characterized in that, the step of the described photoetching friendliness inspection again performing layout design data after being amplified diff area before and after correcting processing for diff area before and after correcting includes: extension preliminary dimension justice in diff area before and after the correcting after amplification is produced ring-band shape, as the auxiliary area that friendliness checks.
7. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 6, it is characterised in that preliminary dimension is 1.5 times of design key sizes.
8. the friendliness inspection method of the photoetching process for layout design data correcting according to claim 1 and 2, it is characterized in that, final photoetching process design review (check) (DR) result is that before checking generation result upper correcting after correcting, non-correcting range check generates result.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610173339.0A CN105653828B (en) | 2016-03-24 | 2016-03-24 | For the friendly property inspection method of the photoetching process of layout design data correcting |
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| CN201610173339.0A CN105653828B (en) | 2016-03-24 | 2016-03-24 | For the friendly property inspection method of the photoetching process of layout design data correcting |
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| CN105653828B CN105653828B (en) | 2019-05-31 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101201854A (en) * | 2006-12-15 | 2008-06-18 | 上海华虹Nec电子有限公司 | Method for constructing integrated circuit territory |
| US7865857B1 (en) * | 2007-01-23 | 2011-01-04 | Cadence Design Systems, Inc. | System and method for improved visualization and debugging of constraint circuit objects |
| CN102346800A (en) * | 2011-11-08 | 2012-02-08 | 中国科学院微电子研究所 | Method and device for detecting acceleration design rule |
| US20140033159A1 (en) * | 2012-07-26 | 2014-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Optimizing Design for Manufacturing (DFM) |
| CN103645611A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | Layout design photolithographic technology friendliness detection method |
| CN103744267A (en) * | 2013-11-28 | 2014-04-23 | 上海华力微电子有限公司 | Layout design photoetching technology friendliness detection method based on regular figure filtering |
| CN104460226A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Automatic repair method of hot spots of photolithography technique |
| CN104715116A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Landscape photolithography technique friendliness checking method |
-
2016
- 2016-03-24 CN CN201610173339.0A patent/CN105653828B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101201854A (en) * | 2006-12-15 | 2008-06-18 | 上海华虹Nec电子有限公司 | Method for constructing integrated circuit territory |
| US7865857B1 (en) * | 2007-01-23 | 2011-01-04 | Cadence Design Systems, Inc. | System and method for improved visualization and debugging of constraint circuit objects |
| CN102346800A (en) * | 2011-11-08 | 2012-02-08 | 中国科学院微电子研究所 | Method and device for detecting acceleration design rule |
| US20140033159A1 (en) * | 2012-07-26 | 2014-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of Optimizing Design for Manufacturing (DFM) |
| CN103744267A (en) * | 2013-11-28 | 2014-04-23 | 上海华力微电子有限公司 | Layout design photoetching technology friendliness detection method based on regular figure filtering |
| CN103645611A (en) * | 2013-11-29 | 2014-03-19 | 上海华力微电子有限公司 | Layout design photolithographic technology friendliness detection method |
| CN104460226A (en) * | 2014-11-28 | 2015-03-25 | 上海华力微电子有限公司 | Automatic repair method of hot spots of photolithography technique |
| CN104715116A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Landscape photolithography technique friendliness checking method |
Non-Patent Citations (1)
| Title |
|---|
| 彭毅等: "异或法实现图像差异提取", 《黑客防线》 * |
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