CN105653404B - The equipment altered for detecting state machine clock pulse - Google Patents
The equipment altered for detecting state machine clock pulse Download PDFInfo
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- CN105653404B CN105653404B CN201410729295.6A CN201410729295A CN105653404B CN 105653404 B CN105653404 B CN 105653404B CN 201410729295 A CN201410729295 A CN 201410729295A CN 105653404 B CN105653404 B CN 105653404B
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Abstract
The present invention provides a kind of equipment altered for detecting state machine clock pulse, including：Host state machine and secondary status machine.Host state machine has major state and is driven by main clock pulse, and major state can be switched in response to event.Secondary status machine has secondary status and is driven by auxiliary clock pulse synchronous with main clock pulse, in response to being at least based on event signal generated and changeable secondary status, it is corresponding between major state and secondary status to establish, therefore it connects after altering main clock pulse, corresponding between major state and secondary status becomes inconsistent, thus represents main clock pulse and has been tampered.
Description
Technical field
The present invention relates to a kind of state machine more particularly to a kind of equipment altered for detecting state machine clock pulse.
Background technique
It is known in the art the state machine implemented with electronic type, it includes the state machines with multiple clock pulses or unit.
For example, the 4th, 480, No. 198 United States Patent (USP) discloses the device or for increasing duplication clock pulse operational safety
8,229, No. 111 United States Patent (USP)s are disclosed using at least two finite state machine units or the 5th, 377, No. 205 beauty
State's patent discloses the equipment with multiple state machines and multiple clock pulses.
Summary of the invention
The present invention provides a kind of equipment altered for detecting state machine clock pulse.
One exemplary embodiment of the present invention is the equipment altered for detecting state machine clock pulse, which includes：It is main
State machine and secondary status machine.The host state machine has major state and is driven by main clock pulse, can be switched in response to event
The major state.The secondary status machine has secondary status and is driven by the auxiliary clock pulse synchronous with main clock pulse, in response at least
The secondary status can be switched based on event signal generated, thus establish it is corresponding between major state and secondary status, because
This is connected at alter main clock pulse after, corresponding between major state and secondary status becomes inconsistent, thus represent main clock pulse by
Alter.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Some non-restrictive illustrative embodiments or feature illustrate in the following figures in the present invention.
Occur in one or more of the drawings it is identical, repeat, equivalent or similar structure, element or part usually generally
It is marked using same reference numerals, and can be without repeating label and/or description.
Previously mentioned presented element implies the attached drawing for being not necessarily to further occur at it or explanation to quote.
Fig. 1 schematically illustrates according to the block diagram of the structure for the exemplary embodiment invented and for detecting state machine
The signal of clock pulse altered；
Fig. 2 is illustrated according to the exemplary embodiment invented in response to the host state machine of equivalent similar events and auxiliary shape
The state of state machine and the conversion between it.
Description of symbols：
100：Structure；
102：Host state machine；
104：Major state；
106：Secondary status machine；
108：Color；
112：Verify circuit；
122：Event；
114,116,124,126：Arrow；
128：Auxiliary signal；
222,224,226,228,246,248：Transition arrow；
132：Main clock pulse；
134：Assist clock pulse；
136：Pecked line；
142：Logic circuit；
144：Dotted line；
210,240：Figure；
212,214,216,218：State；
232：Event I；
234：Event II；
236：Event III；
238：Event IV；
242,244：Secondary status.
Specific embodiment
In the case of unrestricted, state machine is the existing state machine in this field to the contents of the present invention, for example, storage is given
The situation or state fixed time, in response to appearance condition or event and change the situation or state and may to start other dynamic
The device of work.
In general, state machine is referred to as the device including electronic circuit and element in the present invention, but not exclude it
Emulation and/or simulation.
For simplicity and in the case of unrestricted, cause the condition converted from a state to another state
Or event or any presence are referred to as event together.
In the content of the present invention, host state machine refers to the main or kernel state machine for being operable to carry out groundwork,
And secondary status machine refers to the state machine that can operate together with host state machine and be used to verify or test host state machine operation.
For clarity and brevity, the clock pulse of host state machine and state are also referred to as main clock pulse and major state.It is similar
Ground, the clock pulse and state of secondary status machine are also referred to as auxiliary clock pulse and secondary status, and secondary status is also referred to as " color
(color)”。
In the content of the present invention, in the case of unrestricted, the state machine of clock pulse driving refers to its state or state
The state machine that value is arranged by clock signal or keeps or gate (strobbed) or latch；That is, when event cause from
One state to next state conversion when, next state by clock signal maintained until there is another conversion until.
In the content of the present invention, synchronous with another device referring to a device and/or operation simultaneously is meaned
Actually synchronous or simultaneously operation, although may due to element different permissible deviations and/or inherent delay and/or when
Between the factors such as change without complete exactly simultaneous generation.
In the content of the present invention, the clock pulse for altering state machine means to deactivate or cuts clock pulse conductor or pass through this field
Any technology destroy clock pulse, however that, unless otherwise stated, the clock pulse for altering state machine also means state machine at least phase
For the trouble or failure of its clock pulse.
Above-cited term is also represented by its deformation and conjugate.
A technical problem solved by the invention is altering for the main clock pulse of the host state machine of detection clock pulse driving.
A technical solution according to the present invention is that host state machine is added to secondary status machine, and the secondary status machine is logical
It crosses optionally independent auxiliary clock pulse to drive, wherein the auxiliary clock pulse is synchronous with main clock pulse.The secondary status machine is configured to
Together with one biconditional operation of host state machine and the event of host state machine is responded, method is same by the conversion with host state machine
Step ground changes secondary status.The transition response of secondary status machine is in passing through logic circuit auxiliary signal generated, at least one
In a little embodiments, logic circuit considers the state of host state machine.
Host state machine and secondary status machine be arranged such that the state of host state machine and the secondary status of secondary status machine or
Color corresponds to each other or matches each other.
Therefore, in the case where the main clock pulse of host state machine is tampered, host state machine is maintained at before main clock pulse is tampered
The last one state.
It however, auxiliary clock pulse remains operational, and still can operate secondary status machine and in response to auxiliary signal, use change
Color.Therefore, corresponding between the last one state of host state machine and current color cannot keep constant, when then indicating main
Arteries and veins breaks down.
In order to detect and alert the destruction operation of main clock pulse, the matching of verifying major state and color is designed and is configured to
Circuit (also referred to as verifying circuit) and host state machine and secondary status machine be linked together or be connected to host state machine and auxiliary
It helps on state machine.Verifying circuit perceives major state and color and/or major state and color can be obtained, and identifies color not
Corresponding to major state or with the unmatched situation of major state, and this result can be alerted, then indicate altering for main clock pulse.
The warning can be any suitable form or technology, for example, passing through specified electronic signal or audible signal or luminous two
Pole pipe (LED) light passes through trigger action etc..
Therefore, host state machine is used for the combination and/or combination of secondary status machine and with the link offer of verifying circuit
It detects and at least optionally notifies altering for main clock pulse.
Although altering two it should be noted that the clock pulse for altering circuit is well known in the art technology
Clock pulse is more difficult and complicated, in addition, we are also not intended to generate additional clock pulse.
It should also be noted that corresponding between major state and color is not necessarily one-to-one in itself.For example, a pair of
More correspondences, two of them or more than two major states are mapped to a color or correspond to a color.
In some embodiments, in order to further ensure the detection of main clock pulse altered, multiple secondary status machines can be with
Host state machine combination, even if so that winner's clock pulse and auxiliary clock pulse are tampered, then one or more additional secondary status machines
And one or more auxiliary clock pulses still continuous service, and the detection altered and notice such as the main clock pulse above can be carried out.
A potential technology effect of the invention be for detect and alarm state machine clock pulse alter or failure it is simple
Equipment, so as to avoid complicated circuit.
It has appeared herein below and has practiced substantially non-limiting summary of the invention.This summarises the embodiment of the present invention
Illustrative practice, to provide the construction foundation of variation and/or substitution and/or diverging embodiment.
Fig. 1 schematically illustrates according to the block diagram of the structure 100 for the exemplary embodiment invented and for detecting shape
The signal that state machine clock pulse is altered.
Host state machine 102 with major state 104 and the secondary status machine 106 with color 108 as secondary status
It operates together as described hereinafter.
As illustrated by arrow 124, host state machine receives event (for example, event 122).Event 122 realizes host state machine 102
Conversion provide major state 104 to logic circuit 142, logic electricity and in addition as by a dotted line 144 schematically illustrate
Road 142 is generated based on major state 104 provides the auxiliary signal 128 for arriving secondary status machine 106.In response to auxiliary signal 128, auxiliary
The conversion of state machine 106 and host state machine 102 switches color simultaneously.
It should be noted that the conversion of host state machine 102 and the conversion of secondary status machine 106 can not necessarily change main shape respectively
State 104 and/or color 108.Therefore, host state machine 102 and/or secondary status machine 106 can be switched to respectively or effectively protect
It holds in current major state 104 and/or color 108.
It should also be noted that in some embodiments or situation, logic circuit 142 is it is not intended that major state, so that not
By major state 104 how, auxiliary signal 128 can trigger the conversion of secondary status machine 106.
Major state 104 and color 108 are strobed or latch, or are set respectively by main clock pulse 132 and auxiliary clock pulse 134
It sets, wherein main clock pulse 132 and auxiliary clock pulse 134 synchronize (as schematically shown by pecked line 136).In some implementations
In example, main clock pulse 132 and auxiliary clock pulse 134 are independently of mutual.Alternatively, in some embodiments, main clock pulse 132 and auxiliary
Clock pulse 134 is driven by identical timing circuit.
Since the conversion of host state machine 102 and secondary status machine 106 passes through event 122 and auxiliary signal 128 simultaneously respectively
It realizes, and since major state 104 and color 108 are arranged by synchronous main clock pulse 132 and auxiliary clock pulse 134 respectively,
There are corresponding or correlations between major state 104 and color 108.
In the case where main clock pulse 132 is changed into and does not run (for example, due to alter and/or failure and/or failure), main shape
State machine 102 is maintained at the last one major state 104.However, having the independent and auxiliary clock pulse 134 unrelated with host state machine 102
Secondary status machine 106 operated in response to event 122.Therefore, finally, the corresponding or phase between major state 104 and color 108
Closing property becomes inconsistent or uncorrelated, to indicate that the host state machine 102 at least relative to main clock pulse 132 breaks down.
Verifying circuit 112 is formed to check whether major state 104 and color 108 correspond to each other, and at least optionally,
When occur between major state 104 and color 108 it is uncorrelated or it is inconsistent to it is corresponding when start alarm.Therefore, circuit is verified
112 are connected to host state machine 102 and secondary status machine 106, and can get the main shape indicated respectively by arrow 114 and arrow 116
State 104 and color 108.
Therefore, by means of example, it is assumed that major state 104 is in " state A " and should be switched in response to event 122
" state B ", and correspondingly, color 108 is " green " color and should be switched to " blue " color in response to event 122.
Therefore, in the case where main clock pulse 132 is tampered, the switching of host state machine 102 is destroyed and host state machine 102
Major state 104 rests on " state A ", while secondary status machine 106 responds event 122 and when color 108 passes through auxiliary
Arteries and veins 134 is set as " blue ".Therefore, the correlation of major state 104 with color 108 is destroyed.
Due to the detection of verifying circuit 112 or the false correlations of identification major state 104 and color 108, in some realities
It applies in example, verifying circuit 112 is configured to starting operation (for example, generating alarm).For example, feux rouges is opened, and works as main shape
State 104 and color 108 correspond to that at this point, optionally opening green light；Or, for example, verifying circuit 112 can be through forming
To reset host state machine and/or otherwise influence host state machine 102 to deactivate mentioning for data (for example, confidential data)
It takes.
In some embodiments, major state 104 and the secondary status as color 108 are such as the existing side of institute in this field
Formula is implemented.For example, the flip-flop array by indicating data bit, wherein the number of element or data bit indicate major state
104 and the secondary status as color 108 be not necessarily identical.
It should also be noted that major state 104 may not be one-to-one relationship with the corresponding or correlation of color 108, and
Being can actually be at least partly one-to-many or many-to-one correspondence.
Therefore, by means of example, the major state 104 as " state A " and " state B " can correspond to " blue " color,
And the major state 104 as " state C " can correspond to " green " color.
When major state 104 is not relative to each other with color 108 with fully corresponding, until final main clock pulse
It destroys before being identified by verifying circuit 112, in fact it could happen that multiple conversions of secondary status machine 106.
Main clock pulse 132 can be executed with auxiliary the synchronous of clock pulse 134 by the technology of this field.For example, it uses
Separate clocking circuit with equivalent crystal so that winner's clock pulse 132 and auxiliary clock pulse 134 be independently of it is mutual；Or it lifts
For example, main clock pulse 132 and auxiliary clock pulse 134 are driven from identical time signal source.
It should be noted that color is symbolically used for its corresponding secondary status, with further elucidate major state 104 with it is auxiliary
Help the difference between state.
It should also be noted that host state machine 102 is configured to the part in large scale system or device and as large size
Part in system or device operates, and the large scale system or device be, for example, the security system controlled by host state machine 102, with
So that providing the destruction of detection host state machine 102 and being made a response by adequate measures (for example, deactivating host state machine
102)。
In some embodiments, verifying circuit 112 is included in host state machine 102 and/or secondary status machine 106.
In some embodiments, as and/or similar to multiple secondary status machines of secondary status machine 106 are in response to auxiliary
Signal 128 is operated together with host state machine 102 so that as and/or similar to auxiliary clock pulse 134 auxiliary clock pulse
Or in the case that secondary status machine is also tampered or does not run, remaining secondary status machine can be such as the detection host state machine above
102 failure.Likewise it is possible to implement multiple logic circuits 142.Therefore, there is extra secondary status machine at least potentially
Increase the reliability altered for detecting its host state machine 102 and/or the main clock pulse 132 of clock pulse.
According to the exemplary embodiment of invention, Fig. 2 illustrates response by means of being similar to the simplified example of structure 100
In the host state machine of equivalent similar events and the state of secondary status machine and the conversion between it.
Figure 21 0 illustrates four major states and conversion of the host state machine in response to event.Major state is expressed as：
" state A ", is expressed as state 212；" state B ", is expressed as state 214；" state C ", is expressed as state 216；And " state
D " is expressed as state 218.
In response to the event similar with event 122, major state switches therebetween.(event is expressed as in response to event I
232), host state machine is switched to " state B " (as illustrated by transition arrow 222) from " state A "；It (is expressed as in response to event II
Event 234), host state machine is switched to " state C " (as illustrated by transition arrow 224) from " state B "；In response to event III (table
It is shown as event 236), host state machine is switched to " state D " (as illustrated by transition arrow 226) from " state C "；And in response to event
IV (is expressed as event 238), and host state machine switches back to " state A " (as illustrated by transition arrow 228) from " state D ".
Figure 24 0 illustrates two secondary status of the secondary status machine in response to the auxiliary signal similar with auxiliary signal 128
And conversion, the auxiliary signal correspond to or are effectively equivalent to similar events, that is, be equivalent to event I, event II, event III and
Event IV.Therefore, in order to be simplified, the auxiliary signal that the logic circuit similar with logic circuit 142 generates is not dependent on
The state of host state machine, for example, event is re-introduced into auxiliary signal.
Secondary status is by being expressed as " black " color of secondary status 242 and being expressed as " white " of secondary status 244
Color representation.
Accordingly, in response to event I or event III, " black " color is switched to " white " color and (such as passes through transition arrow
Illustrated by 246), and in response to event II or event IV, " white " color is switched to " black " color and (such as passes through transition arrow
Illustrated by 248).
Correspondingly, " state A " and " state C " it is corresponding at two pair one in correspond to " black " color, and " state B " and
Correspond to " white " color during " state D " is corresponding at two pair one.
10 and Figure 24 0 and reference configuration 100 according to fig. 2 will not when the following conditions (1) and condition (2) are effective
Identify or indicate altering for main clock pulse；Otherwise in the case where the condition that is unsatisfactory for (1) or condition (2), it can indicate and identify master
Clock pulse is altered or is destroyed.
(color==" black ") && ((major state==" state A ") II (major state==" state C ")) (1) (color
==" white ") && ((major state==" state B ") II (major state==" state D ")) (2)
Above-mentioned condition is formulated according to C programming language.
Obviously, need at least two bit to indicate four major states, and need at least one bit come indicate two it is auxiliary
Help state (being similar to even-odd check).
Compared to multiple conversions of the host state machine with two colors as illustrated in top and the correspondence of major state, one
Secondary status machine is configured and/or constructs in a little embodiments, so that each conversion of host state machine and secondary status machine switches
To different unique colors, therefore establish corresponding between major state and secondary status.
In some embodiments, as noted above, the centre occurred between major state and color is corresponding, for example, 6 masters
State can correspond to 3 colors.
Therefore a kind of equipment altered for detecting state machine clock pulse is provided according to the present invention, which includes：Main shape
State machine and secondary status machine.The host state machine has major state and is driven by main clock pulse, and can be switched in response to event
The major state；The secondary status machine has secondary status and is driven by the auxiliary clock pulse synchronous with main clock pulse, and in response to extremely
Less based on event signal generated and the secondary status can be switched, thus establish it is corresponding between major state and secondary status,
Therefore connect after altering main clock pulse, corresponding between major state and secondary status becomes inconsistent, thus represent main clock pulse by
Alter.
In some embodiments, due to finally violating between major state and secondary status after main clock pulse is tampered
Corresponding, corresponding between major state and secondary status becomes inconsistent.
In some embodiments, which further comprises verifying circuit, which is configured to detection major state
It is inconsistent corresponding between secondary status.
In some embodiments, which is configured to respond to inconsistent between detection major state and secondary status
Correspondence and starting operation.
In some embodiments, which includes perceptible alarm.
In some embodiments, which includes influencing host state machine.
In some embodiments, which further comprises multiple secondary status machines, therefore be tampered in auxiliary clock pulse
In the case of increase the reliability altered for detecting main clock pulse.
Mean herein for term " configuration " used in an object and/or " use " or its variation to be designed for
The mode and/or mechanism for obtaining target use element.
Term as used herein should not be construed as limiting, unless otherwise stated, and art used herein
Language is only the purpose for description specific embodiment, and is not intended to limitation and is invented.Although having illustrated and described this hair
Bright some embodiments, but it is clear that the present invention is not limited to the embodiments herein.It is not precluded and many modify, changes, changing, replacing
For object and equivalent.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, those skilled in the art should understand that：Its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (6)
1. a kind of equipment altered for detecting state machine clock pulse, which is characterized in that the equipment includes：
Host state machine, the host state machine have major state and are driven by main clock pulse, and the major state can be switched in response to event；
And
An at least secondary status machine, the secondary status machine have secondary status and are driven by the auxiliary clock pulse synchronous with the main clock pulse
It is dynamic, the secondary status can be switched in response to being at least based on event signal generated, so that it is auxiliary with this to establish the major state
The correspondence between state is helped,
Therefore it connects after altering the main clock pulse, the major state of the host state machine is maintained at the last one state, and the secondary status
Machine is still operated by auxiliary clock pulse and in response to the signal, this for making between the major state and the secondary status corresponding becomes different
It causes, thus represents the main clock pulse and be tampered.
2. equipment according to claim 1, which is characterized in that further include：
Circuit is verified, which is configured to detect inconsistent corresponding between the major state and the secondary status.
3. equipment according to claim 2, which is characterized in that the verifying circuit be configured to respond to detect the major state with
The inconsistent correspondence between the secondary status and start a movement.
4. equipment according to claim 3, which is characterized in that the movement includes perceptible alarm.
5. equipment according to claim 3, which is characterized in that the movement includes influencing the host state machine, and influence the main shape
State machine includes the extraction for resetting the host state machine and deactivated confidential data.
6. equipment according to claim 1, which is characterized in that further include：
Multiple secondary status machines, thus in the case where the auxiliary clock pulse is tampered increase detect the main clock pulse alter it is reliable
Property.
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| CN201410729295.6A CN105653404B (en) | 2014-12-04 | 2014-12-04 | The equipment altered for detecting state machine clock pulse |
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| CN105653404B true CN105653404B (en) | 2018-11-30 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101553785A (en) * | 2006-12-08 | 2009-10-07 | 吴灿炜 | State machine and system and method of implementing a state machine |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5511181A (en) * | 1993-04-26 | 1996-04-23 | Apple Computer, Inc. | Polycyclic timing system and apparatus for pipelined computer operation |
| CN101609308A (en) * | 2008-06-20 | 2009-12-23 | 中国科学院沈阳自动化研究所 | Industrial intelligent terminal based on RFID data acquisition function and control method thereof |
| CN102737208B (en) * | 2011-04-14 | 2015-04-22 | 北京中电华大电子设计有限责任公司 | Method for decoding MMC type data by ultrahigh frequency electronic tag |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101553785A (en) * | 2006-12-08 | 2009-10-07 | 吴灿炜 | State machine and system and method of implementing a state machine |
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