CN1056473C - Interconnection device for semiconductor device and making method - Google Patents
Interconnection device for semiconductor device and making method Download PDFInfo
- Publication number
- CN1056473C CN1056473C CN96107262A CN96107262A CN1056473C CN 1056473 C CN1056473 C CN 1056473C CN 96107262 A CN96107262 A CN 96107262A CN 96107262 A CN96107262 A CN 96107262A CN 1056473 C CN1056473 C CN 1056473C
- Authority
- CN
- China
- Prior art keywords
- conduction type
- impurity diffusion
- semiconductor layer
- semiconductor
- trap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a production method for interconnection device for semiconductor device. The said device interconnects to each impurity diffusion area formed on semiconductor substrate, wherein each impurity diffusion area has different conductivity. The method comprises the following steps: the trap of the first conduction type and the trap of the second conduction type forming on semiconductor substrate; the impurity diffusion area of the first conduction type which does not contact with each other forming on the trap of the second conduction type; the impurity diffusion area of the second conduction type which does not contact with each other forming on the trap of the first conduction type; insulation film forming on the ultimate structure and selectively removing the insulation film; thus contact holes which bare impurity diffusion areas of the first conduction type and the second conduction type generating; semiconductor layer forming on the ultimate structure; slicide membrane forming on the semiconductor layer and annealing the ultimate structure; thus impurity ions of impurity diffusion areas of the first conduction type and the second conduction type being diffused into the semiconductor layer.
Description
The present invention relates to interconnection device for semiconductor device and manufacture method thereof, more particularly, relate to and be suitable for the interconnection device for semiconductor device that utilizes interconnection wiring that semiconductor element is connected together,, also relate to the method for making above-mentioned interconnection device for semiconductor device so that show electricity and architectural characteristic.
Usually, have the multi-crystal silicification thing of heat and structural stability, be widely used in interconnection device for semiconductor is connected together.Above-mentioned multi-crystal silicification thing is made up of polysilicon and silicide.Utilize the dielectric film below polysilicon and the silicide to form a knot.On the other hand, utilize silicide current limit district.
Routinely, in the diffusion region with identical impurity doped polysilicon, so that connect multi-crystal silicification thing and impurity diffusion zone.
For P type and N type impurity diffusion zone are linked together, conventional method is included in the non-doping silicon fiml of deposit on P type and the N type impurity diffusion zone, injects P type and n type impurity respectively in P type and N type impurity diffusion zone then.
But conventional method has variety of issue.
That is, in order to connect the impurity diffusion zone of different conduction-types, conventional method needs the secondary ion implantation step.In addition, whole technology is complicated, because in the zone that each step forms, should control the ion implantation technology condition that forms the contact zone.
Because adopt above-mentioned complicated technology, conventional method has reduced the reliability of semiconductor device.The result can not make high integrated semiconductor device.
Therefore, the objective of the invention is to solve problems of the prior art, and provide a kind of interconnection device for semiconductor device and manufacture method thereof, this device to have to simplify the structure that interconnects between the semiconductor element, therefore, can make high integrated and the semiconductor device that improves reliability.
According to a scheme of the present invention, it provides the semiconductor element interconnect devices, be connected each impurity diffusion zone that forms on the Semiconductor substrate, each impurity diffusion zone has different conductivity, this device comprises: the 1st conductive type of trap that forms on Semiconductor substrate and the trap of the 2nd conduction type, the 1st conductive type of trap has the 2nd conductive type impurity diffusion region, and the 2nd conductive type of trap has the 1st conductive type impurity diffusion region; Form dielectric film on Semiconductor substrate, dielectric film limits contact hole, in order to expose the 1st and the 2nd conductive type impurity diffusion region respectively; The 1st diffusion of impurities semiconductor layer and the 2nd diffusion of impurities semiconductor layer are respectively formed at the 1st and the 2nd conductive type impurity diffusion region that expose the bottom of contact hole separately; On the 1st and the 2nd diffusion of impurities semiconductor layer, form silicon fiml, be used to interconnect them.
According to another program, the invention provides a kind of method of making interconnection device for semiconductor device, this device is suitable for being connected each impurity diffusion zone that forms on the Semiconductor substrate, each impurity diffusion zone has different conductivity, and this method comprises the following steps: to form the 1st conductive type of trap and the 2nd conductive type of trap on Semiconductor substrate; Inject the foreign ion of the 1st conduction type at the well region of the 2nd conduction type, therefore, form mutually non-touching the 1st conductive type impurity diffusion region; Inject the foreign ion of the 2nd conduction type at the well region of the 1st conduction type, so form mutually non-touching the 2nd conductive type impurity diffusion region; Form dielectric film above the whole surface of exposing of the structure that after forming the 2nd conductive type impurity diffusion region, obtains; Selectively remove dielectric film, therefore form and expose the contact hole of the 1st and the 2nd conductive type impurity diffusion region; Form semiconductor layer above the whole exposing surface of the structure that after forming contact hole, obtains; On semiconductor layer, form silicide film; Anneal to forming the final structure that forms behind the silicide film, therefore, the foreign ion of the impurity diffusion zone of the 1st and the 2nd conduction type is diffused in the semiconductor layer.
By the explanation of the following accompanying drawing of reference to embodiment, other purpose of the present invention and various scheme will be apparent.
Figure 1A is the cutaway view of representing to make according to the present invention a kind of each sequential steps of method of interconnection device for semiconductor device respectively to Fig. 1 C.
Figure 1A represents to make according to the present invention each sequential steps of a kind of method of interconnection device for semiconductor device respectively to Fig. 1 C.
Shown in Figure 1A, according to the present invention, at first N type foreign ion and p type impurity ion are injected in the Semiconductor substrate, therefore, form N trap 11 and P trap 12 respectively.
After, in the desired part of Semiconductor substrate,, form the dielectric film 13 of isolated component respectively corresponding to passive region.By the dielectric film 13 of these isolated components, limit Semiconductor substrate with active area and passive region.
On each active area of Semiconductor substrate, form gate oxidation films 14.On each gate oxidation films 14, form gate electrode 15.
Utilize gate electrode 15 as mask, with the p type impurity of high concentration and the N trap 11 and the P trap 12 of N type impurity doped semiconductor substrate.Therefore form highly doped p type impurity diffusion region 16 and highly doped N type impurity diffusion zone 17 respectively.
On the whole exposed surface of the structure that obtains, form dielectric film 18, be used for planar surface.Dielectric film 18 is made up of bpsg film, demonstrates the USG/BPSG film of a kind of flowability or multilayer.
Shown in Figure 1B, utilize contact mask (not shown), by etching process, selectively remove dielectric film 18, form the 1st and the 2nd contact hole 19 and 20 thus, expose P type and N type impurity diffusion zone 16 and 17 respectively.
On the whole exposing surface of the structure that obtains, form a unadulterated silicon fiml 21 than minimal thickness.Unadulterated film 21, by the 1st and the 2nd contact hole 19 and 20 and Semiconductor substrate contact.Best, silicon fiml 21 has the thickness of about 200 dusts to about 700 dusts.
On silicon fiml 21, deposit has the silicide film 22 of required thickness.Under the condition that silicon fiml 21 is not doped, realize the deposit of silicide film 22.Best, silicide film 22 has the thickness of about 500 dusts to 3000 dusts.
Connect, shown in Fig. 1 C, utilize a mask (not shown), sequentially corrode the part of the requirement corrosion of silicide film 22 and silicon fiml 21 according to etching process.
Leave the corrosion silicification film 22 and the silicon fiml 21 of process allowance, be enough to prevent that the 1st and the 2nd contact hole 19 and 20 is damaged.In other words, even after corrosion, silicon fiml 21 and silicification film 22 still interconnect in the 1st and the 2nd contact hole 19 and 20.
After, the structure that obtains is arrived about 900 ℃ of annealing at about 800 ℃, the result is entrained in foreign ion in P type and N type impurity diffusion zone 16 and 17 and is diffused into and lays respectively among the part 21a of the 1st and the 2nd contact hole 19 and 20 than the undoped silicon films 21 of lower part, therefore, form doping silicon fiml 23 and 24.
As a result, at the adjacent active area of the Semiconductor substrate of isolating mutually by the dielectric film 13 of isolated component, the impurity diffusion zone of Xing Chenging may interconnect respectively, therefore, its relevant with adjacent active area respectively semiconductor element is interconnected.
Apparent by above-mentioned explanation, according to the device and the multiple effect that goes up of manufacture method generation thereof of interconnection device for semiconductor provided by the invention.For example,, utilize simple process, make the different conduction-types impurity diffusion zone interconnection that in Semiconductor substrate, forms according to the present invention.Therefore, may improve the reliability of semiconductor device.
Because the present invention has simplified the manufacturing interconnection device for semiconductor device, improved the reliability of semiconductor device, so realized the highly integrated of semiconductor device.
Though for goal of the invention is described; the preferred embodiments of the present invention are disclosed; but it will be understood by a person skilled in the art that the various modifications that may carry out, increase and minimizing all do not break away from disclosed invention protection range of claim and the spirit that the present invention has.
Claims (17)
1. an interconnection device for semiconductor device is connected the impurity diffusion zone that forms on the Semiconductor substrate, and each impurity diffusion zone has different conductances, and this device comprises:
The trap of the 1st conduction type that on Semiconductor substrate, forms and the trap of the 2nd conduction type, the trap of the 1st conduction type has the impurity diffusion zone of the 2nd conduction type, and the trap of the 2nd conduction type has the impurity diffusion zone of the 1st conduction type;
Form dielectric film on Semiconductor substrate, dielectric film limits contact hole, exposes the 1st and the 2nd conductive type impurity diffusion region respectively;
The 1st diffusion of impurities semiconductor layer and the 2nd diffusion of impurities semiconductor layer are respectively formed at the impurity diffusion zone of the 1st and the 2nd conduction type that exposes the bottom of contact hole separately;
On the 1st and the 2nd diffusion of impurities semiconductor layer, form silicide film, and interconnect them.
2. according to the interconnection device for semiconductor device of claim 1, it is characterized in that the 1st diffusion of impurities semiconductor layer is by forming with the conductivity identical materials of the 1st conductive type impurity diffusion region.
3. according to the interconnection device for semiconductor device of claim 1, it is characterized in that the 2nd diffusion of impurities semiconductor layer is by forming with the conductivity identical materials of the 2nd conductive type impurity diffusion region.
4. according to the interconnection device for semiconductor device of claim 1, the thickness that it is characterized in that the 1st diffusion of impurities semiconductor layer is that 200 dusts are to 700 dusts.
5. according to the interconnection device for semiconductor device of claim 1, the thickness that it is characterized in that the 2nd diffusion of impurities semiconductor layer is that 200 dusts are to 700 dusts.
6. according to the interconnection device for semiconductor device of claim 1, the thickness that it is characterized in that silicification film is that 500 dusts are to 3000 dusts.
7. according to the interconnection device for semiconductor device of claim 1, it is characterized in that dielectric film is made up of bpsg film.
8. according to the interconnection device for semiconductor device of claim 1, it is characterized in that dielectric film is made up of the USG/BPSG film of multilayer.
9. according to the interconnection device for semiconductor device of claim 1, also comprise the semiconductor layer that is arranged between dielectric film and the silicide film.
10. method of making interconnection device for semiconductor device, the impurity diffusion zone that this device interconnection forms on Semiconductor substrate, each impurity diffusion zone has different conductivity, and this method comprises the following steps:
On Semiconductor substrate, form the trap of the 1st conduction type and the trap of the 2nd conduction type, the foreign ion of the 1st conduction type is injected in the trap of the 2nd conduction type, thus, form mutually non-touching the 1st conductive type impurity diffusion region;
The foreign ion of the 2nd conduction type is injected in the trap of the 1st conduction type, thus, forms the impurity diffusion zone of mutually non-touching the 2nd conduction type;
After forming the 2nd conductive type impurity diffusion region, on the whole exposing surface of the structure that is obtained, form dielectric film;
Selectively remove dielectric film, therefore, form the contact hole of the impurity diffusion zone that exposes the 1st and the 2nd conduction type;
On the whole exposing surface of structure that obtains, form semiconductor layer;
On semiconductor layer, form silicide film;
Annealing forms the structure that is obtained behind the silicification film, and therefore, the foreign ion of the 1st and the 2nd conductive type impurity diffusion region is diffused in the semiconductor layer.
11. according to the method for claim 10, the thickness that it is characterized in that semiconductor layer is that 200 dusts are to 700 dusts.
12., it is characterized in that silicide film thickness is that 500 dusts are to 3000 dusts according to the method for claim 10.
13., it is characterized in that dielectric film is made up of bpsg film according to the method for claim 10.
14., it is characterized in that dielectric film is made up of the USG/BPSG film of multilayer according to the method for claim 10.
15. the method according to claim 10 is characterized in that, anneals 800 ℃ to 900 ℃ temperature range.
16. the method according to claim 10 is characterized in that, at annealing steps, foreign ion is diffused into and is arranged in the part of contact hole bottom semiconductor layer requirement diffusion separately.
17. the method according to claim 10 is characterized in that, utilizes the semiconductor layer doped part, makes the 1st to link to each other with silicification film respectively with the impurity diffusion zone of the 2nd conduction type.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006819A KR0140720B1 (en) | 1995-03-29 | 1995-03-29 | Semiconductor contact and manufacturing method thereof |
| KR6819/95 | 1995-03-29 | ||
| KR6819/1995 | 1995-03-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1139820A CN1139820A (en) | 1997-01-08 |
| CN1056473C true CN1056473C (en) | 2000-09-13 |
Family
ID=19410774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96107262A Expired - Fee Related CN1056473C (en) | 1995-03-29 | 1996-03-29 | Interconnection device for semiconductor device and making method |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR0140720B1 (en) |
| CN (1) | CN1056473C (en) |
| TW (1) | TW363224B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1049765C (en) * | 1997-04-08 | 2000-02-23 | 世界先进积体电路股份有限公司 | Method for making inter-connecting polycrystalline silicon to polycrystalline silicon low resistance contact on integrated circuit |
| CN1056469C (en) * | 1997-04-15 | 2000-09-13 | 世界先进积体电路股份有限公司 | Method for forming conductor and internal leadings of high compact integrated circuits |
| KR100445638B1 (en) * | 2002-07-26 | 2004-08-25 | 삼성전자주식회사 | Interconnection structure connecting electrically isolated regions and method of fabricatinging the same |
| KR100935298B1 (en) * | 2003-02-17 | 2010-01-06 | 매그나칩 반도체 유한회사 | Method of forming interconnection line for semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0324459A2 (en) * | 1988-01-14 | 1989-07-19 | Fujitsu Limited | Semiconductor integrated circuit having CMOS inverter |
-
1995
- 1995-03-29 KR KR1019950006819A patent/KR0140720B1/en not_active IP Right Cessation
-
1996
- 1996-03-28 TW TW085103723A patent/TW363224B/en not_active IP Right Cessation
- 1996-03-29 CN CN96107262A patent/CN1056473C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0324459A2 (en) * | 1988-01-14 | 1989-07-19 | Fujitsu Limited | Semiconductor integrated circuit having CMOS inverter |
Also Published As
| Publication number | Publication date |
|---|---|
| TW363224B (en) | 1999-07-01 |
| KR960036045A (en) | 1996-10-28 |
| KR0140720B1 (en) | 1998-06-01 |
| CN1139820A (en) | 1997-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5479054A (en) | Semiconductor device with improved planarization properties | |
| US4446613A (en) | Integrated circuit resistor and method of fabrication | |
| EP0126424A2 (en) | Process for making polycide structures | |
| CN1056472C (en) | Method for production of capacitor of semiconductor device | |
| CN1062979C (en) | Method of fabricating gate electrode of CMOS device | |
| CN100490062C (en) | Method of manufacturing semiconductor device | |
| CN1056473C (en) | Interconnection device for semiconductor device and making method | |
| US5622884A (en) | Method for manufacturing a semiconductor memory cell and a polysilicon load resistor of the semiconductor memory cell | |
| US5322815A (en) | Method for producing semiconductor device with multilayer leads | |
| CN1041472C (en) | Thin film transistor and method for fabracating the same | |
| KR920009372B1 (en) | Manufacturing method of semiconductor device | |
| CN1097310C (en) | Method of forming well of semiconductor device | |
| GB2223127A (en) | Static random access memory | |
| US20010006834A1 (en) | Semiconductor device with high- and low-density regions of transistor elements on single semiconductor substrate, and method of manufacturing such semiconductor device | |
| US5686323A (en) | Method of manufacturing a semiconductor device having an out diffusion preventing film | |
| KR0130382B1 (en) | Metalizing method of semiconductor device | |
| KR100415095B1 (en) | Method for manufacturing semiconductor device | |
| KR970009868B1 (en) | Method of metalizing a semiconductor device and the structure thereof | |
| KR100354278B1 (en) | Semiconductor device and method for manufacturing same | |
| KR100325461B1 (en) | Method of fabricating semiconductor device for preventing interconnection line from being shorted to metal contact | |
| EP0078221A2 (en) | Polycrystalline silicon diode with metal silicide contact | |
| KR100325462B1 (en) | Method of fabricating semiconductor device for preventing interconnection line from being shorted to metal contact | |
| KR100353531B1 (en) | Method of fabricating semiconductor device for preventing interconnection line from being shorted to metal contact | |
| KR100294825B1 (en) | Contact Forming Method of Semiconductor Device | |
| KR20010057117A (en) | Method of fabricating semiconductor device for preventing interconnection line from being shorted to metal contact |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20000913 Termination date: 20100329 |