CN105635003B - A kind of Base-band Processing System based on DMA - Google Patents
A kind of Base-band Processing System based on DMA Download PDFInfo
- Publication number
- CN105635003B CN105635003B CN201610018298.8A CN201610018298A CN105635003B CN 105635003 B CN105635003 B CN 105635003B CN 201610018298 A CN201610018298 A CN 201610018298A CN 105635003 B CN105635003 B CN 105635003B
- Authority
- CN
- China
- Prior art keywords
- dma
- dsp module
- data flow
- interface
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/026—Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a kind of Base-band Processing Systems based on DMA, including high-speed bus, low speed bus, microprocessor, memory, DMA unit, routing unit and multiple DSP modules, the high-speed bus is used to provide the high-speed data path of connection microprocessor, memory, DMA unit, low speed data access of the low speed bus for providing connection microprocessor, DSP module, the DMA unit are carried out data transmission by routing unit and DSP module.The present invention provides unified interface for DSP module, realizes that modularity designs to greatest extent, improves the handling capacity of DSP module interface, while can neatly increase or delete DSP module, scalability is good to greatest extent.
Description
Technical field
The present invention relates to signal processing technology field, more particularly to a kind of Base-band Processing System based on DMA.
Background technology
As wireless communication physical layer protocol becomes increasingly complex, the hardware realization of physical layer protocol is wirelessly communicated usually by micro-
Processor and multiple signal processing modules (DSP) collectively constitute, and become on-chip bus (SOC) system.Wherein each DSP moulds
Block is responsible for corresponding signal processing algorithm, such as automatic growth control (AGC), signal timing, radio channel estimation and compensation etc..
Microprocessor controls each DSP module and orderly works according to certain algorithm, is finally completed complicated signal processing flow.Its
Existing major defect is：DSP module complex interfaces, handling capacity is not high, and the system expandability is poor.
Invention content
The purpose of the present invention is to provide a kind of Base-band Processing Systems based on DMA, and unification is provided for DSP module
Interface, realize to greatest extent modularity design, improve the handling capacity of DSP module interface to greatest extent, while can be flexible
Ground increases or deletes DSP module, and scalability is good.
To achieve the above object, the present invention uses following technical scheme：
A kind of Base-band Processing System based on DMA, including high-speed bus, low speed bus, microprocessor, memory, DMA
Unit, routing unit and multiple DSP modules, the high-speed bus are used to provide the height of connection microprocessor, memory, DMA unit
Fast data path, low speed data access of the low speed bus for providing connection microprocessor, DSP module, the DMA unit
Carried out data transmission by routing unit and DSP module.
Preferably, the DMA unit includes multiple DMA Read Controllers and multiple DMA write controllers, and the DMA reads control
Device connects the microprocessor and memory, the DMA Read Controllers and DMA write control with DMA write controller by high-speed bus
Device connects the routing unit.
Preferably, the routing unit includes the first data flow router and the second data flow router, first number
It is separately connected the DMA Read Controllers and DSP module according to stream router, the second data flow router is separately connected described
DMA write controller and DSP module.
Preferably, each DSP module all has a control interface, an input interface and an output and connects
Mouthful, the control interface of the DSP module connects the microprocessor, input interface connection first number by low speed bus
According to stream router, output interface connects the second data flow router.
Preferably, the first data flow router and the second data flow router all have multiple input interface and output
The input interface of interface, the first data flow router connects the DMA Read Controllers, the first data flow router
Output interface connects the input interface of the DSP module, and the input interface of the second data flow router connects the DSP moulds
The output interface of the output interface of block, the second data flow router connects the DMA write controller.
Preferably, further include that signal sends DSP module, the signal send DSP module tool there are one control interface and
One input interface, the control interface that the signal sends DSP module connect the microprocessor by low speed bus, input
Interface connects the output interface of the first data flow router.
Preferably, further include that signal receives DSP module, the signal receive DSP module tool there are one control interface and
One output interface, the control interface that the signal receives DSP module connect the microprocessor by low speed bus, export
Interface connects the input interface of the second data flow router.
Preferably, the memory uses DRAM or sram chip.
After adopting the above technical scheme, compared with the background technology, the present invention, having the following advantages that：
1, the present invention provides unified interface for DSP module, realizes modularized design to greatest extent.
2, the handling capacity for improving DSP module interface to greatest extent, to support a large amount of data interaction.
3, expansible system architecture is constructed, DSP module can be neatly increased or delete.
4, it can realize that dsp bus bandwidth-bus logic resource is exchanged according to the processing data amount of DSP.
Description of the drawings
Fig. 1 is the structural diagram of the present invention；
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Embodiment
Referring to Fig. 1, the invention discloses a kind of Base-band Processing System based on DMA, including it is high-speed bus 1, low
Fast bus 2, DMA unit, routing unit, multiple DSP modules 5, microprocessor 6 and memory 7, wherein：
Refering to what is shown in Fig. 1, high-speed bus 1 is logical for providing connection DMA unit, microprocessor 6, the high-speed data of memory 7
Road.Low speed data access of the low speed bus 2 for providing connection DSP module 5, microprocessor 6.
DMA unit includes multiple DMA Read Controllers 31 and multiple DMA write controllers 32, DMA Read Controllers 31 and DMA write
Controller 32 connects microprocessor 6 and memory 7,32 link road of DMA Read Controllers 31 and DMA write controller by high-speed bus 1
By unit.DMA Read Controllers 31 are used for the data-moving of specified memory 7 to data flow bus；DMA write controller 32 is responsible for
Data on data flow bus are written to 7 designated position of memory.The quantity root of DMA Read Controllers 31 and DMA write controller 32
It is determined according to the total bandwidth need of DSP module 5.The quantity of DMA Read Controllers 31 and DMA write controller 32 is more, can be provided
Total data bandwidth is also bigger, this can realize that the tradeoff of data bandwidth and hardware resource is compromised.
Routing unit is used for the routing of data flow comprising the first data flow router 41 and the second data flow router
42, the first data flow router 41 and the second data flow router 42 all have multiple input interface and output interface.First number
According to the input interface connection DMA Read Controllers 31 of stream router 41, the output interface of the second data flow router 42 connects DMA write
Controller 32.First data flow router 41 and the second data flow router 42 are according to the DAF destination address field of input terminal data flow
Data flow is routed to designated port output, specifically, the first data flow router 41 completion DMA Read Controllers 31 arrive specific
The data distribution of DSP module 5, the second data flow router 42 complete 5 data of multiple DSP modules answering to DMA write controller 32
With.
There are one control interface, an input interface and an output interface, the controls of DSP module 5 to connect for the tool of DSP module 5
Mouth connects microprocessor 6 by low speed bus 2, and input interface connects the output interface of the first data flow router 41, defeated
Outgoing interface connects the input interface of the second data flow router 42.
DSP module 5 is to wirelessly communicate the nucleus module of physical layer signal processing, has the processing operational capability of high speed, it
The hardware module usually write with HDL.The signal processing that multiple DSP modules 5 realize different piece in agreement respectively is calculated
Method, such as automatic growth control (AGC), signal timing, radio channel estimation and compensation etc..
To realize sending and receiving for signal, sends DSP module the invention also includes signal and signal receives DSP module,
Signal sends the transmission that DSP module is responsible for wireless modulated signal, and signal receives the reception that DSP module is responsible for wireless signal.Signal
DSP module tool is sent there are one control interface and an input interface, the control interface that signal sends DSP module is total by low speed
Line 2 connects microprocessor 6, and input interface connects the output interface of the first data flow router 41, and it is same that signal sends DSP module
When additionally provide connection with hardware DAC (D/A converter).Signal receives DSP module tool, and there are one control interface and one
Output interface, the control interface that signal receives DSP module connect microprocessor 6, output interface connection the by low speed bus 2
The input interface of two data flow routers 42, signal receive DSP module and additionally provide and hardware ADC (A/D converter) simultaneously
Connection.
Microprocessor 6 controls DMA Read Controllers 31 and is orderly delivered to specific data for configuring each DSP module 5
Corresponding DSP module 5, completes complicated signal processing flow, while controlling DMA write controller 32 will be after the processing of DSP module 5
Write back data to memory 7, be finally completed complete radio physical layer protocol.In addition to this, microprocessor 6 can also handle other
Necessary affairs.
Memory 7 is used for the data buffer storage before and after signal processing, and DRAM or sram chip can be used, on piece can also be used and deposit
Store up module.
The workflow of the present invention is as follows:
1, upon power-up of the system, microprocessor 6 carries out the self-test of system first, confirms 5 version of each DSP module or work(
It can meet the requirements.Then according to the operating mode of radio physical layer, the register of each DSP module 5 is initialized.
2, microprocessor 6 checks DMA Read Controllers 31 and DMA write controller 32, and is initialized, them is made to be in just
Not-ready status.
3, when system starts, microprocessor 6 starts DMA Read Controllers 31 and DMA write controller 32, and according to physics
Layer protocol dispatches each DSP module 5 and carries out data processing.
By taking transmission link as an example, elaborate to the workflow of present system.First, upper-layer protocol (such as MAC
Agreement) initial data to be sent can be put into memory 7.Then, microprocessor 6 can utilize DMA Read Controllers 31 that will send out
The data sent read in data flow bus, and the DSP module 5 for being responsible for channel coding is sent by the selection of the first data flow router 41
In, be responsible for channel coding DSP module 5 output further through the second data flow router 42 select after, give DMA write controller
32, finally it is written back to memory 7.Then, microprocessor 6 starts DMA Read Controllers 31 by the data just handled well but also feeding not only
The DSP module 5 for being responsible for modulation is modulated, and modulated data give DMA write controller 32 and finally write back memory 7 again.According to
Above-mentioned similar step, is finally completed entire transmission process.
4, when system needs to close or suspend, microprocessor 6 is notified that each DSP module 5, DMA Read Controllers 31
And DMA write controller 32 is stopped, and discharge respective resources.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
Subject to.
Claims (5)
1. a kind of Base-band Processing System based on DMA, it is characterised in that：Including high-speed bus, low speed bus, microprocessor
Device, memory, DMA unit, routing unit and multiple DSP modules, the high-speed bus for provide connection microprocessor, memory,
The high-speed data path of DMA unit, low speed data access of the low speed bus for providing connection microprocessor, DSP module,
The DMA unit is carried out data transmission by routing unit and DSP module；
The DMA unit includes multiple DMA Read Controllers and multiple DMA write controllers, the DMA Read Controllers and DMA write control
Device processed connects the microprocessor and memory by high-speed bus, and the DMA Read Controllers connect the road with DMA write controller
By unit；
The routing unit includes the first data flow router and the second data flow router, the first data flow router point
Do not connect the DMA Read Controllers and DSP module, the second data flow router be separately connected the DMA write controller and
DSP module；
Each DSP module all has a control interface, an input interface and an output interface, the DSP moulds
The control interface of block connects the microprocessor by low speed bus, and input interface connects the first data flow router,
Its output interface connects the second data flow router.
2. a kind of Base-band Processing System based on DMA as described in claim 1, it is characterised in that：First data
Stream router and the second data flow router all have multiple input interface and output interface, the first data flow router
Input interface connects the DMA Read Controllers, and the output interface of the first data flow router connects the defeated of the DSP module
The input interface of incoming interface, the second data flow router connects the output interface of the DSP module, second data flow
The output interface of router connects the DMA write controller.
3. a kind of Base-band Processing System based on DMA as claimed in claim 2, it is characterised in that：It further includes signal
DSP module is sent, the signal sends DSP module tool there are one control interface and an input interface, and the signal sends DSP
The control interface of module connects the microprocessor by low speed bus, and input interface connects the first data flow router
Output interface.
4. a kind of Base-band Processing System based on DMA as claimed in claim 2 or claim 3, it is characterised in that：It further includes letter
Number DSP module is received, the signal receives DSP module tool there are one control interface and an output interface, and the signal receives
The control interface of DSP module connects the microprocessor by low speed bus, and output interface connects second data stream
By the input interface of device.
5. a kind of Base-band Processing System based on DMA as described in claim 1, it is characterised in that：The memory uses
DRAM or sram chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610018298.8A CN105635003B (en) | 2016-01-12 | 2016-01-12 | A kind of Base-band Processing System based on DMA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610018298.8A CN105635003B (en) | 2016-01-12 | 2016-01-12 | A kind of Base-band Processing System based on DMA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105635003A CN105635003A (en) | 2016-06-01 |
| CN105635003B true CN105635003B (en) | 2018-10-23 |
Family
ID=56049513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610018298.8A Active CN105635003B (en) | 2016-01-12 | 2016-01-12 | A kind of Base-band Processing System based on DMA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105635003B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111858436B (en) * | 2020-07-30 | 2021-10-26 | 南京英锐创电子科技有限公司 | Switching circuit for high-speed bus read-write low-speed bus and data read-write equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6434161B1 (en) * | 1998-02-25 | 2002-08-13 | 3Com Corporation | UART with direct memory access buffering of data and method therefor |
| CN102945217A (en) * | 2012-10-11 | 2013-02-27 | 浙江大学 | Triple modular redundancy based satellite-borne comprehensive electronic system |
| CN205304861U (en) * | 2016-01-12 | 2016-06-08 | 陈玉平 | Baseband signal processing system based on DMA |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7739433B2 (en) * | 2008-03-05 | 2010-06-15 | Microchip Technology Incorporated | Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock |
-
2016
- 2016-01-12 CN CN201610018298.8A patent/CN105635003B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6434161B1 (en) * | 1998-02-25 | 2002-08-13 | 3Com Corporation | UART with direct memory access buffering of data and method therefor |
| CN102945217A (en) * | 2012-10-11 | 2013-02-27 | 浙江大学 | Triple modular redundancy based satellite-borne comprehensive electronic system |
| CN205304861U (en) * | 2016-01-12 | 2016-06-08 | 陈玉平 | Baseband signal processing system based on DMA |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的DMA方式高速数据采集系统设计;何琼 等;《电子技术应用（嵌入式技术）》;20111206(第12期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105635003A (en) | 2016-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7028898B2 (en) | Duplicate transmission configuration, duplicate transmission method and equipment | |
| US7965624B2 (en) | Data link fault tolerance | |
| CN101001209B (en) | System for switching variable-length data packets of heterogeneous network and method thereof and method for forming address list using signal loop interface | |
| CN112703488B (en) | Serial interface for semiconductor package | |
| CN101741664A (en) | Method and device for realizing Ethernet interface system | |
| CN103823784A (en) | FC-AE-1553 bus controller based on FPGA | |
| US9515963B2 (en) | Universal network interface controller | |
| KR20100025335A (en) | Data processing system | |
| US20090274131A1 (en) | Method and system for dynamic distribution of traffic in channel bonding wireless local area network(lan) systems | |
| CN103401707A (en) | Link aggregation method and access equipment | |
| US10305825B2 (en) | Bus control device, relay device, and bus system | |
| CN102307141B (en) | Message forwarding method and device | |
| US10342032B2 (en) | Method and device for streaming control data in a mobile communication system | |
| CN101901199B (en) | Method and system for data transparent transmission | |
| CN107852423A (en) | The method and system retained for the bandwidth of USB 2.0 | |
| US10263905B2 (en) | Distributed flexible scheduler for converged traffic | |
| WO2023123905A1 (en) | Data transmission processing method in chip system and related apparatus | |
| CN105635003B (en) | A kind of Base-band Processing System based on DMA | |
| KR100505689B1 (en) | Transceiving network controller providing for common buffer memory allocating corresponding to transceiving flows and method thereof | |
| CN100382009C (en) | Shared queue for multiple input-streams | |
| US9317678B2 (en) | System and method for managing logins in a network interface | |
| CN103428301A (en) | Interface layer and method for processing data packet | |
| CN103812775A (en) | Method, device and system for forwarding messages | |
| CN205304861U (en) | Baseband signal processing system based on DMA | |
| CN104699649A (en) | Multi-branch serial bus interface and data exchange method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180904 Address after: 361000 351, room three, 45 Xixia Road, Siming District, Xiamen, Fujian Applicant after: Ling Tuo Zhi Lian (Xiamen) Network Technology Co., Ltd. Address before: 361010 room 1717, wo Xiang East Road, Siming District, Xiamen, Fujian, 1717 Applicant before: Chen Yuping |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |