CN105634642A - Clock synchronization method and device for EPON (Ethernet Passive Optical Network) system - Google Patents
Clock synchronization method and device for EPON (Ethernet Passive Optical Network) system Download PDFInfo
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- CN105634642A CN105634642A CN201610005829.XA CN201610005829A CN105634642A CN 105634642 A CN105634642 A CN 105634642A CN 201610005829 A CN201610005829 A CN 201610005829A CN 105634642 A CN105634642 A CN 105634642A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
The invention discloses a clock synchronization method and device for an EPON (Ethernet Passive Optical Network) system. The method comprises the following steps: extracting a synchronous Ethernet clock from a gigabit Ethernet optical interface at an OLT (Optical Line Terminal) side; converting the frequency of the synchronous Ethernet clock to obtain a low-speed differential clock meeting the transmission requirement of an OLT backboard; extracting, by each service disk, the low-speed differential clock from the backboard, and performing frequency multiplication to form a PON (Passive Optical Network) system clock used by a PON chip on each service disk; transmitting the PON system clock to an ONU (Optical Network Unit) via an optical path; and extracting, by the PON chip on the ONU, the PON system clock used by a TDM (Time Division Multiplexing) service disk of the ONU side. According to the method and the device, the synchronous Ethernet clock extracted from the synchronous Ethernet (SvncE) is used as a synchronous clock source of the OLT side, so that the input of a specific external hardware clock source is not needed, the category of the OLT synchronous clock source is enriched, the synchronous clock design of the OLT side is simplified, and the cost is lowered.
Description
Technical field
The present invention relates to the clock of EPON system to synchronize, be specifically related to clock synchronizing method and the device of a kind of EPON system.
Background technology
Clock synchronization is the premise of network system normal operation. Whole system is made to reach to synchronize, it is necessary to having a common reference clock, in an epon with local side PON system clock for reference clock, each ONU clock is Tong Bu with PON system clock.
Current EPON system, local side PON system clock is inputted by external clock reference, for instance 1PPS+TOD or IEEE1588V2, and these external clocks are all produced by special hardware device.
Extensive use in view of synchronous ethernet (SvncE), and International Telecommunication Union its G.8261 in issued the IEEE1588 standard relevant to accurate time synchronization protocol (PTP), therefore, synchronous ethernet how is utilized to simplify the local side PON system clock design of EPON system, and then the kind of abundant clock source, reduce system cost, it is current this area urgent problem.
Summary of the invention
The technical problem to be solved is to solve how to utilize synchronous ethernet to simplify the problem that the local side PON system clock of EPON system designs.
In order to solve above-mentioned technical problem, the technical solution adopted in the present invention is to provide the clock synchronizing method of a kind of EPON system, comprises the following steps:
In OLT side, from gigabit Ethernet optical interface, extract synchronous Ethernet clock;
The frequency of described synchronous Ethernet clock is changed so that it is become the low speed differential clocks of applicable OLT backboard transmission requirement;
Each business dish extracts described low speed differential clocks from backboard, and becomes PON system clock for the PON chip on each business dish after carrying out process of frequency multiplication;
PON system clock passes to ONU by light path;
In ONU side, the PON chip on ONU extracts described PON system clock, for the TDM business dish of ONU side.
In the above-mentioned methods, in OLT side, the BCM54240 chip of BCM company is adopted to extract the synchronous Ethernet clock that frequency is 25Mhz from gigabit Ethernet optical interface.
In the above-mentioned methods, adopting the Si5326B chip of SiliconLabs company to complete the conversion of synchronous Ethernet clock frequency, the frequency of the low speed differential clocks being suitable for OLT backboard transmission requirement is 8KHz.
In the above-mentioned methods, the frequency of described PON system clock is 125MHz.
In the above-mentioned methods, described PON system clock is delivered to ONU side by light path after phase-locked loop pll processes.
Present invention also offers the clock synchronization apparatus of a kind of EPON system, including:
Synchronous Ethernet clock extraction unit, arranges in united dish or master control in united dish, extracts the synchronous Ethernet clock in synchronous ethernet from described upper united dish or master control in the optical interface of the gigabit Ethernet in united dish;
Clock frequency converting unit, arranges in united dish or master control in united dish, and the frequency of synchronous Ethernet clock is converted to the low speed differential clocks of applicable OLT backboard transmission requirement;
PON system Clock Extraction unit, is arranged on each business dish, exports PON system clock, for each business dish after the low speed differential clocks frequency multiplication extracted from backboard; Meanwhile, after phase-locked loop pll processes, it is delivered to ONU side by light path.
The present invention, the synchronous Ethernet clock that utilization extracts from synchronous ethernet (SvncE) is as the synchronous clock source of OLT side, it is no longer necessary to the input of specific external hardware clock source, enrich the kind of OLT synchronous clock source, simplify the synchronised clock design of OLT end, reduce cost.
Accompanying drawing explanation
Fig. 1 is the flow chart of the clock synchronizing method of EPON system in the present invention;
Fig. 2 is the schematic diagram extracting synchronous Ethernet clock in the present invention;
Fig. 3 is that in the present invention, business dish obtains low speed differential clocks from backboard and is converted to PON system clock and is simultaneously transferred to the schematic diagram of ONU.
Detailed description of the invention
The invention provides the clock synchronizing method of a kind of EPON system, enrich the kind of OLT synchronous clock source, simplify the synchronised clock design of OLT end. Below in conjunction with specification drawings and specific embodiments, the present invention is described in detail.
Ethernet is current most widely used network technology in the world, has the trend progressively replacing PDH and SONET/SDH transmission network. For the high-precision clock synchronization requirement of Ethernet, up-to-date standard solution is synchronous ethernet (SvncE). In SyncE, Ethernet adopts the mode with SONET (Synchronous Optical Network)/identical for SDH (Synchronous Digital Hierarchy), by high-quality, can follow the tracks of one-level reference clock signal and synchronizes its bit clock. Present latest edition is IEEE1588, i.e. IEEE1588v2. The standards define one at the clock synchronization protocol measured and in automated system, be particularly suitable for Ethernet, it is possible to achieve the high-precision clock of Microsecond grade synchronizes. The present invention program is based on synchronous ethernet (SvncE) and realizes.
As it is shown in figure 1, the clock synchronizing method of EPON system provided by the invention, comprise the following steps:
S110, on OLT side, upper united dish or master control, united dish extracts the synchronous Ethernet clock in synchronous ethernet (SvncE) from gigabit Ethernet optical interface;
S120, frequency to synchronous Ethernet clock are changed so that it is become the low speed differential clocks of applicable OLT backboard transmission requirement;
TDM (time division multiplex) the business dish of plug-in mounting or other business dish on each groove position of S130, OLT backboard, extract low speed differential clocks from backboard, and becomes PON system clock for the PON chip on each business dish after carrying out process of frequency multiplication;
S140, PON system clock export after processing from PON interface chip, pass to ONU through light path;
S150, in ONU side, the PON chip on ONU extracts PON system clock, for the TDM business dish of ONU side, it is achieved thereby that the clock between OLT and ONU synchronizes.
On this basis, present invention also offers the clock synchronization apparatus of a kind of EPON system, this clock synchronization apparatus is arranged on OLT side, including synchronous Ethernet clock extraction unit, clock frequency converting unit and PON system Clock Extraction unit.
That synchronous Ethernet clock extraction unit adopts is BCM (BroadcomCorporation, company of Botong) the BCM54240 chip of company, it is arranged in united dish or master control in united dish, utilizing this chip to extract synchronous Ethernet clock from the optical interface of the gigabit Ethernet in united dish in upper united dish or master control, frequency is 25Mhz.
BCM54240 chip is a 4 mouthfuls of gigabit Ethernet PHY chip, supports IEEE1588v2 agreement, supports the output of two-way synchronous Ethernet clock, and the extraction source of output clock can be any one road in 4 tunnel gigabit ethernet interfaces, it is possible to configured by software.
Clock frequency converting unit completes the conversion of synchronous Ethernet clock frequency, and employing is the Si5326B clock generator of SiliconLabs company, is similarly disposed in united dish or master control in united dish.
Si5326B clock generator is a Jitter Attenuation clock multiplier chip, adopts the doubleclocking input of 2kHz��710MHz, and produces 2 independent frequency doubling clock outputs, and reference frequency output is 2kHz��945MHz. In synchronised clock, main adopt third generation DSPLL technology, it is possible to produce frequency synthesis and the Key dithering at the high velocities of arbitrary ratio.
As shown in Figure 2, when local clock 21 ensures Si5326B chip 22 normal operation, the 25Mhz synchronous Ethernet clock input Si5326B chip 22 that BCM54240 chip 23 provides, after Si5326B chip 22 divides, exporting a road at its output port and be suitable for the low speed differential clocks of backboard 24 transmission, clock frequency is 8KHz.
PON system Clock Extraction unit realizes the extraction of PON system clock, for the TDM dish on OLT or other business dish. PON system Clock Extraction unit adopts zl30142 Clock Extraction chip to realize. This chip is 3 grades of clock chips, adopts the clock input of 8kHz��77.76MHz, could support up 6 road clock inputs, and SONET/SDH clock and ethernet clock are supported in clock output, and the present invention selects ethernet clock to export. According to PON chip demand, amendment chip configuration, it is configured to the output of 125Mhz clock, for PON chip.
As shown in Figure 3, when local clock 31 ensures zl30142 chip 32 normal operation, backboard 33 provides the synchronous Ethernet clock of 8Khz to input to zl30142 chip 32, after zl30142 chip 32 frequency multiplication, the PON system clock of 125MHz is exported, for the TDM dish on OLT or other business dish at its output port.
Simultaneously, BCM55524 chip 34 on OLT by PON system clock through phase-locked loop pll process after, it is delivered to ONU side by light path, PON system clock (synchronous Ethernet clock) is extracted by PON chip on ONU again, the TDM business dish giving ONU side uses, it is achieved thereby that the clock between OLT and ONU synchronizes.
The present invention, ethernet clock in synchronous ethernet is extracted, the system clock of System Backplane transmission is become suitable for through oversampling clock conversion, in business groove position, the work clock that EPON system chip needs is converted to by clock recovery chip zlk30143, process conversion then through the PON interface chip on OLT is sent to optical network unit (ONU equipment) by optical fiber, in ONU side by the PON chip on ONU, system clock is extracted, it is achieved thereby that the clock of EPON system synchronizes.
The present invention, changes tradition and is directly provided the design of synchronous clock source by external equipment, it is not necessary to provide external clock reference, synchronous clock source can in the optical path signal of backbone local area network extracting directly, and but can accomplish the clock homology with backbone local area network.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structure change made under the enlightenment of the present invention, and every have same or like technical scheme with the present invention, each falls within protection scope of the present invention.
Claims (6)
- The clock synchronizing method of 1.EPON system, it is characterised in that comprise the following steps:In OLT side, from gigabit Ethernet optical interface, extract synchronous Ethernet clock;The frequency of described synchronous Ethernet clock is changed so that it is become the low speed differential clocks of applicable OLT backboard transmission requirement;Each business dish extracts described low speed differential clocks from backboard, and becomes PON system clock for the PON chip on each business dish after carrying out process of frequency multiplication;PON system clock passes to ONU by light path;In ONU side, the PON chip on ONU extracts described PON system clock, for the TDM business dish of ONU side.
- 2. the clock synchronizing method of EPON system as claimed in claim 1, it is characterised in that in OLT side, adopts the BCM54240 chip of BCM company to extract the synchronous Ethernet clock that frequency is 25Mhz from gigabit Ethernet optical interface.
- 3. the clock synchronizing method of EPON system as claimed in claim 1, it is characterized in that, the Si5326B chip adopting SiliconLabs company completes the conversion of synchronous Ethernet clock frequency, and the frequency of the low speed differential clocks being suitable for OLT backboard transmission requirement is 8KHz.
- 4. the clock synchronizing method of EPON system as claimed in claim 1, it is characterised in that the frequency of described PON system clock is 125MHz.
- 5. the clock synchronizing method of EPON system as claimed in claim 1, it is characterised in that described PON system clock is delivered to ONU side by light path after phase-locked loop pll processes.
- The clock synchronization apparatus of 6.EPON system, it is characterised in that including:Synchronous Ethernet clock extraction unit, arranges in united dish or master control in united dish, extracts the synchronous Ethernet clock in synchronous ethernet from described upper united dish or master control in the optical interface of the gigabit Ethernet in united dish;Clock frequency converting unit, arranges in united dish or master control in united dish, and the frequency of synchronous Ethernet clock is converted to the low speed differential clocks of applicable OLT backboard transmission requirement;PON system Clock Extraction unit, is arranged on each business dish, exports PON system clock, for each business dish after the low speed differential clocks frequency multiplication extracted from backboard; Meanwhile, after phase-locked loop pll processes, it is delivered to ONU side by light path.
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| CN201610005829.XA CN105634642A (en) | 2016-01-06 | 2016-01-06 | Clock synchronization method and device for EPON (Ethernet Passive Optical Network) system |
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Cited By (2)
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| CN110601787A (en) * | 2019-10-16 | 2019-12-20 | 深圳市友华通信技术有限公司 | OLT (optical line terminal) equipment and clock synchronization method thereof |
| CN111865464A (en) * | 2020-06-30 | 2020-10-30 | 烽火通信科技股份有限公司 | Automatic mounting method and device for multi-slot communication system clock channel |
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| CN102412923A (en) * | 2011-11-18 | 2012-04-11 | 烽火通信科技股份有限公司 | Method for realizing clock synchronization between optical line terminal (OLT) and optical network unit (ONU) in Ethernet-based passive optical network (EPON) system |
| WO2015010250A1 (en) * | 2013-07-23 | 2015-01-29 | Telefonaktiebolaget L M Ericsson (Publ) | Clock recovery in a packet based network |
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| CN101630988A (en) * | 2008-07-14 | 2010-01-20 | 华为技术有限公司 | Method, device and system for transferring synchronous clock |
| CN101741539A (en) * | 2008-11-14 | 2010-06-16 | 中兴通讯股份有限公司 | Method and system for implementing synchronous Ethernet based on clock recovery and public reference sources |
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| CN110601787A (en) * | 2019-10-16 | 2019-12-20 | 深圳市友华通信技术有限公司 | OLT (optical line terminal) equipment and clock synchronization method thereof |
| CN111865464A (en) * | 2020-06-30 | 2020-10-30 | 烽火通信科技股份有限公司 | Automatic mounting method and device for multi-slot communication system clock channel |
| CN111865464B (en) * | 2020-06-30 | 2022-03-01 | 烽火通信科技股份有限公司 | Automatic mounting method and device for multi-slot communication system clock channel |
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Application publication date: 20160601 |