CN105633154A - Transistor and forming method therefor - Google Patents
Transistor and forming method therefor Download PDFInfo
- Publication number
- CN105633154A CN105633154A CN201410696596.3A CN201410696596A CN105633154A CN 105633154 A CN105633154 A CN 105633154A CN 201410696596 A CN201410696596 A CN 201410696596A CN 105633154 A CN105633154 A CN 105633154A
- Authority
- CN
- China
- Prior art keywords
- ion
- breakdown
- layer
- forming method
- transistor according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a transistor and a forming method therefor. The forming method for the transistor comprises the steps of providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming grooves in the semiconductor substrate on two sides of the gate structure; forming an anti-breakdown layer on a side wall, close to one side of the gate structure, of any groove; and forming a source and a drain in the grooves. According to the method, the performance of the formed transistor can be improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to a kind of transistor and forming method thereof.
Background technology
Transistor is the most basic element in semiconductor manufacturing, and it is widely used in various integrated circuit. Transistor is generally symmetrical structure, specifically includes that the grid structure being positioned at semiconductor substrate surface, is positioned at source electrode and the drain electrode of the Semiconductor substrate of grid structure both sides. Wherein source electrode and drain electrode are by highly doped formation, different according to type of device, can be divided into n-type doping and the doping of P type.
Along with the development of semiconductor technology, integrated circuit integration degree is more and more higher, and the current densities of IC interior is increasing, and the number of elements comprised also gets more and more, and the size of semiconductor element also reduces therewith. But the continuous reduction of device size can cause that the performance of device is also affected by very big impact. Such as, when raceway groove length reduction to a certain extent, transistor starts to show short-channel effect, for instance: problem such as (DIBL) that carrier mobility declines, threshold voltage increases and drain-induced barrier declines. Owing to the source electrode of transistor easily carries out horizontal proliferation with the dopant ion in drain electrode in channel region, causing that the lateral breakdown voltage of transistor reduces, under drain-induced barrier, degradation problem is also more notable. And along with transistor size is more little, the problems referred to above are more notable.
Therefore, the performance of the transistor that prior art is formed needs further to be improved.
Summary of the invention
The problem that this invention address that is to provide a kind of transistor and forming method thereof, improves the performance of the transistor formed.
For solving the problems referred to above, the present invention provides the forming method of a kind of transistor, including: Semiconductor substrate is provided; Form grid structure on the semiconductor substrate; Groove is formed in the Semiconductor substrate of described grid structure both sides; Anti-breakdown layer is formed at arbitrary groove sidewall near grid structure side; Source-drain electrode is formed in described groove.
Optionally, also include: while forming described anti-breakdown layer, formed and assist anti-breakdown layer; The anti-breakdown layer of wherein said auxiliary lays respectively in relative groove with anti-breakdown layer and the described anti-breakdown layer of auxiliary is positioned at the groove sidewall away from grid structure side.
Optionally, the method forming described anti-breakdown layer includes: described recess sidewall carries out anti-breakdown ion implanting, forms ion implanted layer; Described ion implanted layer is carried out baking process, forms anti-breakdown layer.
Optionally, the mol ratio of the atom of the anti-breakdown ion in described anti-breakdown layer and semiconductor substrate materials is 0.01��0.05, and the thickness of described anti-breakdown layer is 2nm��50nm.
Optionally, described anti-breakdown ion includes carbon ion, Nitrogen ion, fluorion or germanium ion.
Optionally, the Implantation Energy of described carbon ion is 0.5keV��10keV, and dosage is 1e14atom/cm2��1e15atom/cm2, implant angle is 15 �㡫45 ��.
Optionally, described baking processes and adopts furnace anneal or spike annealing process, and the temperature of described furnace anneal is 800 DEG C��900 DEG C, and the time is 10min��30min, and the temperature of described spike annealing is 950 DEG C��1100 DEG C, and the time is 5s��30s. .
Optionally, being additionally included in after carrying out anti-breakdown ion implanting, carry out N plasma injection, the injection degree of depth is 5nm��50nm, and implantation concentration is 1e19atom/cm3��1e20atom/cm3, energy is 1keV��12keV, and implant angle is 15 �㡫45 ��.
Optionally, the section of described groove is U-shaped, inverted trapezoidal or �� shape.
Optionally, described Semiconductor substrate is silicon-on-insulator substrate, including bottom silicon layer, is positioned at the insulating barrier of bottom silicon surface, is positioned at the top silicon layer of surface of insulating layer.
Optionally, the bottom of described groove is positioned at surface of insulating layer.
Optionally, the forming method of described source-drain electrode includes: form the stressor layers filling full described groove, described stressor layers is carried out dopant ion injection.
Optionally, the material of described stressor layers is SiGe, SiSn or SiC.
Optionally, selective epitaxial process is adopted to form described stressor layers.
Optionally, when the material of described stressor layers is SiGe, the temperature of described selective epitaxial process is 600 DEG C��800 DEG C, and in described stressor layers, the mol ratio of Ge and Si is 0.1��0.45.
Optionally, when the material of described stressor layers is SiC, the temperature of described selective epitaxial process is 680 DEG C��800 DEG C, and in described stressor layers, the mol ratio of C and Si is 0.01��0.05.
Optionally, described grid structure includes: is positioned at the gate dielectric layer of semiconductor substrate surface and is positioned at the grid on gate dielectric layer surface.
Optionally, described grid structure also includes the side wall that is positioned at gate dielectric layer and gate lateral wall surface.
For solving the problems referred to above, the present invention also provides for a kind of transistor adopting said method to be formed, including: Semiconductor substrate; It is positioned at the grid structure in described Semiconductor substrate; It is positioned at the groove of the Semiconductor substrate of described grid structure both sides; It is positioned at the anti-breakdown layer of arbitrary groove sidewall near grid structure side; It is positioned at the source-drain electrode of described groove.
Optionally, having anti-breakdown ion in described anti-breakdown layer, the mol ratio of the atom that described anti-breakdown ion includes carbon ion, Nitrogen ion, fluorion or germanium ion, described anti-breakdown ion and semiconductor substrate materials is 0.01��0.05.
Compared with prior art, technical scheme has the advantage that
In the forming method of the transistor of the present invention, first grid structure is formed at semiconductor substrate surface, then in the Semiconductor substrate of grid structure both sides, form groove, in the sidewall of the close grid structure side of arbitrary groove, form anti-breakdown layer again, in described groove, then form source-drain electrode again. Described anti-breakdown layer has higher breakdown voltage, it is possible to increase the lateral breakdown voltage between source electrode and the drain electrode of transistor, thus improving the performance of transistor.
Further, the forming method of described anti-breakdown layer includes: described recess sidewall carries out anti-breakdown ion implanting, forms ion implanted layer; Described ion implanted layer is carried out baking process, forms anti-breakdown layer. By controlling the injection parameter of anti-breakdown ion implanting, it is possible to adjust doping content and the degree of depth of described anti-breakdown layer, thus adjusting the breakdown voltage of described anti-breakdown layer.
Accompanying drawing explanation
Fig. 1 to Fig. 5, Figure 10, Figure 11 are the structural representations of the forming process of the transistor of embodiments of the invention;
Fig. 6 to Fig. 9 is the comparison diagram of the electrology characteristic of Si and the 4H-SiC of same size.
Detailed description of the invention
As described in the background art, the performance of the transistor that prior art is formed needs further to be improved.
Horizontal proliferation due to the dopant ion in the source drain of transistor, it is easy to cause that the breakdown voltage of transistor declines, degradation problem under drain-induced barrier, affect the performance of transistor.
In embodiments of the invention, groove is formed in the Semiconductor substrate of grid structure both sides, then in the sidewall of grid structure side, anti-breakdown layer is formed at arbitrary groove, then in described groove, form source-drain electrode again, so that described anti-breakdown layer is between the channel region and the source-drain electrode of channel region side of transistor, improve the breakdown voltage of transistor, thus improving the performance of transistor.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Refer to Fig. 1, it is provided that Semiconductor substrate 100.
Described Semiconductor substrate 100 is silicon substrate, silicon-Germanium substrate, silicon-on-insulator substrate one therein. In the present embodiment, described Semiconductor substrate 100 is silicon substrate. Those skilled in the art can select the type of described Semiconductor substrate 100 according to semiconductor device to be formed, and therefore the type of described Semiconductor substrate should too not limit the scope of the invention.
In the present embodiment, described Semiconductor substrate 100 is silicon-on-insulator substrate, including bottom silicon layer 101, is positioned at the insulating barrier 102 on bottom silicon layer 101 surface and is positioned at the top silicon layer 103 on insulating barrier 102 surface.
Refer to Fig. 2, form grid structure in described Semiconductor substrate 100, described grid structure includes: is positioned at the gate dielectric layer 201 on part semiconductor substrate 100 surface and is positioned at the grid 202 on described gate dielectric layer 201 surface.
The material of described gate dielectric layer 201 is silicon oxide or high K dielectric material, for instance hafnium oxide, zirconium oxide etc., and the material of described grid 202 is the material such as polysilicon or metal of polysilicon, doping.
The method forming described grid structure includes: sequentially forms gate dielectric material layer in described Semiconductor substrate 100 and is positioned at the gate material layers on gate dielectric material layer surface; Form Patterned masking layer on described gate material layers surface, described Patterned masking layer has opening, and described opening exposes the surface of some gate material, limits size and the position of grid structure; Along described opening etching grid material layer and gate dielectric material layer, forming grid structure, described grid structure includes gate dielectric layer 201 and grid 202.
In the present embodiment, described grid structure also includes the side wall 203 being positioned at gate dielectric layer 201 and grid 202 sidewall surfaces. The material of described side wall 203 can be silicon oxide and silicon nitride, it is possible to protects described grid 202 and gate dielectric layer 201 in subsequent technique.
Refer to Fig. 3, in the Semiconductor substrate 100 of described grid structure both sides, form groove 301.
The section of described groove 301 can be the different shape such as U-shaped, inverted trapezoidal or �� shape, and in the present embodiment, the section shape of described groove 301 is inverted trapezoidal.
Dry etch process can be adopted to form described groove 301, and concrete, the etching gas that described dry etch process adopts includes Cl2��CCl2F2, the halogen-containing element such as HBr or HCl gas. In the present embodiment, adopt HBr and Cl2Mixing gas as etching gas, O2As buffer gas, wherein the flow of HBr is 50sccm��1000sccm, Cl2Flow be 50sccm��1000sccm, O2Flow be 5sccm��20sccm, pressure is 5mTorr��50mTorr, and power is 400W��750W, O2Gas flow be 5sccm��20sccm, temperature is 40 DEG C��80 DEG C, and bias voltage is 100V��250V.
In other embodiments of the invention, it is possible to after first forming, in the Semiconductor substrate 100 of described grid structure both sides, the groove that sidewall is vertical, described recess sidewall is carried out chemical gaseous phase etching, adopt Cl2��CCl2F2, the gas such as HBr or HCl perform etching, owing to the gas concentration of groove top contact is relatively big, thus it is possible to form inverted trapezoidal groove 301 wide at the top and narrow at the bottom. In the present embodiment, the bottom of described groove 301 is positioned at insulating barrier 102 surface.
Described inverted trapezoidal groove 301 part is positioned at below grid structure, it is possible to reduce follow-up formed in groove 301 source electrode, distance between drain electrode and the channel region of transistor, improve described source electrode, the drain electrode stress effect to channel region.
In other embodiments of the invention, anisotropic etch process can be adopted, form the U-shaped groove 301 that sidewall is vertical, or adopt anisotropic wet-etching technology further U-shaped groove to be performed etching after forming U-shaped groove, form the groove 301 of �� shape.
Follow-up can form stress material in described groove 301, as source electrode and drain electrode, the channel region of transistor be applied stress, improving the mobility of the carrier of transistor, thus improving the performance of transistor.
Refer to Fig. 4, in the sidewall of grid structure side, form anti-breakdown ion implanted layer 302 at arbitrary groove 301.
Described anti-breakdown ion can include one or more in carbon ion, Nitrogen ion, fluorion or germanium ion, and described anti-breakdown ion can improve the breakdown voltage of the ion implanted layer 302 of formation.
In the present embodiment, described anti-breakdown ion is carbon ion, and the Implantation Energy of described carbon ion is 0.5keV��10keV, and dosage is 1e14atom/cm2��1e15atom/cm2Implant angle is 15 �㡫45 ��, the injection degree of depth is 5nm��30nm, in the present embodiment, arbitrary groove 301 sidewall near grid structure side is carried out anti-breakdown ion implanting, the side making the channel region below described grid structure forms described ion implanted layer 302, simultaneously because the groove 301 of grid structure opposite side does not block, described anti-breakdown ion implanting simultaneously can form assisting ion implanted layer 302a at the groove of opposite side away from the side sidewall of grid structure. By the state modulator of ion implanting, it is possible to doping content and thickness to ion implanted layer 302 and assisting ion implanted layer 302a are adjusted, thus adjusting the breakdown voltage of the anti-breakdown layer ultimately formed. And the dopant ion in described assisting ion implanted layer 302a can suppress the diffusion of dopant ion, thus enough suppressing the dopant ion in the follow-up source-drain electrode formed in groove 301 to affect the resistance of source-drain electrode to external diffusion.
Anti-breakdown ion and the mol ratio of silicon in described ion implanted layer 302 and assisting ion implanted layer 302a are 0.01��0.05, and the thickness of described ion implanted layer 302 and assisting ion implanted layer 302a is 5nm��30nm.
In other embodiments of the invention, mask layer can also will be formed in the Semiconductor substrate 100 of grid structure side and in groove 301, then side sidewall close to grid structure in the groove 301 of opposite side is carried out anti-breakdown ion implanting, make only to be formed in channel region side described ion implanted layer 302, then remove described mask layer again. The material of described mask layer can be photoresist or other mask materials.
The breakdown voltage of described ion implanted layer 302 improves, such that it is able to the breakdown voltage improved between transistor source and drain electrode, improves the performance of transistor, simultaneously, owing to the doping content in described ion implanted layer 302 improves, the carrier mobility in channel region can be reduced, in the present embodiment, owing to only arbitrary groove of grid structure both sides being formed ion implanted layer 302 in the sidewall of grid structure side, so described ion implanted layer 302 can only formed in transistor channel region side, the mobility of channel region carriers is affected little, compared with all forming ion implanted layer with in channel region both sides, can avoid the mobility of the carrier in channel region is caused large effect, and the performance of transistor is exerted an adverse impact.
In other embodiments of the invention, after carrying out anti-breakdown ion implanting, it is also possible to described ion implanted layer 302 carries out N plasma injection again, and the injection degree of depth of described N ion is 5nm��50nm, and implantation concentration is 1e19atom/cm3��1e20atom/cm3, energy is 1keV��12keV, and implant angle is 15 �㡫45 ��. Described N ion implanting can form the ion cluster suppressing the diffusion of the dopant ion such as boron and phosphonium ion, thus suppressing the dopant ion in the source electrode being subsequently formed and drain electrode to the horizontal proliferation of channel region, thus suppressing Punchthrough effect, improves the performance of transistor.
Refer to Fig. 5, described ion implanted layer 302 (with reference to Fig. 4) is carried out baking process, forms anti-breakdown layer 303.
Described baking processes the dopant ion that can activate in described anti-breakdown layer 303, can repair the damage that described Semiconductor substrate 100 is caused by ion implanting simultaneously, reduces described ion implanted layer 302 and the interface damage on the interface of top silicon layer 103.
Described baking processes the furnace process that temperature can be adopted relatively low, and temperature is 800 DEG C��900 DEG C, and the time is 10min��30min, and described low temperature bakees can avoid high temperature that other regions of transistor are had undesirable effect.
Described baking processes can also adopt the spike annealing process that temperature is higher, and temperature is 950 DEG C��1100 DEG C, and the time is 5s��30s, and annealing time is shorter, it is possible to improve efficiency.
In the present embodiment, after carrying out baking process, there is diffusion further in the injection ion in described ion implanted layer 302 and assisting ion implanted layer 302a, form described anti-breakdown layer 303 and assist anti-breakdown layer 303a, the mol ratio of the anti-breakdown ion in described anti-breakdown layer 303 is 0.01��0.05, and the thickness of described anti-breakdown layer 303 is 2nm��50nm. Described anti-breakdown ion concentration and thickness can not be too big, to avoid the carrier mobility of channel region is caused large effect. And described anti-breakdown layer 303 thickness is between 2nm��50nm, the raising of breakdown voltage can be played preferably effect. Anti-breakdown ion in the anti-breakdown layer of described auxiliary 303 can suppress the diffusion of dopant ion such that it is able to suppresses dopant ion in the source-drain electrode that is subsequently formed to external diffusion, it is to avoid the resistance of source-drain electrode increases.
Fig. 6 to Fig. 9 is the comparison diagram of the electrology characteristic parameter of Si and the 4H-SiC of same size, wherein the SiC of 4H-SiC to be the cycle be hexagonal lattice structure that the atom solid matter of 4 layers formed, and the performance of described 4H-SiC can represent the performance of the SiC of other structures.
Refer to Fig. 6, for the relation comparison diagram that the impact ionization coefficient of Si and 4H-SiC changes with electric field intensity. Wherein, impact ionization coefficient is more big, it was shown that the ionization by collision intensity in Si or 4H-SiC is more big, more is susceptible to puncture. Wherein, dotted line is the datagraphic calculated by mathematical model. As shown in Figure 6, when identical impact ionization coefficient, the electric field intensity that 4H-SiC needs is more than the Si electric field intensity needed, and need the voltage strength being applied to 4H-SiC two ends accordingly more than the voltage needing to be applied to Si two ends, such that it is able to show that 4H-SiC and Si compares, more difficult puncture.
Refer to Fig. 7, for the relation comparison diagram that the breakdown voltage of Si and 4H-SiC changes with doping content.
It can be seen from figure 7 that when identical doping content, the breakdown voltage of the 4H-SiC breakdown voltage more than Si.
Refer to Fig. 8, puncture, for Si and 4H-SiC, the relation comparison diagram that crucial electric field intensity changes with doping content.
When identical doping content, crucial electric field intensity when crucial electric field intensity when 4H-SiC punctures punctures more than Si, thus, it is applied to the breakdown voltage more than Si of the breakdown voltage on 4H-SiC.
Refer to Fig. 9, for the relation comparison diagram between opening resistor and the breakdown voltage of Si and 4H-SiC.
Described opening resistor is resistance during Si or 4H-SiC forward conduction. When same breakdown voltage, the forward conduction resistance of 4H-SiC is less, and more favourable and transistor performance improves.
Be can be seen that by Fig. 6 to Fig. 9, the breakdown voltage of the SiC breakdown voltage more than Si, thus in embodiments of the invention, the described anti-breakdown layer 303 (refer to Fig. 5) of formation can be effectively improved the breakdown voltage of transistor, thus improving the performance of transistor.
Refer to Figure 10, in described groove 301 (refer to Fig. 5), form stressor layers 400.
The top silicon layer 103 of groove 301 both sides can be provided stress effect by described stressor layers 400, improves the carrier mobility of the channel region of transistor, thus improving the performance of transistor.
When transistor to be formed is P-type transistor, the material of described stressor layers 400 is SiGe or SiSn, it is possible to channel region is applied compressive stress, improves the hole mobility in channel region; When transistor to be formed is N-type transistor, the material of described stressor layers 400 is SiC, it is possible to channel region is applied tensile stress, improves the electron mobility in channel region.
Selective epitaxial process can be adopted to form described stressor layers 400 at described groove 301.
In the present embodiment, described transistor to be formed is P-type transistor, and the material of described stressor layers 400 is SiGe, concrete, and the reacting gas that described selective epitaxial process adopts includes ge source gas, silicon source gas, HCl and H2, wherein, ge source gas is GeH4, silicon source gas includes SiH4Or SiH2Cl2Deng silicon-containing gas, the gas flow of ge source gas, silicon source gas and HCl is 1sccm��1000sccm, H2Flow be 0.1slm��50slm, the temperature of described selective epitaxial is 600 DEG C��800 DEG C, and in described stressor layers 400, the mol ratio of Ge and Si is 0.1��0.45.
In other embodiments of the invention, when the material of described stressor layers 400 is SiC, the epitaxial gas of the selective epitaxial process employing forming described SiC stressor layers 400 includes: carbon-source gas, silicon source gas, HCl and H2, wherein, carbon-source gas is CH4, silicon source gas includes SiH4Or SiH2Cl2Deng silicon-containing gas, the gas flow of carbon-source gas, silicon source gas and HCl is 1sccm��1000sccm, H2Flow be 0.1slm��50slm, temperature is 680 DEG C��800 DEG C, and in described stressor layers 400, the mol ratio of C and Si is 0.01��0.05.
Refer to Figure 11, described stressor layers 400 (refer to Figure 10) is carried out dopant ion injection, forms source-drain electrode respectively in grid structure both sides. Described source-drain electrode includes the source electrode 401 and the drain electrode 402 that lay respectively at grid structure both sides.
The injection of described dopant ion can include light dopant ion and inject, and pocket ion implanting and heavy doping ion are injected. Wherein, described light dopant ion injects consistent with the type of transistor to be formed with the type of the dopant ion of heavy doping ion injection employing; The dopant ion type of pocket ion implanting is contrary with the type of transistor to be formed.
In one embodiment of the invention, first after described stressor layers 400 being carried out light dopant ion injection, proceed pocket ion implanting, then after described side wall 203 surface forms isolation side walls again, again described stressor layers 400 is carried out heavy doping ion injection, forming described source electrode 401 and drain electrode 402, described light dopant ion injects and pocket ion implanting, it is possible to improve the short-channel effect of transistor. The thickness of described isolation side walls is for limiting the distance between heavy doping ion injection region and channel region.
In sum, in embodiments of the invention, groove is formed in the Semiconductor substrate of grid structure both sides, then anti-breakdown layer is formed at arbitrary groove sidewall near grid structure side, described anti-breakdown layer has higher breakdown voltage, then in described groove, form source-drain electrode, make described anti-breakdown layer channel region below the grid structure of transistor and between the source-drain electrode of described channel region side, can improve transistor grid structure both sides source-drain electrode between lateral breakdown voltage, improve drain induced barrier decline problem simultaneously, thus improving the performance of transistor.
Embodiments of the invention also provide for a kind of transistor adopting said method to be formed.
Refer to Figure 11, described transistor includes: Semiconductor substrate 100; It is positioned at the grid structure in described Semiconductor substrate 100; It is positioned at the groove of the Semiconductor substrate 100 of described grid structure both sides; It is positioned at the anti-breakdown layer 303 of arbitrary groove sidewall near grid structure side; Being positioned at the source-drain electrode of described groove, described source-drain electrode includes the source electrode 401 and the drain electrode 402 that lay respectively at grid structure both sides.
Described Semiconductor substrate 100 is silicon substrate, silicon-Germanium substrate, silicon-on-insulator substrate one therein. In the present embodiment, described Semiconductor substrate 100 is silicon substrate. Those skilled in the art can select the type of described Semiconductor substrate 100 according to semiconductor device to be formed, and therefore the type of described Semiconductor substrate should too not limit the scope of the invention.
In the present embodiment, described Semiconductor substrate 100 is silicon-on-insulator substrate, including bottom silicon layer 101, is positioned at the insulating barrier 102 on bottom silicon layer 101 surface and is positioned at the top silicon layer 103 on insulating barrier 102 surface.
The section of described groove can be the different shape such as U-shaped, inverted trapezoidal or �� shape, and in the present embodiment, the section shape of described groove is inverted trapezoidal.
Having anti-breakdown ion in described anti-breakdown layer 303, described anti-breakdown ion includes one or more in carbon ion, Nitrogen ion, fluorion or germanium ion. In the present embodiment, described anti-breakdown ion is carbon ion, and the mol ratio of the atom silicon of described anti-breakdown ion and semiconductor substrate materials is 0.01��0.05, and the thickness of described anti-breakdown layer 303 is 2nm��50nm.
In the present embodiment, in another groove relative with the groove being formed with described anti-breakdown layer 303, sidewall away from grid structure side is formed with the anti-breakdown layer 303a of auxiliary, also having anti-breakdown ion in described auxiliary anti-breakdown layer 303a, the anti-breakdown layer 303a of described auxiliary can stop that dopant ion in source-drain electrode is to external diffusion.
When transistor to be formed is P-type transistor, the material of described source electrode 401 and drain electrode 402 is SiGe or SiSn, it is possible to channel region is applied compressive stress, improves the hole mobility in channel region; When transistor to be formed is N-type transistor, the material of described source electrode 401 and drain electrode 402 is SiC, it is possible to channel region is applied tensile stress, improves the electron mobility in channel region. In described source electrode 401 and drain electrode 402, there is dopant ion.
Described anti-breakdown layer 303 has higher breakdown voltage, it is possible to increase the lateral breakdown voltage between source electrode 401 and drain electrode 302, improves leakage to potential barrier decline problem, thus improving the performance of transistor simultaneously.
Although present disclosure is as above, but the present invention is not limited to this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a transistor, it is characterised in that including:
Semiconductor substrate is provided;
Form grid structure on the semiconductor substrate;
Groove is formed in the Semiconductor substrate of described grid structure both sides;
In the sidewall of grid structure side, anti-breakdown layer is formed at arbitrary groove;
Source-drain electrode is formed in described groove.
2. the forming method of transistor according to claim 1, it is characterised in that also include: while forming described anti-breakdown layer, is formed and assists anti-breakdown layer; The anti-breakdown layer of wherein said auxiliary lays respectively in relative groove with anti-breakdown layer and the described anti-breakdown layer of auxiliary is positioned at the groove sidewall away from grid structure side.
3. the forming method of transistor according to claim 1, it is characterised in that the method forming described anti-breakdown layer includes: described recess sidewall carries out anti-breakdown ion implanting, forms ion implanted layer; Described ion implanted layer is carried out baking process, forms anti-breakdown layer.
4. the forming method of transistor according to claim 3, it is characterised in that the mol ratio of the atom of described anti-breakdown ion and semiconductor substrate materials is 0.01��0.05, and the thickness of described anti-breakdown layer is 2nm��50nm.
5. the forming method of transistor according to claim 4, it is characterised in that described anti-breakdown ion includes carbon ion, Nitrogen ion, fluorion or germanium ion.
6. the forming method of transistor according to claim 5, it is characterised in that the Implantation Energy of described carbon ion is 0.5keV��10keV, dosage is 1e14atom/cm2��1e15atom/cm2, implant angle is 15 �㡫45 ��.
7. the forming method of transistor according to claim 3, it is characterized in that, described baking processes and adopts furnace anneal or spike annealing process, the temperature of described furnace anneal is 800 DEG C��900 DEG C, time is 10min��30min, the temperature of described spike annealing is 950 DEG C��1100 DEG C, and the time is 5s��30s.
8. the forming method of transistor according to claim 3, it is characterised in that be additionally included in after carrying out anti-breakdown ion implanting, carries out N plasma injection, and the injection degree of depth is 5nm��50nm, and implantation concentration is 1e19atom/cm3��1e20atom/cm3, energy is 1keV��12keV, and implant angle is 15 �㡫45 ��.
9. the forming method of transistor according to claim 1, it is characterised in that the section of described groove is U-shaped, inverted trapezoidal or �� shape.
10. the forming method of transistor according to claim 1, it is characterised in that described Semiconductor substrate is silicon-on-insulator substrate, including bottom silicon layer, is positioned at the insulating barrier of bottom silicon surface, is positioned at the top silicon layer of surface of insulating layer.
11. the forming method of transistor according to claim 10, it is characterised in that the bottom of described groove is positioned at surface of insulating layer.
12. the forming method of transistor according to claim 1, it is characterised in that the forming method of described source-drain electrode includes: form the stressor layers filling full described groove, described stressor layers is carried out dopant ion injection.
13. the forming method of transistor according to claim 12, it is characterised in that the material of described stressor layers is SiGe, SiSn or SiC.
14. the forming method of transistor according to claim 13, it is characterised in that adopt selective epitaxial process to form described stressor layers.
15. the forming method of transistor according to claim 13, it is characterised in that when the material of described stressor layers is SiGe, the temperature of described selective epitaxial process is 600 DEG C��800 DEG C, and in described stressor layers, the mol ratio of Ge and Si is 0.1��0.45.
16. the forming method of transistor according to claim 13, it is characterised in that when the material of described stressor layers is SiC, the temperature of described selective epitaxial process is 680 DEG C��800 DEG C, and in described stressor layers, the mol ratio of C and Si is 0.01��0.05.
17. the forming method of transistor according to claim 1, it is characterised in that described grid structure includes: be positioned at the gate dielectric layer of semiconductor substrate surface and be positioned at the grid on gate dielectric layer surface.
18. the forming method of transistor according to claim 17, it is characterised in that described grid structure also includes the side wall being positioned at gate dielectric layer and gate lateral wall surface.
19. the transistor that the forming method of the transistor according to any claim in claim 1 to 18 is formed, it is characterised in that including:
Semiconductor substrate;
It is positioned at the grid structure in described Semiconductor substrate;
It is positioned at the groove of the Semiconductor substrate of described grid structure both sides;
It is positioned at the anti-breakdown layer of arbitrary groove sidewall near grid structure side;
It is positioned at the source-drain electrode of described groove.
20. transistor according to claim 19, it is characterized in that, having anti-breakdown ion in described anti-breakdown layer, the mol ratio of the atom that described anti-breakdown ion includes carbon ion, Nitrogen ion, fluorion or germanium ion, described anti-breakdown ion and semiconductor substrate materials is 0.01��0.05.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410696596.3A CN105633154B (en) | 2014-11-26 | 2014-11-26 | Transistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410696596.3A CN105633154B (en) | 2014-11-26 | 2014-11-26 | Transistor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105633154A true CN105633154A (en) | 2016-06-01 |
| CN105633154B CN105633154B (en) | 2020-04-21 |
Family
ID=56047895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410696596.3A Active CN105633154B (en) | 2014-11-26 | 2014-11-26 | Transistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105633154B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291052A (en) * | 1991-07-09 | 1994-03-01 | Samsung Electronics Co., Ltd. | CMOS semiconductor device with (LDD) NMOS and single drain PMOS |
| CN102938377A (en) * | 2011-08-15 | 2013-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, P-channel metal oxide semiconductor (PMOS) transistor and forming method of P-channel metal oxide semiconductor transistor |
| US20140015104A1 (en) * | 2012-07-13 | 2014-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for Introducing Carbon to a Semiconductor Structure and Structures Formed Thereby |
| CN103715090A (en) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN103943502A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN104051341A (en) * | 2013-03-13 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Asymmetric cyclic deposition and etch process for epitaxial formation mechanisms of source and drain regions |
-
2014
- 2014-11-26 CN CN201410696596.3A patent/CN105633154B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5291052A (en) * | 1991-07-09 | 1994-03-01 | Samsung Electronics Co., Ltd. | CMOS semiconductor device with (LDD) NMOS and single drain PMOS |
| CN102938377A (en) * | 2011-08-15 | 2013-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method of semiconductor structure, P-channel metal oxide semiconductor (PMOS) transistor and forming method of P-channel metal oxide semiconductor transistor |
| US20140015104A1 (en) * | 2012-07-13 | 2014-01-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for Introducing Carbon to a Semiconductor Structure and Structures Formed Thereby |
| CN103715090A (en) * | 2012-09-29 | 2014-04-09 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN103943502A (en) * | 2013-01-22 | 2014-07-23 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect transistor and forming method thereof |
| CN104051341A (en) * | 2013-03-13 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Asymmetric cyclic deposition and etch process for epitaxial formation mechanisms of source and drain regions |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105633154B (en) | 2020-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101386838B1 (en) | METHODS AND APPARATUS FOR DOPED SiGe SOURCE/DRAIN STRESSOR DEPOSITION | |
| US9263549B2 (en) | Fin-FET transistor with punchthrough barrier and leakage protection regions | |
| KR101811796B1 (en) | Semiconductor devices including source/drain regions with abrupt junction profiles and methods of fabricating the same | |
| US8853008B1 (en) | Counter-doped low-power FinFET | |
| US9443963B2 (en) | SiGe FinFET with improved junction doping control | |
| CN103426769B (en) | Semiconductor device manufacturing method | |
| CN108962987B (en) | Semiconductor device and method for manufacturing the same | |
| CN105448679A (en) | Semiconductor device forming method | |
| US9263585B2 (en) | Methods of forming enhanced mobility channel regions on 3D semiconductor devices, and devices comprising same | |
| CN102403227A (en) | Manufacturing method for stepped silicon germanium source/drain structures | |
| CN105448916A (en) | Transistor and method of forming same | |
| CN103515238B (en) | Nmos pass transistor and formation method, CMOS structure and formation method | |
| CN104217955A (en) | N-type transistor, manufacture method of N-type transistor, and complementary metal oxide semiconductor | |
| CN102054695B (en) | Method for improving performance of semiconductor components | |
| CN102938375B (en) | Field effect transistor and forming method thereof | |
| CN104701177B (en) | The forming method of transistor | |
| CN102074476B (en) | Forming method of N-channel metal oxide semiconductor (NMOS) transistor | |
| CN109755297A (en) | Semiconductor devices and its manufacturing method | |
| CN103943504A (en) | Semiconductor device and manufacturing method thereof | |
| CN104752213A (en) | Semiconductor structure forming method | |
| CN104637879A (en) | Method for preparing semiconductor device | |
| CN107492487B (en) | Method for forming semiconductor device | |
| CN101930924B (en) | Fabrication method of MOS (Metal Oxide Semiconductor) transistor | |
| CN105826374B (en) | P-type fin field effect transistor and forming method thereof | |
| CN104701149A (en) | Semiconductor device and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |