CN105633110B - A kind of plane STT-MRAM memory unit and its reading/writing method - Google Patents
A kind of plane STT-MRAM memory unit and its reading/writing method Download PDFInfo
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- CN105633110B CN105633110B CN201510608804.4A CN201510608804A CN105633110B CN 105633110 B CN105633110 B CN 105633110B CN 201510608804 A CN201510608804 A CN 201510608804A CN 105633110 B CN105633110 B CN 105633110B
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Abstract
The present invention provides a kind of plane STT-MRAM memory unit.This STT-MRAM memory unit includes: magnetic reference layer, Magnetic memory layer, tunnel barrier layer, magnetocrystalline optimization auxiliary layer, sets pressurized layer and control line；Magnetocrystalline optimization auxiliary layer is adjacent with Magnetic memory layer and is set to one side of the Magnetic memory layer far from substrate base；It is adjacent and be set to magnetocrystalline optimization one side of the auxiliary layer far from substrate base to set pressurized layer and magnetocrystalline optimization auxiliary layer；Control line is adjacent with pressurized layer is set and is set to the one side far from substrate base of setting pressurized layer.The present invention also provides the reading/writing methods of plane STT-MRAM a kind of, including when read operation, and between control line and bit line plus forward bias voltage, the electric field of generation reduce the perpendicular magnetic anisotropy of Magnetic memory layer, intra-face anisotropy enhancing；When write operation, between control line and bit line plus negatively biasing voltage, the electric field of generation enhance the perpendicular magnetic anisotropy of Magnetic memory layer, and intra-face anisotropy weakens.
Description
Technical field
The present invention relates to memory device field more particularly to a kind of plane STT-MRAM memory unit and its read-write sides
Method.
Background technique
The magnetic that people are made into using the characteristic of magnetic tunnel junction (MTJ, Magnetic Tunnel Junction) in recent years
Property random access memory, as MRAM (Magnetic Random Access Memory).MRAM is that a kind of New Solid is non-
Volatile memory, it has the characteristic of high-speed read-write.Ferromagnetism MTJ is usually sandwich structure, remembers layer wherein being magnetic,
It can change the direction of magnetization to record different data；Middle layer is insulating layer；Magnetic reference layer is located at the another of insulating layer
Side, its direction of magnetization are constant.When the magnetization intensity vector direction between memory layer and reference layer is parallel or antiparallel,
The Resistance states of Magnetic Memory element also mutually should be low resistance state or high-impedance state.The Resistance states for measuring magnetoresistive element in this way, which can be obtained, deposits
The information of storage.
Has a kind of available high magneto-resistor (MR, Magneto Resistance) rate of method: in non crystalline structure
The surface of magnetic film accelerates crystallization to form a layer crystalization and accelerates film.After this tunic is formed, crystallization starts from tunnel barrier layer one
Side is formed, so that the surface of tunnel barrier layer is matched with magnetic surface formation, can be obtained by high MR in this way.
Generally classified by different write operation methods to MRAM device.Traditional MRAM is magnetic field switch type
MRAM: magnetic field is generated in the intersection for the current line that two intersect, the intensity of magnetization of the memory layer in magnetoresistive element can be changed
Direction.Spin-transfer torque magnetic RAM (STT-MRAM, Spin-transfer Torque Magnetic Random
Access Memory) entirely different write operation is then used, what it was utilized is the spin angular momentaum transfer of electronics, i.e. spin pole
The electron stream of change is transferred to its angular momentum the magnetic material in memory layer.The capacity of Magnetic memory layer is smaller, needs to carry out
The spin polarized current of write operation is also smaller.Institute can meet device miniaturization and low current density simultaneously in this way.
STT-MRAM have high-speed read-write, large capacity, low-power consumption characteristic, it is potential in electronic chip industry, especially moving chip
In industry, traditional semiconductor memory is substituted to realize the non-volatile of energy conservation and data.
In a simple face inner mold STT-MRAM structure, the memory layer of each MTJ element has in stable face
The intensity of magnetization.The easy magnetizing axis of face inner mold device is determined by shape in the face of memory layer or shape anisotropy.CMOS transistor
After the write current of generation flows through the stacked structure of magnetoresistive element, thus it is possible to vary its Resistance states, namely change the information of storage.
Resistance can change when carrying out write operation, use constant voltage under normal circumstances.In STT-MRAM, voltage is acted predominantly on aboutOn thick oxide skin(coating) (i.e. tunnel barrier layer).If voltage is excessive, tunnel barrier layer can be breakdown.Even if tunnel barrier
Layer will not be breakdown immediately, if repeating write operation, resistance value can be made to generate variation, and read operation mistake increases,
Magnetoresistive element can also fail, and can not re-record data.In addition, write operation needs sufficiently big voltage or spinning current.Institute
Incomplete problem is recorded also will appear before tunnel barrier layer is breakdown.
The read operation of STT-MRAM is voltage to be acted in MTJ stack structure, then measuring this MTJ element is in high resistant
State or low resistance state.In order to be correctly obtained Resistance states be it is high or low, required voltage is relatively high.And write operation and read operation
Required voltage value is simultaneously unequal, in current advanced technology nodes, if having any characteristic electron fluctuation between each MTJ, all
It will lead to the electric current that should carry out read operation, but as write current, change the magnetization direction of mtj memory layer.
Because making mtj memory device when its resistance value can be changed by carrying out write operation to this non-volatile mtj memory body
Part generates loss, shortens its life cycle.In order to reduce this negative effect, it is desirable to provide certain methods obtain certain
The STT-MRAM of structure can have high-precision read operation and highly reliable write operation simultaneously.
In US14/153047, dielectric layer and set pressurized layer and be set in below MTJ, that is, needed when depositing first dielectric layer with
Pressurized layer is set, then redeposition MTJ, such that MTJ, the deposition quality decline of tunnel barrier layer especially therein.
Summary of the invention
In view of the above drawbacks of the prior art, the present invention provides a kind of plane STT-MRAM memory units, including
Bit line and stacked structure, the stacked structure include:
The direction of magnetization of magnetic reference layer, the magnetic reference layer is constant and magnetic anisotropy is parallel to layer surface；
The direction of magnetization of Magnetic memory layer, the Magnetic memory layer is variable and magnetic anisotropy is parallel to layer surface；
Tunnel barrier layer, the tunnel barrier layer is between the magnetic reference layer and the Magnetic memory layer and distinguishes
It is adjacent with the magnetic reference layer and the Magnetic memory layer；
Further include:
Magnetocrystalline optimizes auxiliary layer, and the magnetocrystalline optimization auxiliary layer is adjacent with the Magnetic memory layer and is set to the magnetic
Property memory one side of the layer far from substrate base；
Set pressurized layer, the pressurized layer of setting is adjacent with magnetocrystalline optimization auxiliary layer and be set to the magnetocrystalline optimization auxiliary layer
One side far from the substrate base；
Control line, the control line and the pressurized layer of setting are adjacent and be set to and described set pressurized layer far from the substrate base
One side；
The Magnetic memory layer is connected with the bit line.
Further, the material of the magnetocrystalline optimization auxiliary layer is metal oxide, the nitride metal of NaCl lattice structure
Object or metal chloride, and its (100) crystal face is parallel to the basal plane of the substrate base.
Further, the metal in the metal oxide, metal nitride or metal chloride be Na, Li, Mg, Ca,
At least one of Zn, Cd, In, Sn, Cu, Ag.
Further, the material of magnetocrystalline optimization auxiliary layer be the MgO for having stable NaCl lattice structure under natural conditions,
At least one of MgN, CaO, CaN, MgZnO, CdO, CdN, MgCdO, CdZnO.
Further, the thickness range of the magnetocrystalline optimization auxiliary layer is 1~20nm.
Further, the resistance of at least 5 times stacked structures of resistance of the magnetocrystalline optimization auxiliary layer.
Further, the resistance of the magnetocrystalline optimization auxiliary layer is greater than 200ohm/ μm2。
Further, the material for setting pressurized layer is metal or metal alloy, and thickness is greater than 10nm.
Further, the material of the tunnel barrier layer is metal oxide, metal nitride or metal oxynitride.
Further, the material of the tunnel barrier layer is MgO, ZnO, MgZnO, Mg3N2, at least one of MgON.
Further, the material of the Magnetic memory layer is B alloy, wherein including at least one of Co, Fe, Ni member
Element.
Further, the material of the Magnetic memory layer is CoFeB or CoB, and wherein B element at least accounts for 10%.
Further, the Magnetic memory layer is multilayered structure, including the first Co alloy to connect with tunnel barrier layer
Layer and the 2nd Co alloy sublayer.
Further, the first Co alloy sublayer is CoFe or CoFeB；2nd Co alloy sublayer is CoFeB or CoB.
Further, an insert layer is added in two layers of Co alloy sublayer, in insert layer at least a kind of element be selected from Ta,
Hf, Zr, Ti, Mg, Nb, W, Mo, Ru, Al, Cu, Si, thickness are less than 0.5nm.
The present invention also provides a kind of reading/writing method with voltage-controlled plane STT-MRAM memory unit, packets
It includes:
When read operation between control line and bit line plus forward bias voltage, obtain electric field downwards, magnetocrystalline optimize auxiliary layer and
The perpendicular magnetic anisotropy that pressurized layer reduces memory layer is set, enhances intra-face anisotropy, enhances stability；
When write operation between control line and bit line plus negatively biasing voltage, obtain electric field upwards, magnetocrystalline optimize auxiliary layer and
The perpendicular magnetic anisotropy for setting pressurized layer enhancing memory layer, reduces intra-face anisotropy, reduces write current.
Further, forward bias voltage is 0 between 1.8V when the read operation.
Further, negatively biasing voltage is between -0.5V to -1.8V when the write operation.
Magnetocrystalline is optimized auxiliary layer, sets pressurized layer and control line is set on MTJ by the present invention, i.e., first production MTJ adds again
Work above layers effectively improve the deposition quality of MTJ.
It is described further below with reference to technical effect of the attached drawing to design of the invention, specific structure and generation, with
It is fully understood from the purpose of the present invention, feature and effect.
Detailed description of the invention
Fig. 1 is the schematic diagram of the section structure of plane STT-MRAM memory unit of the present invention；
Fig. 2 is another the schematic diagram of the section structure of plane STT-MRAM memory unit of the present invention；
Fig. 3 is the magnetoresistive element schematic diagram under read states；
Fig. 4 is the magnetoresistive element schematic diagram under write state.
Specific embodiment
In the description of embodiments of the present invention, it is to be understood that term " on ", "lower", "front", "rear", " left side ",
The orientation of the instructions such as " right side ", "vertical", "horizontal", "top", "bottom", "inner", "outside", " clockwise ", " counterclockwise " or position are closed
System is merely for convenience of description of the present invention and simplification of the description to be based on the orientation or positional relationship shown in the drawings, rather than indicates
Or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore cannot understand
For limitation of the present invention.
Fig. 1 is that a kind of section of a magneto-resistor memory unit of plane STT-MRAM array provided in this embodiment shows
It is intended to.Magnetoresistive element includes: bit line 1, magnetic reference layer 11, tunnel barrier layer 12, Magnetic memory layer 13, magnetocrystalline optimization auxiliary
Layer 15, sets pressurized layer 16, control line 17, through-hole VIA 14, selective transistor.Selective transistor includes: dielectric 2, interconnection
Layer 3, source contact zone 4, drain contact area 10, source region 5, gate insulating film 7, gate electrode 8, drain region 9.The magnetic of one group of magneto-resistor memory unit
Property reference layer 11 is connected with CMOS.Bit line 1 is connected by VIA 14 with 13 side of Magnetic memory layer.One group of magneto-resistor memory unit
Pressurized layer 16 of setting be connected with control line 17.
The direction of magnetization of magnetic reference layer 11 is constant and magnetic anisotropy is parallel to layer surface；The magnetization of Magnetic memory layer 13
Direction-agile and magnetic anisotropy is parallel to layer surface；Tunnel barrier layer 12 be located at magnetic reference layer 11 and Magnetic memory layer 13 it
Between and it is adjacent with magnetic reference layer 11 and Magnetic memory layer 13 respectively；It is adjacent with Magnetic memory layer 13 simultaneously that magnetocrystalline optimizes auxiliary layer 15
And it is set to one side of the Magnetic memory layer 13 far from substrate base；It is adjacent and be arranged to set pressurized layer 16 and magnetocrystalline optimization auxiliary layer 15
Optimize one side of the auxiliary layer 15 far from substrate base in magnetocrystalline；Control line 17 is adjacent with pressurized layer 16 is set and is set to and sets pressurized layer 16
One side far from substrate base；Magnetic memory layer 13 is connected with bit line 1.
Fig. 2 additionally provides the section signal of a magneto-resistor memory unit of another plane STT-MRAM array
Figure, VIA 14 and magnetocrystalline optimize auxiliary layer 15, set pressurized layer 16, the position of control line 17 is not necessarily fixed.
Magnetic memory layer 13 is ferrimagnet, and has the uniaxial magnetic anisotropy positioned at film surface.Tunnel barrier layer
12 be one layer of metal oxide thin, and such as MgO forms tunneling junction magnetoresistive between Magnetic memory layer 13 and magnetic reference layer 11.
In the case that direction of easy axis refers to no external magnetic field, the intrinsic magnetic energy of material has minimum energy value this side up.Meanwhile it is difficult
In the case that the direction of magnetization refers to no external magnetic field, the intrinsic magnetic energy of material has maximum energy value this side up.
Magnetic memory layer 13 has variable (turnover) magnetization direction；Magnetic reference layer 11 has constant
(fixed) magnetization direction.It can make polarization current that can only overturn the magnetization vector direction of Magnetic memory layer 13, and keep
The magnetization vector direction of magnetic reference layer 11 is constant.
Magnetocrystalline optimization auxiliary layer 15 can promote or change the perpendicular magnetic anisotropic of Magnetic memory layer 13.Magnetocrystalline optimization is auxiliary
It helps the material of layer 15 to be preferred with MgO, or is other metal oxides (nitride, chloride).These materials have stabilization
NaCl lattice structure.
The deposited of CoFeB (B content is not less than 15%) in Magnetic memory layer 13 is non crystalline structure.And tunnel barrier layer
12 optimize the MgO of auxiliary layer 15 with magnetocrystalline as NaCl crystal structure, and (100) crystal face is parallel to substrate plane.NaCl lattice
In structure, Mg atom respectively forms a set of fcc phase sublattice with O atom, and the displacement between them is [100] crystal orientation lattice
The half of constant.It [110] direction lattice constant between 2.98 to 3.02 Ethylmercurichlorendimides, this value exists slightly larger than bcc phase CoFe
[100] lattice constant of crystal orientation, the lattice mismatch generated between the two is between 4% to 7%.By 250 degrees Celsius or more temperature
The annealing of degree, amorphous CoFeB crystallization form the CoFe crystal grain of bcc phase, its epitaxial growth plane (100) crystal face is parallel to
The surface of NaCl lattice structure layer, and have in face and expand, the characteristic shunk outside face, therefore Magnetic memory layer 13 passes through up and down
Two with the interface interaction of MgO, there is perpendicular magnetic anisotropy on interface.Thin MgO tunnel barrier 12 has and circuit phase
The low magnetoelectricity resistance value matched, thick MgO magnetocrystalline optimizes to be had at auxiliary layer 15 and the bcc phase CoFe crystal grain interfaces of Magnetic memory layer 13
Superior NaCl lattice structure.
Because perpendicular magnetic anisotropy derives from interface interaction, the intensity of magnetization of thick CoFeB Magnetic memory layer 13 is still located at
In film surface, when perpendicular magnetic anisotropy enhancing, critical spin transfer current can also reduce therewith.
The specific material of the present embodiment:
Magnetic reference layer 11 is PtMn (20m)/CoFe (2nm)/Ru (0.8nm)/CoFe (2nm), and tunnel barrier layer 12 is
MgO (1nm), Magnetic memory layer 13 are CoFeB (3nm), and it is MgO (2nm) that magnetocrystalline, which optimizes auxiliary layer 15, and setting pressurized layer 16 is Ta
(20nm)/Cu(20nm)/Ta(20nm)."/" refers to that the element on its left side is located on the element on the right.Magnetocrystalline optimizes auxiliary layer 15
Thickness be greater than 1nm, be less than 20nm.The vertical resistor that magnetocrystalline optimizes auxiliary layer 15 is greater than 200ohm/ μm2.Set the thickness of pressurized layer 16
Degree is greater than 10nm.
Magnetoresistive element of Fig. 3 signal under read states, adds forward bias at this time, obtains between control line 17 and bit line 1
Downward electric field, the interface of Magnetic memory layer 13 and magnetocrystalline optimization auxiliary layer 15, O ion shifts up, reduce two layers it
Between interface interaction, reduce the perpendicular magnetic anisotropy of Magnetic memory layer 13, that is, enhance in-plane anisotropy, can make read grasp
Make more stable.
Since the resistance value and thickness of MgO layer are exponentially increased relationship.The typical RA value of stack architecture MTJ should 3 to
20ohm/ μm 2, and the RA value of magnetocrystalline optimization auxiliary layer 15 is greater than 200ohm/ μm2.So magnetocrystalline optimization auxiliary layer 15 have it is relatively good
Dielectric resistance, can make to be almost equal to zero from the leakage current for setting pressurized layer 16 and flowing to mtj stack.Fig. 4 signal is under write state
Magnetoresistive element.On setting pressurized layer 16 plus negative voltage forms electric field, this electric field is directed toward magnetocrystalline optimization auxiliary layer 15 from below to up
Lower surface can enhance the perpendicular magnetic anisotropy of Magnetic memory layer 13, that is, reduce intra-face anisotropy, make across stack architecture
The spin polarized current of MTJ is easily changed memory layer state, so the write circuit of needs can be greatly reduced, the magnetization in addition changed
Intensity direction is determined by the direction of write current.Write current enters stack architecture via bit line 1 and acts on Magnetic memory layer 13.
After write operation is completed, the bias voltage of wordline/set pressurized layer 16 is closed, the perpendicular magnetic anisotropy of Magnetic memory layer 13 obtains extensive
It is multiple, so that memory unit is able to maintain excellent thermal stability and data retention.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without
It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical solution, all should be within the scope of protection determined by the claims.
Claims (10)
1. a kind of plane STT-MRAM memory unit, including bit line and stacked structure, the stacked structure include:
The direction of magnetization of magnetic reference layer, the magnetic reference layer is constant and magnetic anisotropy is parallel to layer surface；
The direction of magnetization of Magnetic memory layer, the Magnetic memory layer is variable and magnetic anisotropy is parallel to layer surface；
Tunnel barrier layer, the tunnel barrier layer between the magnetic reference layer and the Magnetic memory layer and respectively with institute
It states magnetic reference layer and the Magnetic memory layer is adjacent；
It is characterized by further comprising:
Magnetocrystalline optimizes auxiliary layer, and the magnetocrystalline optimization auxiliary layer is adjacent with the Magnetic memory layer and is set to the magnetic note
Recall one side of the layer far from substrate base；
Set pressurized layer, it is described to set that pressurized layer is adjacent with magnetocrystalline optimization auxiliary layer and to be set to the magnetocrystalline optimization auxiliary layer separate
The one side of the substrate base；
Control line, the control line and the pressurized layer of setting are adjacent and be set to and described set one of pressurized layer far from the substrate base
Face；
The Magnetic memory layer is connected with the bit line.
2. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the magnetocrystalline optimization auxiliary layer
Material is metal oxide, metal nitride or the metal chloride of NaCl lattice structure, and its (100) crystal face be parallel to it is described
The basal plane of substrate base.
3. plane STT-MRAM memory unit as claimed in claim 2, which is characterized in that the metal oxide, metal
Metal in nitride or metal chloride is at least one of Na, Li, Mg, Ca, Zn, Cd, In, Sn, Cu, Ag.
4. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the magnetocrystalline optimization auxiliary layer
Thickness range is 1~20nm.
5. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the magnetocrystalline optimization auxiliary layer
The resistance of at least 5 times stacked structures of resistance.
6. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the magnetocrystalline optimization auxiliary layer
Resistance is greater than 200ohm/ μm2。
7. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the material for setting pressurized layer is gold
Belong to or metal alloy, thickness are greater than 10nm.
8. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the material of the tunnel barrier layer
For metal oxide, metal nitride or metal oxynitride.
9. plane STT-MRAM memory unit as described in claim 1, which is characterized in that the material of the Magnetic memory layer
For B alloy, wherein including at least one of Co, Fe, Ni element.
10. a kind of reading/writing method of the plane STT-MRAM memory unit as described in claim 1~9 is any, feature exist
In,
When read operation, between control line and bit line plus forward bias voltage, the electric field of generation make the vertical each of Magnetic memory layer
Anisotropy reduces, intra-face anisotropy enhancing；
When write operation, between control line and bit line plus negatively biasing voltage, the electric field of generation make the vertical each of Magnetic memory layer
Anisotropy enhancing, intra-face anisotropy weaken.
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| CN1783334A (en) * | 2004-11-29 | 2006-06-07 | 株式会社日立制作所 | Magnetic memory and method of manufacturing the same |
| CN101783166A (en) * | 2009-01-14 | 2010-07-21 | 索尼公司 | Nonvolatile magnetic memory device |
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| KR100457159B1 (en) * | 2001-12-26 | 2004-11-16 | 주식회사 하이닉스반도체 | Magnetic random access memory |
| US10953319B2 (en) * | 2013-01-28 | 2021-03-23 | Yimin Guo | Spin transfer MRAM element having a voltage bias control |
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| CN1783334A (en) * | 2004-11-29 | 2006-06-07 | 株式会社日立制作所 | Magnetic memory and method of manufacturing the same |
| CN101783166A (en) * | 2009-01-14 | 2010-07-21 | 索尼公司 | Nonvolatile magnetic memory device |
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