CN105633110A - Planar type STT-MRAM (spin-transfer torque magnetic random access memory) memory unit and read-write method therefor - Google Patents
Planar type STT-MRAM (spin-transfer torque magnetic random access memory) memory unit and read-write method therefor Download PDFInfo
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Abstract
The invention provides a planar type STT-MRAM (spin-transfer torque magnetic random access memory) memory unit. The STT-MRAM memory unit comprises a magnetic reference layer, a magnetic memory layer, a tunnel barrier layer, a magnetocrystalline optimizing auxiliary layer, a pressing layer and a control line, wherein the magnetocrystalline optimizing auxiliary layer is adjacent to the magnetic memory layer, and arranged on one surface, far from a substrate chip, of the magnetic memory layer; the pressing layer is adjacent to the magnetocrystalline optimizing auxiliary layer, and arranged on one surface, far from the substrate chip, of the magnetocrystalline optimizing auxiliary layer; and the control line is adjacent to the pressing layer, and arranged on one surface, far from the substrate chip, of the pressing layer. The invention also provides a read-write method for the planar type STT-MRAM memory unit; the read-write method comprises the steps that a positive bias voltage is applied between the control line and a bit line in the reading operation; the generated electric field weakens the perpendicular anisotropy of the magnetic memory layer and strengthens the in-plane anisotropy of the magnetic memory layer; a negative bias voltage is applied between the control line and the bit line in the writing operation; the generated electric field strengthens the perpendicular anisotropy of the magnetic memory layer and weakens the in-plane anisotropy of the magnetic memory layer.
Description
Technical field
The present invention relates to memory device field, particularly relate to a kind of plane STT-MRAM mnemon and reading/writing method thereof.
Background technology
People utilize the magnetic random access memory that the characteristic of MTJ (MTJ, MagneticTunnelJunction) is made in recent years, are MRAM (MagneticRandomAccessMemory). MRAM is a kind of New Solid nonvolatile memory, and it has the characteristic of high-speed read-write. Ferromagnetism MTJ is generally sandwich structure, and be wherein magnetic memory layer, and it can change the direction of magnetization to record different data; Intermediate layer is insulating barrier; Magnetic reference layer is positioned at the opposite side of insulating barrier, and its direction of magnetization is constant. When the magnetization intensity vector direction remembered between layer and reference layer is parallel or during antiparallel, the Resistance states of Magnetic Memory element also should be low resistance state or high-impedance state mutually. The Resistance states so measuring magnetoresistive element can obtain the information of storage.
A kind of existing method can obtain high magneto-resistor (MR, MagnetoResistance) rate: accelerates crystallization on the surface of the magnetic film of non crystalline structure and forms a layer crystalization acceleration film. After this tunic is formed, crystallization starts to be formed from tunnel barrier layer side, so makes the surface of tunnel barrier layer be formed with magnetic surface and mates, so can be obtained by high MR.
Typically via different write operation methods, MRAM device is classified. Traditional MRAM is magnetic field switch type MRAM: the intersection at two electric current lines intersected produces magnetic field, can change the magnetization direction remembering layer in magnetoresistive element. Spin-transfer torque magnetic RAM (STT-MRAM, Spin-transferTorqueMagneticRandomAccessMemory) diverse write operation is then adopted, what it utilized is the spin angular momentaum transfer of electronics, and namely the electron stream of spin polarization is transferred to the magnetic material in memory layer its angular momentum. The capacity of Magnetic memory layer is more little, it is necessary to the spin polarized current carrying out write operation is also more little. Institute in this way can meet device miniaturization and low current density simultaneously. STT-MRAM has the characteristic of high-speed read-write, Large Copacity, low-power consumption, potential in electronic chip industry, especially in moving chip industry, substitutes traditional semiconductor memory to realize the non-volatile of energy conservation and data.
In a simple face inner mold STT-MRAM structure, the memory layer of each MTJ element has the intensity of magnetization in stable face. The easy magnetizing axis of face inner mold device is determined by remembering shape or shape anisotropy in the face of layer. After the write current that CMOS transistor produces flows through the stacked structure of magnetoresistive element, thus it is possible to vary its Resistance states, namely change the information of storage. When carrying out write operation, resistance can change, and generally adopts constant voltage. In STT-MRAM, voltage acts predominantly on aboutOn thick oxide skin(coating) (i.e. tunnel barrier layer). If voltage is excessive, tunnel barrier layer can be breakdown. Even if tunnel barrier layer will not be breakdown immediately, if repeating write operation, resistance value being made to produce change, read operation mistake increases, and magnetoresistive element also can lose efficacy, it is impossible to re-records data. It addition, write operation needs sufficiently large voltage or spinning current. Incomplete problem is recorded so also there will be before tunnel barrier layer is breakdown.
The read operation of STT-MRAM is that voltage is acted in MTJ stack structure, then measures this MTJ element and be in high-impedance state or low resistance state. High or low to be correctly obtained Resistance states, it is necessary to voltage of a relatively high. And write operation and read operation required voltage value are also unequal, at current advanced technology nodes, if there being any characteristic electron to fluctuate between each MTJ, the electric current that should carry out read operation all can be caused, but, as write current, the magnetization direction of mtj memory layer is changed.
Because when this non-volatile mtj memory body being carried out write operation and can change its resistance value, make mtj memory device produce loss, shorten its life cycle. In order to reduce this negative effect, it is desirable to provide certain methods obtains the STT-MRAM of certain structure, it is possible to have high-precision read operation and highly reliable write operation simultaneously.
In US14/153047, dielectric layer being set in below MTJ with putting laminate layer, namely need first dielectric layer during deposition and put laminate layer, then depositing MTJ again, such that MTJ, the deposition quality of tunnel barrier layer especially therein declines.
Summary of the invention
Because the drawbacks described above of prior art, the invention provides a kind of plane STT-MRAM mnemon, including bit line and stacked structure, described stacked structure includes:
Magnetic reference layer, the direction of magnetization of described magnetic reference layer is constant and magnetic anisotropy is parallel to a layer surface;
Magnetic memory layer, the direction of magnetization of described Magnetic memory layer is variable and magnetic anisotropy is parallel to a layer surface;
Tunnel barrier layer, described tunnel barrier layer is between described magnetic reference layer and described Magnetic memory layer and adjacent with described magnetic reference layer and described Magnetic memory layer respectively;
Also include:
Magnetocrystalline optimizes auxiliary layer, and described magnetocrystalline optimization auxiliary layer is adjacent with described Magnetic memory layer and is arranged at the described Magnetic memory layer one side away from substrate base;
Put laminate layer, described in put laminate layer and described magnetocrystalline to optimize auxiliary layer adjacent and be arranged at described magnetocrystalline and optimize the auxiliary layer one side away from described substrate base;
Control line, described control line is adjacent and put the laminate layer one side away from described substrate base described in being arranged at described laminate layer of putting;
Described Magnetic memory layer is connected with described bit line.
Further, it is the metal-oxide of NaCl lattice structure, metal nitride or metal chloride that described magnetocrystalline optimizes the material of auxiliary layer, and its (100) crystal face is parallel to the basal plane of described substrate base.
Further, the metal in described metal-oxide, metal nitride or metal chloride is at least one in Na, Li, Mg, Ca, Zn, Cd, In, Sn, Cu, Ag.
Further, described magnetocrystalline optimizes the material of auxiliary layer is have at least one in MgO, MgN, CaO, CaN, MgZnO, CdO, CdN, MgCdO, CdZnO of stable NaCl lattice structure under naturalness.
Further, described magnetocrystalline optimizes the thickness range of auxiliary layer is 1��20nm.
Further, described magnetocrystalline optimizes the resistance of the described stacked structure of resistance at least 5 times of auxiliary layer.
Further, described magnetocrystalline optimizes the resistance of auxiliary layer more than 200ohm/ ��m2��
Further, described in put the material of laminate layer be metal or metal alloy, thickness is more than 10nm.
Further, the material of described tunnel barrier layer is metal-oxide, metal nitride or metal oxynitride.
Further, the material of described tunnel barrier layer is MgO, ZnO, MgZnO, Mg3N2, at least one in MgON.
Further, the material of described Magnetic memory layer is B alloy, wherein comprises at least one element in Co, Fe, Ni.
Further, the material of described Magnetic memory layer is CoFeB or CoB, and wherein B element at least accounts for 10%.
Further, described Magnetic memory layer is multiple structure, including the Co alloy sublayer connected with tunnel barrier layer and the 2nd Co alloy sublayer.
Further, a described Co alloy sublayer is CoFe or CoFeB; 2nd Co alloy sublayer is CoFeB or CoB.
Further, adding an interposed layer in two-layer Co alloy sublayer, have at least a kind of element selected from Ta, Hf, Zr, Ti, Mg, Nb, W, Mo, Ru, Al, Cu, Si in interposed layer, thickness is less than 0.5nm.
Present invention also offers a kind of reading/writing method with voltage-controlled plane STT-MRAM mnemon, including:
Adding forward bias voltage during read operation between control line and bit line, obtain electric field downwards, magnetocrystalline optimizes auxiliary layer and puts the perpendicular magnetic anisotropy of laminate layer reduction memory layer, strengthens intra-face anisotropy, enhanced stability;
Adding negatively biasing voltage during write operation between control line and bit line, obtain electric field upwards, magnetocrystalline optimizes auxiliary layer and puts the perpendicular magnetic anisotropy of laminate layer hypermnesis layer, reduces intra-face anisotropy, reduces write current.
Further, during described read operation, forward bias voltage is between 0 to 1.8V.
Further, during described write operation, negatively biasing voltage is between-0.5V to-1.8V.
Magnetocrystalline optimizes auxiliary layer by the present invention, put laminate layer and control line is set on MTJ, namely first makes MTJ and reprocesses above layers, effectively improves the deposition quality of MTJ.
Below with reference to accompanying drawing, the technique effect of the design of the present invention, concrete structure and generation is described further, to be fully understood from the purpose of the present invention, feature and effect.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of plane STT-MRAM mnemon of the present invention;
Fig. 2 is another cross-sectional view of plane STT-MRAM mnemon of the present invention;
Fig. 3 is the magnetoresistive element schematic diagram being under read states;
Fig. 4 is the magnetoresistive element schematic diagram being under write state.
Detailed description of the invention
In the description of embodiments of the present invention, it will be appreciated that, term " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end ", " interior ", " outward ", " clockwise ", orientation or the position relationship of the instruction such as " counterclockwise " are based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than the device of instruction or hint indication or element must have specific orientation, with specific azimuth configuration and operation, therefore it is not considered as limiting the invention.
The generalized section of one magneto-resistor mnemon of a kind of plane STT-MRAM array that Fig. 1 provides for the present embodiment. Magnetoresistive element includes: bit line 1, magnetic reference layer 11, tunnel barrier layer 12, Magnetic memory layer 13, and magnetocrystalline optimizes auxiliary layer 15, puts laminate layer 16, control line 17, through hole VIA14, selectivity transistor. Selectivity transistor includes: electrolyte 2, interconnection layer 3, contact area, source 4, misses contact area 10, source region 5, gate insulating film 7, gate electrode 8, drain region 9. The magnetic reference layer 11 of one group of magneto-resistor mnemon is connected with CMOS. Bit line 1 is connected with Magnetic memory layer 13 side by VIA14. The laminate layer 16 of putting of one group of magneto-resistor mnemon is connected with control line 17.
The direction of magnetization of magnetic reference layer 11 is constant and magnetic anisotropy is parallel to a layer surface; The direction of magnetization of Magnetic memory layer 13 is variable and magnetic anisotropy is parallel to a layer surface; Tunnel barrier layer 12 is between magnetic reference layer 11 and Magnetic memory layer 13 and adjacent with magnetic reference layer 11 and Magnetic memory layer 13 respectively; Magnetocrystalline optimization auxiliary layer 15 is adjacent with Magnetic memory layer 13 and is arranged at the Magnetic memory layer 13 one side away from substrate base; Putting laminate layer 16 and magnetocrystalline, to optimize auxiliary layer 15 adjacent and be arranged at magnetocrystalline and optimize the auxiliary layer 15 one side away from substrate base; Control line 17 is adjacent with putting laminate layer 16 and is arranged at the one side putting laminate layer 16 away from substrate base; Magnetic memory layer 13 is connected with bit line 1.
Fig. 2 additionally provides the generalized section of a magneto-resistor mnemon of another plane STT-MRAM array, and VIA14 optimizes auxiliary layer 15 with magnetocrystalline, puts laminate layer 16, and the position of control line 17 is not necessarily fixed.
Magnetic memory layer 13 is ferrimagnet, and has the uniaxial magnetic anisotropy being positioned at face. Tunnel barrier layer 12 is one layer of metal oxide thin, such as MgO, formation tunneling junction magnetoresistive between Magnetic memory layer 13 and magnetic reference layer 11. When direction of easy axis refers to without external magnetic field, the intrinsic magnetic energy of material has minimum energy value this side up. Meanwhile, when hard direction refers to without external magnetic field, the intrinsic magnetic energy of material has maximum energy value this side up.
Magnetic memory layer 13 has variable (turnover) magnetization direction; Magnetic reference layer 11 has constant (fixing) magnetization direction. Current of polarization can be made can only to overturn the magnetization vector direction of Magnetic memory layer 13, and keep the magnetization vector direction of magnetic reference layer 11 constant.
Magnetocrystalline optimizes auxiliary layer 15 can promote or change the perpendicular magnetic anisotropic of Magnetic memory layer 13. Magnetocrystalline optimizes the material of auxiliary layer 15 and is preferred with MgO, or is other metal-oxide (nitride, chloride). These materials have stable NaCl lattice structure.
The deposited of the CoFeB (B content is not less than 15%) in Magnetic memory layer 13 is non crystalline structure. And the MgO that tunnel barrier layer 12 and magnetocrystalline optimize auxiliary layer 15 is NaCl crystal structure, and (100) crystal face is parallel to substrate plane. In NaCl lattice structure, Mg atom and O atom each form a set of fcc phase sublattice respectively, and the displacement between them is the half of [100] crystal orientation lattice paprmeter. Its lattice paprmeter in [110] direction is between 2.98 to 3.02 Ethylmercurichlorendimides, and this value is slightly larger than the bcc phase CoFe lattice paprmeter in [100] crystal orientation, and the lattice mismatch produced between the two is between 4% to 7%. Annealing through 250 degrees Celsius of temperatures above, amorphous CoFeB crystallization forms the CoFe crystal grain of bcc phase, its epitaxial growth plane (100) crystal face is parallel to the surface of NaCl lattice structure layer, and have in face and expand, the characteristic shunk outside face, therefore Magnetic memory layer 13 by upper and lower two with the interface interaction of MgO, interface has perpendicular magnetic anisotropy. Thin MgO tunnel barrier 12 has a low magnetoelectricity resistance matched with circuit, and thick MgO magnetocrystalline optimizes the bcc phase CoFe crystal grain interfaces place of auxiliary layer 15 and Magnetic memory layer 13 and has more excellent NaCl lattice structure.
Because perpendicular magnetic anisotropy derives from interface interaction, the intensity of magnetization of thick CoFeB Magnetic memory layer 13 is still positioned at face, and when perpendicular magnetic anisotropy strengthens, critical spin transfer current also can reduce therewith.
The concrete material of the present embodiment:
Magnetic reference layer 11 is PtMn (20m)/CoFe (2nm)/Ru (0.8nm)/CoFe (2nm), tunnel barrier layer 12 is MgO (1nm), Magnetic memory layer 13 is CoFeB (3nm), it is MgO (2nm) that magnetocrystalline optimizes auxiliary layer 15, puts laminate layer 16 for Ta (20nm)/Cu (20nm)/Ta (20nm). "/" refers to that the element on its left side is positioned on the element on the right. Magnetocrystalline optimizes the thickness of auxiliary layer 15 more than 1nm, less than 20nm. Magnetocrystalline optimizes the vertical resistor of auxiliary layer 15 more than 200ohm/ ��m2. Put the thickness of laminate layer 16 more than 10nm.
Fig. 3 signal is in the magnetoresistive element under read states, now add forward bias between control line 17 and bit line 1, obtain electric field downwards, Magnetic memory layer 13 optimizes the interface of auxiliary layer 15 with magnetocrystalline, O ion shifts up, and reduces the interface interaction between two-layer, reduces the perpendicular magnetic anisotropy of Magnetic memory layer 13, namely in-plane anisotropy is enhanced, it is possible to make read operation more stable.
Owing to the resistance of MgO layer is exponentially increased relation with thickness. The typical RA value of stack architecture MTJ should at 3 to 20ohm/ ��m 2, and magnetocrystalline optimize auxiliary layer 15 RA value more than 200ohm/ ��m2. So magnetocrystalline optimizes auxiliary layer 15 and has reasonable dielectric resistance, it is possible to make the leakage current from putting laminate layer 16 and flow mtj stack be almost equal to zero. Fig. 4 signal is in the magnetoresistive element under write state. Putting, laminate layer 16 adds negative voltage formation electric field, this electric field points to magnetocrystalline from below to up and optimizes the lower surface of auxiliary layer 15, the perpendicular magnetic anisotropy of Magnetic memory layer 13 can be strengthened, namely intra-face anisotropy is reduced, the spin polarized current through stack architecture MTJ is made to be easily changed memory layer state, so the write circuit of needs can be greatly reduced, the magnetization direction additionally changed is determined by the direction of write current. Write current enters stack architecture via bit line 1 and acts on Magnetic memory layer 13. After write operation completes, closing the bias voltage of wordline/put laminate layer 16, the perpendicular magnetic anisotropy of Magnetic memory layer 13 is restored so that mnemon can keep excellent heat stability and data retention.
The preferred embodiment of the present invention described in detail above. Should be appreciated that those of ordinary skill in the art just can make many modifications and variations according to the design of the present invention without creative work. Therefore, all technical staff in the art, all should in the protection domain being defined in the patent claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (10)
1. a plane STT-MRAM mnemon, including bit line and stacked structure, described stacked structure includes:
Magnetic reference layer, the direction of magnetization of described magnetic reference layer is constant and magnetic anisotropy is parallel to a layer surface;
Magnetic memory layer, the direction of magnetization of described Magnetic memory layer is variable and magnetic anisotropy is parallel to a layer surface;
Tunnel barrier layer, described tunnel barrier layer is between described magnetic reference layer and described Magnetic memory layer and adjacent with described magnetic reference layer and described Magnetic memory layer respectively;
It is characterized in that, also include:
Magnetocrystalline optimizes auxiliary layer, and described magnetocrystalline optimization auxiliary layer is adjacent with described Magnetic memory layer and is arranged at the described Magnetic memory layer one side away from substrate base;
Put laminate layer, described in put laminate layer and described magnetocrystalline to optimize auxiliary layer adjacent and be arranged at described magnetocrystalline and optimize the auxiliary layer one side away from described substrate base;
Control line, described control line is adjacent and put the laminate layer one side away from described substrate base described in being arranged at described laminate layer of putting;
Described Magnetic memory layer is connected with described bit line.
2. plane STT-MRAM mnemon as claimed in claim 1, it is characterized in that, it is the metal-oxide of NaCl lattice structure, metal nitride or metal chloride that described magnetocrystalline optimizes the material of auxiliary layer, and its (100) crystal face is parallel to the basal plane of described substrate base.
3. plane STT-MRAM mnemon as claimed in claim 2, it is characterised in that the metal in described metal-oxide, metal nitride or metal chloride is at least one in Na, Li, Mg, Ca, Zn, Cd, In, Sn, Cu, Ag.
4. plane STT-MRAM mnemon as claimed in claim 1, it is characterised in that it is 1��20nm that described magnetocrystalline optimizes the thickness range of auxiliary layer.
5. plane STT-MRAM mnemon as claimed in claim 1, it is characterised in that described magnetocrystalline optimizes the resistance of the described stacked structure of resistance at least 5 times of auxiliary layer.
6. plane STT-MRAM mnemon as claimed in claim 1, it is characterised in that described magnetocrystalline optimizes the resistance of auxiliary layer more than 200ohm/ ��m2��
7. plane STT-MRAM mnemon as claimed in claim 1, it is characterised in that described in put the material of laminate layer be metal or metal alloy, thickness is more than 10nm.
8. plane STT-MRAM mnemon as claimed in claim 1, it is characterised in that the material of described tunnel barrier layer is metal-oxide, metal nitride or metal oxynitride.
9. plane STT-MRAM mnemon as claimed in claim 1, it is characterised in that the material of described Magnetic memory layer is B alloy, wherein comprises at least one element in Co, Fe, Ni.
10. one kind as arbitrary in claim 1��9 as described in the reading/writing method of plane STT-MRAM mnemon, it is characterised in that
During read operation, adding forward bias voltage between control line and bit line, the electric field of generation makes the perpendicular magnetic anisotropy of Magnetic memory layer reduce, and intra-face anisotropy strengthens;
During write operation, adding negatively biasing voltage between control line and bit line, the electric field of generation makes the perpendicular magnetic anisotropy of Magnetic memory layer strengthen, and intra-face anisotropy weakens.
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| US10079337B2 (en) | 2017-01-11 | 2018-09-18 | International Business Machines Corporation | Double magnetic tunnel junction with dynamic reference layer |
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| US20030117835A1 (en) * | 2001-12-26 | 2003-06-26 | Hynix Semiconductor Inc. | Magnetic random access memory |
| CN1783334A (en) * | 2004-11-29 | 2006-06-07 | 株式会社日立制作所 | Magnetic memory and method of manufacturing the same |
| CN101783166A (en) * | 2009-01-14 | 2010-07-21 | 索尼公司 | Nonvolatile magnetic memory device |
| US20140210025A1 (en) * | 2013-01-28 | 2014-07-31 | T3Memory, Inc. | Spin transfer mram element having a voltage bias control |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030117835A1 (en) * | 2001-12-26 | 2003-06-26 | Hynix Semiconductor Inc. | Magnetic random access memory |
| CN1783334A (en) * | 2004-11-29 | 2006-06-07 | 株式会社日立制作所 | Magnetic memory and method of manufacturing the same |
| CN101783166A (en) * | 2009-01-14 | 2010-07-21 | 索尼公司 | Nonvolatile magnetic memory device |
| US20140210025A1 (en) * | 2013-01-28 | 2014-07-31 | T3Memory, Inc. | Spin transfer mram element having a voltage bias control |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10079337B2 (en) | 2017-01-11 | 2018-09-18 | International Business Machines Corporation | Double magnetic tunnel junction with dynamic reference layer |
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