CN105633081A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN105633081A CN105633081A CN201410585002.1A CN201410585002A CN105633081A CN 105633081 A CN105633081 A CN 105633081A CN 201410585002 A CN201410585002 A CN 201410585002A CN 105633081 A CN105633081 A CN 105633081A
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Abstract
The present invention provides a manufacturing method of semiconductor device. The manufacturing method comprises: providing an SOI substrate; forming a device structure on the substrate; removing the grid of the device structure until exposing top silicon to form a grid opening; performing etching along the (111) crystal face of the top silicon to form a groove under the grid opening; and filling the grid opening and the groove to form a grid again. The manufacturing method of a semiconductor device is able to form thinner channel so as to facilitate forming a full depletion device, and is able to allow the effective length of the channel to get longer so as to effectively ease a short-channel effect; and moreover, the manufacturing method of a semiconductor device may utilize a common SOI substrate, allows the manufacture technology to be compatible with the tradition, and is simple in technology, easy to operate and low in manufacture cost.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly to a kind of semiconductor device and manufacture method thereof.
Background technology
Body silicon device technology is always up the mainstream technology of semiconductor device, but along with the characteristic size of device constantly reduces, SOI (silicon-on-insulator, Silicon-On-Insulator) technology is arisen at the historic moment.
SOI technology is to be embedded into one layer of SiO at the bottom of backing and in the middle of top layer silicon2Bury oxide layer, then using this substrate as substrate, in top layer silicon make transistor device. SiO2Bury oxide layer and ensure that the medium isolation of device, the parasitic capacitance and the leakage current that make device are substantially reduced, also completely eliminate the parasitic latch-up in body silicon device, there is the advantages such as parasitic capacitance is little, short-channel effect is little, speed is fast, integrated level is high, low in energy consumption, increasingly by the favor of industry.
SOI substrate divides thick-layer and thin layer SOI, the thickness of the top layer silicon of thin layer SOI device is less than the width being maximally depleted layer under grid, when the lower thickness of top layer silicon, device changes from part depletion (PartiallyDepletion) to all exhausting (FullyDepletion), when top layer silicon is less than 50nm, for ultra-thin SOI (UltrathinSOI, UTSOI), SOI device all exhausts, the device all exhausted has larger current driving force, steep sub-threshold slope, less short channel, narrow-channel effect and the advantages such as Kink effect is completely eliminated, it is particularly well-suited at a high speed, low pressure, the application of low consumption circuit, ultra-thin SOI becomes the ideal solution of below 22nm dimension process.
But, ETSOI is high for the uniformity requirement of top layer silicon thickness, the manufacturing cost of wafer is high, simultaneously, owing to thin top layer silicon can cause entirely decrystallized, S seed silicon (SeedSi) is not had as growth starting point, it is necessary to original position epitaxial growth source-drain area forms source-drain area and source drain extension district, and technique is complex and cost is high when source and drain annealing crystallization.
Summary of the invention
The purpose of the present invention is intended at least solve one of above-mentioned technological deficiency, it is provided that a kind of semiconductor device and manufacture method thereof.
A kind of manufacture method of semiconductor device, including:
SOI substrate is provided;
Substrate is formed device architecture;
The grid of removal devices structure, until exposed top layer silicon, to form grid opening;
(111) crystal face along top layer silicon performs etching, to form groove under grid opening;
Fill grid opening and groove, again to form grid.
Optionally, anisotropic etching is adopted to carry out wet etching along (111) crystal face of top layer silicon, to form groove under grid opening.
Optionally, etching agent is TEMAH.
Optionally, before again forming grid, further comprise the steps of: and carry out oxidation technology, to form oxide layer in flute surfaces; Remove this oxide layer.
Optionally, in the step performed etching along (111) crystal face of top layer silicon, by control etch period, the groove of formation be shaped as the del of opening, rhombus or inverted trapezoidal.
Additionally, present invention also offers the semiconductor device that said method is formed, including:
SOI substrate;
Device architecture on substrate;
Wherein, being formed with groove in the top layer silicon of substrate, the wall of this groove is etched by (111) crystal face along top layer silicon and is formed; The grid of device architecture is formed in the trench and on groove.
Optionally, described groove is the shape of the del of opening, rhombus or inverted trapezoidal.
The semiconductor device of embodiment of the present invention offer and manufacture method thereof, adopt SOI substrate, after forming device architecture, grid is removed, and etch the channel region under grid opening further, thus forming groove in the substrate of channel region, and then again form grid, so, raceway groove after etching becomes thinner, being beneficial to the device forming complete depletion type, meanwhile, the effective length of raceway groove is elongated, effectively alleviate short-channel effect, the method can utilize common SOI substrate, and manufacturing process and tradition compatible, simple for process and low cost of manufacture.
Accompanying drawing explanation
The present invention above-mentioned and/or that add aspect and advantage will be apparent from easy to understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1 illustrates the flow chart of the manufacture method of Semiconductor substrate according to embodiments of the present invention;
Fig. 2-Fig. 8 illustrates the schematic diagram of each formation stages of semiconductor device according to embodiments of the present invention.
Detailed description of the invention
Being described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of same or like function from start to finish. The embodiment described below with reference to accompanying drawing is illustrative of, and is only used for explaining the present invention, and is not construed as limiting the claims.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention can also adopt other to be different from alternate manner described here to be implemented, those skilled in the art can do similar popularization when without prejudice to intension of the present invention, and therefore the present invention is not by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; representing that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this. Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
The present invention proposes the manufacture method of a kind of semiconductor device, including step: provide SOI substrate; Substrate is formed device architecture; The grid of removal devices structure, until exposed top layer silicon, to form grid opening; (111) crystal face along top layer silicon performs etching, to form groove under grid opening; Fill grid opening and groove, again to form grid.
In the present invention, adopt SOI substrate, after forming device architecture, grid is removed, and etches the channel region under grid opening further, thus forming groove in the substrate of channel region, and then again form grid, so, the raceway groove after etching becomes thinner, being beneficial to the device forming complete depletion type, meanwhile, the effective length of raceway groove is elongated, effectively alleviate short-channel effect, the method can utilize common SOI substrate, and manufacturing process and tradition compatible, simple for process and low cost of manufacture.
In order to be better understood from technical scheme and technique effect, below with reference to flow chart 1, specific embodiment is described in detail.
First, in step S01, it is provided that SOI substrate 100, with reference to shown in Fig. 2.
In the present invention, adopting SOI substrate 100, SOI substrate 100 includes 100-3 at the bottom of top layer silicon 100-1, backing and the oxygen buried layer 100-2 between them. In an embodiment of the present invention, SOI substrate selects thick-layer SOI substrate, the namely common SOI substrate for thin layer SOI substrate, and the thickness of its top layer silicon is typically larger than 50nm, is generally the substrate of non-depletion device.
In the present embodiment, described SOI substrate 100 can carry out preceding processing operations, and described process operation can include prerinse, form well region and form isolation area 102 etc., with reference to shown in Fig. 3.
Then, in step S02, device architecture is formed on the substrate 100, with reference to shown in Fig. 3.
The device of desirable type can be formed as required, define cmos device structure in the present embodiment.
Concrete, it is possible, firstly, to by sequentially forming pseudo-gate dielectric layer 104, grid 106 and cap layers (not shown go out), then utilize lithographic technique, be patterned being formed gate regions, with reference to shown in Fig. 3; Then, deposit and perform etching and form side wall 108.
Described gate dielectric layer 104 can be thermal oxide layer or other suitable dielectric materials, for instance silicon oxide, silicon nitride etc., in one embodiment, it is possible to for silicon dioxide, it is possible to formed by the method for thermal oxide.
Described grid 106 can be non-crystalline silicon, polysilicon or silicon oxide etc., in one embodiment, it is possible to for non-crystalline silicon. In the present embodiment, this gate dielectric layer and grid are dummy grid and pseudo-gate dielectric layer, after forming device architecture, it will be removed.
Described cap layers can be nitride etc., in one embodiment, it is possible to for silicon nitride.
Described side wall 108 can have single or multiple lift structure, it is possible to by silicon nitride, silicon oxide, silicon oxynitride, carborundum, fluoride-doped silica glass, low k dielectric material and combination thereof, and/or other suitable materials are formed. In one embodiment, described side wall 108 can be the single layer structure of silicon nitride.
Then, can pass through according to desired transistor arrangement, implanted with p-type or n-type dopant or impurity are in the top layer silicon 100-1 of grid 106 both sides, certainly, normally, before forming side wall, also can form source drain extension district in top layer silicon 100-1, after doping, be annealed, to activate doping, form source-drain area 110.
Then, deposit interlayer dielectric layer material, for instance can be unadulterated silicon oxide (SiO2), doping silicon oxide (such as Pyrex, boron-phosphorosilicate glass etc.) or silicon nitride (Si3N4) etc., and carrying out flatening process, such as CMP (cmp), until removing cap layers, exposing grid 106, as it is shown on figure 3, so far define the device architecture of the present embodiment.
Then, in step S03, the grid 106 of removal devices structure, until exposed top layer silicon 100-1, to form grid opening 116, with reference to shown in Fig. 4.
In the present embodiment, it is possible to use wet etching and/or dry ecthing remove gate dielectric layer 104 and grid 106, in the particular embodiment, adopt wet etching to remove gate dielectric layer 104 and grid 106, until exposed top layer silicon, form grid opening 116, as shown in Figure 4.
Then, in step S04, (111) crystal face along top layer silicon performs etching, to form groove 118 116 times at grid opening, with reference to shown in Fig. 5.
Suitable lithographic method can be adopted so that etch (111) crystal face along top layer silicon and carry out, as such, it is possible to form groove in (111) crystal face substrate under grid opening. In the present embodiment, the method adopting anisotropic wet etch, etching agent for example with TEMAH, etching top layer silicon, by controlling etch period, (111) crystal face 119 along top layer silicon can be formed and form difform groove, for instance form the groove 118 of the inverted triangle of opening, as shown in Figure 5; Such as form the groove 118-1 of not completely open inverted triangle, as shown in fig. 5-1; Such as form the groove 118-2 of the rhombus of opening, as shown in Fig. 5-2; Such as forming the groove 118-3 of the inverted trapezoidal of opening, as shown in Fig. 5-3, in this etching, the time used is shorter, and bottom, but without the pinch off because of etch rate difference, therefore defines trapezoidal pattern. Below by the groove 118 for the upside-down triangle shape in accompanying drawing 5, carry out the processing of subsequent step.
The substrate of channel region under the gate defines this groove 118, the thickness making channel region reduces so that can form fully-depleted device by common SOI substrate, and add the effective length of raceway groove, it is easily solved short-channel effect, improves the performance of device.
Then, in step S05, fill grid opening and groove, again to form grid 112, with reference to shown in Figure 10.
In the present embodiment, again formed between grid 112, also carrying out oxidation and removed the step of oxide layer, concrete, first, carry out oxidation technology, it is possible to adopt O3Oxidation technology or RTA (RapidThermalAnneal) oxidation technology, form one layer of thin oxide layer 120 on the surface of groove 118, and as shown in Figure 6, its thickness can be about 1-10nm; Then, this oxide layer 120 is removed, as shown in Figure 7. Should in this oxidation technology, it is possible to repair the boundary defect owing to bringing in above-mentioned etching groove, after removing oxide layer so that the boundary defect of flute surfaces eliminates, improve interfacial characteristics.
Then, new gate dielectric layer 122 and grid 124 are continuously formed, as shown in Figure 8. new gate dielectric layer 122 can be formed by oxidation technology or depositing technics, in oxidation technology, gate dielectric layer 122 will only be in being formed on the surface of groove, as shown in Figure 8, and in depositing technics, gate dielectric layer will be formed on the surface of groove and grid opening, gate dielectric layer can be silicon oxide or high K medium material (such as, compare with silicon oxide, there is the material of high-k) or other suitable dielectric materials, high K medium material such as hafnio oxide, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc., grid can include metal material or polysilicon or their combination, metal material is Ti such as, TiAlx��TiN��TaNx��HfN��TiCx��TaCxEtc..
Then, it is possible to complete the processing that device is follow-up traditionally, carry out the processing of device, as formed source and drain contact, gate contact and interconnection structure etc.
So far, the semiconductor device of the embodiment of the present invention is defined.
The above, be only presently preferred embodiments of the present invention, and the present invention not does any pro forma restriction.
Additionally, present invention also offers the semiconductor device that said method is formed, with reference to shown in Fig. 8, this Semiconductor substrate includes: SOI substrate 100; Device architecture on substrate 100; Wherein, being formed with groove 118 in the top layer silicon 101 of substrate, the wall of this groove is etched by (111) crystal face 119 along top layer silicon and is formed; The grid 124 of device architecture is formed in groove 118 and on groove.
Wherein, groove 118 is the del of opening, rhombus or inverted trapezoidal.
This device can be the depletion device formed in common SOI substrate, and the effective length of low cost of manufacture and raceway groove is long, effectively alleviates short-channel effect.
The above, be only presently preferred embodiments of the present invention, and the present invention not does any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but is not limited to the present invention. Any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, all may utilize the method for the disclosure above and technology contents and technical solution of the present invention is made many possible variations and modification, or be revised as the Equivalent embodiments of equivalent variations. Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the scope of technical solution of the present invention protection.
Claims (7)
1. the manufacture method of a semiconductor device, it is characterised in that including:
SOI substrate is provided;
Substrate is formed device architecture;
The grid of removal devices structure, until exposed top layer silicon, to form grid opening;
(111) crystal face along top layer silicon performs etching, to form groove under grid opening;
Fill grid opening and groove, again to form grid.
2. manufacture method according to claim 1, it is characterised in that adopt anisotropic etching to carry out wet etching along (111) crystal face of top layer silicon, to form groove under grid opening.
3. manufacture method according to claim 2, it is characterised in that etching agent is TEMAH.
4. manufacture method according to claim 1, it is characterised in that before again forming grid, further comprises the steps of: and carries out oxidation technology, to form oxide layer in flute surfaces; Remove this oxide layer.
5. manufacture method according to claim 1, it is characterised in that in the step performed etching along (111) crystal face of top layer silicon, by control etch period, the groove of formation be shaped as the del of opening, rhombus or inverted trapezoidal.
6. a semiconductor device, it is characterised in that including:
SOI substrate;
Device architecture on substrate;
Wherein, being formed with groove in the top layer silicon of substrate, the wall of this groove is etched by (111) crystal face along top layer silicon and is formed; The grid of device architecture is formed in the trench and on groove.
7. semiconductor device according to claim 6, it is characterised in that described groove is the shape of the del of opening, rhombus or inverted trapezoidal.
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| CN201410585002.1A CN105633081A (en) | 2014-10-27 | 2014-10-27 | Semiconductor device and manufacturing method thereof |
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| CN201410585002.1A CN105633081A (en) | 2014-10-27 | 2014-10-27 | Semiconductor device and manufacturing method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222694A (en) * | 2010-04-16 | 2011-10-19 | 台湾积体电路制造股份有限公司 | semiconductor device having a strained channel and method of manufacture thereof |
| CN103117220A (en) * | 2011-11-16 | 2013-05-22 | 上海华虹Nec电子有限公司 | Removal method for super junction sacrificial oxide layer |
| WO2013171892A1 (en) * | 2012-05-18 | 2013-11-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for producing same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222694A (en) * | 2010-04-16 | 2011-10-19 | 台湾积体电路制造股份有限公司 | semiconductor device having a strained channel and method of manufacture thereof |
| CN103117220A (en) * | 2011-11-16 | 2013-05-22 | 上海华虹Nec电子有限公司 | Removal method for super junction sacrificial oxide layer |
| WO2013171892A1 (en) * | 2012-05-18 | 2013-11-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for producing same |
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Application publication date: 20160601 |