CN105633079A - Semiconductor structure and manufacturing method therefor - Google Patents
Semiconductor structure and manufacturing method therefor Download PDFInfo
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- CN105633079A CN105633079A CN201510451122.7A CN201510451122A CN105633079A CN 105633079 A CN105633079 A CN 105633079A CN 201510451122 A CN201510451122 A CN 201510451122A CN 105633079 A CN105633079 A CN 105633079A
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Abstract
The invention provides a semiconductor structure and a manufacturing method therefor. The semiconductor structure can comprise a substrate, fins, multiple device gate stacks, pseudo gate stacks and a conductive material, wherein the fins extend along a first direction on the substrate; the multiple device gate stacks extend along a second direction that is intersected with the first direction on the substrate so as to be intersected with the fins; a spacer is formed on the side wall by each device gate stack; the multiple device gate stacks comprise adjacent first device gate stacks and second device gate stacks; the pseudo gate stacks are formed between the first device gate stacks and the second device gate stacks; spacers are formed on the side wall by the pseudo gate stacks; and the conductive material extends among the respective gate stacks.
Description
Technical field
The application relates to semiconductor applications, more particularly, to a kind of semiconductor structure with self-aligned source drain contact site and manufacture method thereof.
Background technology
Along with the integration density of semiconductor device improves day by day, FinFET (fin formula field effect transistor) is due to its good electric property, extensibility and receives much attention with the compatibility of manufacturing processes customary. Fig. 1 has illustrated the perspective view of example FinFET. As it is shown in figure 1, this FinFET includes: substrate 101; The fin 102 formed on the substrate 101; The gate electrode 103 intersected with fin 102, is provided with gate dielectric layer 104 between gate electrode 103 and fin 102; And sealing coat 105. In this FinFET, under the control of gate electrode 103, it is possible to specifically produce conducting channel in fin 102 in three sidewalls (figure middle left and right sidewall and roof) of fin 102, as shown by the arrows in Figure 1. That is, fin 102 is positioned at the part under gate electrode 103 serves as channel region, source region, drain region then lay respectively at channel region both sides.
In the example of fig. 1, FinFET owing to all can produce raceway groove on the three of fin 102 sidewalls, thus also referred to as 3 gate FinFETs. Additionally, it is possible to dielectric layer (such as nitride) is set between the roof and gate electrode 103 of fin 102 and forms 2 gate FinFETs, raceway groove will not now be produced on the roof of fin 102.
Along with being increasingly miniaturized of device, the size of fin is more and more less. Such as, in 22nm node technology, the width of fin can be about 10-30nm. For so little fin, accurately to realize source and drain contacts extremely difficult. Specifically, common process is by etching contact hole, forming contact site to filled conductive material in contact hole. It is extremely difficult for etching little contact hole, and is difficult to filled conductive material in so little contact hole.
Summary of the invention
The purpose of the disclosure is in that to provide a kind of semiconductor structure and manufacture method thereof at least in part, to overcome above-mentioned difficulties of the prior art at least in part.
According to an aspect of this disclosure, it is provided that a kind of semiconductor structure, including: substrate; The fin extended in a first direction on substrate; Along the second direction extension intersected with first direction thus stacking with multiple device gate that fin intersects on substrate, each device gate is stacked on sidewall and is formed with side wall, and the plurality of device gate is stacking includes that the first adjacent device gate is stacking and the second device gate is stacking; The pseudo-grid formed between and the second device gate stacking in the first device gate is stacking are stacking, and pseudo-grid are stacked on sidewall and are formed with side wall; The conductive material extended between each grid are stacking.
According to another aspect of the present disclosure, it is provided that a kind of method manufacturing semiconductor structure, including: on substrate, form the fin extended in a first direction; Forming a plurality of gate line of the second direction extension that edge intersects with first direction on substrate, described a plurality of gate line includes the device gate polar curve for forming device grids and the dummy grid line between described device gate polar curve; The sidewall of gate line is formed side wall; And between each gate line filled conductive material.
According to embodiment of the disclosure, by directly grid stacking/gate line between filled conductive material, it is possible to form self aligned source and drain contacts. This can be avoided the difficulty of etching and filling contact hole. Pseudo-grid are stacking/and dummy grid line can realize the required electric isolution of source and drain contacts of adjacent devices.
Accompanying drawing explanation
By referring to the accompanying drawing description to disclosure embodiment, above-mentioned and other purposes of the disclosure, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 illustrates the example FinFET according to prior art;
Fig. 2-6 shows according to the schematic section in multiple stages in the flow process manufacturing semiconductor structure of disclosure embodiment;
Fig. 7 illustrates the semiconductor structure according to another embodiment of the disclosure;
Fig. 8 illustrates the semiconductor structure according to the another embodiment of the disclosure.
Detailed description of the invention
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure. However, it should be understood that these descriptions are illustrative of, and it is not intended to limit the scope of the present disclosure. Additionally, in the following description, eliminate the description to known features and technology, to avoid unnecessarily obscuring the concept of the disclosure.
Various structural representations according to disclosure embodiment shown in the drawings. These figure are not drawn to scale, wherein in order to know the purpose of expression, are exaggerated some details, and are likely to eliminate some details. Various regions shown in figure, the shape of layer and relative size, the position relationship between them are merely illustrative of, reality is likely to be due to manufacturing tolerance or technical limitations and deviation to some extent, and those skilled in the art can additionally design the regions/layers with difformity, size, relative position according to actually required.
In the context of the disclosure, when one layer/element is called be positioned at another layer/element " on " time, this layer/element can be located immediately on this another layer/element, or can there is intermediate layer/element between them. If it addition, one towards in one layer/element be positioned at another layer/element " on ", then when turn towards time, this layer/element may be located at this another layer/element D score.
Fig. 2-8 shows according to the schematic section in multiple stages in the flow process manufacturing semiconductor structure of disclosure embodiment.
As shown in Fig. 2 (Fig. 2 (a) is top view, and Fig. 2 (b) is the sectional view of AA ' line along Fig. 2 (a), and Fig. 2 (c) is the sectional view of BB ' line along Fig. 2 (a)), it is provided that substrate 200. Substrate 200 can include body Semiconductor substrate such as Si, Ge, and compound semiconductor substrate is SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb such as, semiconductor-on-insulator substrate (SOI) etc. For convenience of description, it is described for body silicon substrate and silicon based material below.
On the substrate 200, multiple fin 202a, 202b and 202c that (such as, horizontal direction in figure) in the first direction extends in parallel are defined. Wherein, fin 202b is patterned to according to device design and is divided into two part 202b-1 and 202b-2. In the figure 2 example, fin 202a, 202b and 202c are shown as and substrate 200 one, a part (such as, by substrate 200 is patterned) for substrate 200 formed. But, the disclosure is not limited to this. Such as, fin 202a, 202b and 202c can pass through the other semiconductor layer formation of extension on the substrate 200. Additionally need it is noted that the layout of fin is determined according to device design, be not limited to the layout shown in Fig. 2, and the number of fin can be more or less. In the disclosure, statement " forms fin " on substrate or similar statement includes forming one or more fin by any suitable layout by any suitable mode on substrate, and statement " fin formed on substrate " or similar statement include one or more fins of any suitable layout formed on substrate by any suitable mode.
It addition, in fig. 2, the sidewall of fin 202a, 202b and 202c is shown as being exactly perpendicularly to the surface of substrate 200. It is convenient that this is only used to diagram. It is true that the sidewall of fin can tilt.
It addition, could be formed with sealing coat 204 on the substrate 200. Such as, then sealing coat 204 can be etched back by deposited oxide (such as, silicon oxide) on the substrate 200 and be formed. Before eat-back, it is possible to carry out planarization and process such as chemically mechanical polishing (CMP). This sealing coat 204 can be considered as defining shallow trench isolation (STI) in source region (that is, fin). It is to be herein pointed out in some cases, for instance substrate is SOI substrate, it is convenient to omit this sealing coat 204.
In this respect it is to be noted that just to the convenience of diagram, the top view in Fig. 2 is not drawn to scale with sectional view.
It follows that gate line (grid subsequently forming device are stacking) can be formed on the substrate 200 be formed with fin. According to embodiment of the disclosure, except by device design forming for except forming the device gate polar curve that device gate is stacking, also on-demand (as described below, for instance the source and drain contacts in adjacent devices needs to carry out isolating part) form dummy grid line. At this, so-called " puppet " gate line, refer to and be physically substantially the same with device gate polar curve, but not really for the gate line of device operation.
Specifically, it is possible in the structure shown in Fig. 2, for instance form gate dielectric material layer and layer of gate electrode material by depositing. Such as, gate dielectric material layer can include high-K gate dielectric such as HfO2����HfSiO��HfSiON��HfTaO��HfTiO��HfZrO��Al2O3��La2O3��ZrO2, any one or its combination in LaAlO; Layer of gate electrode material can include metal gate conductor such as Ti, Co, Ni, Al, W or its alloy or metal nitride etc. It addition, gate dielectric material layer can also include oxide (high-K gate dielectric is formed on this oxide) a layer thin. Between gate dielectric material layer and layer of gate electrode material, it is also possible to form work function regulating course (not shown). Alternatively, in the embodiment of application replacement gate process, gate dielectric material layer can include sacrificial gate dielectric material such as oxide, and layer of gate electrode material can include sacrificial gate conductor such as polysilicon.
In layer of gate electrode material, can pass through be coated with photoresist (not shown) and utilize mask to be exposed, then develop, it is thus achieved that the photoresist linear pattern corresponding with the gate line pattern (including device gate polar curve and dummy grid line) that will be formed. Photoetching agent pattern can include in a second direction the line segment that (such as, vertical direction in figure) is parallel to each other, and they have same or like spacing and critical size. The second direction that the first direction that fin extends extends with gate line can at an angle as 90 degree intersect.
Next, such as Fig. 3, (Fig. 3 (a) is top view, Fig. 3 (b) is the sectional view of AA ' line along Fig. 3 (a), Fig. 3 (c) is the sectional view of BB ' line along Fig. 3 (a)) shown in, linear pattern is utilized to etch such as reactive ion etching (RIE) layer of gate electrode material, to form parallel gate line 208a, 208D-a, 208D-b and 208b. At this, gate line 208b is patterned to according to device design and is divided into two part 208b-1 and 208b-2. At this, also etch gate dielectric material layer, thus the gate dielectric layer 206 obtained is only located under each gate line. Afterwards, it is possible to remove photoresist.
According to another example, it is possible to be initially formed a hard mask layer (such as, silicon nitride) in the structure shown in Fig. 2, the then photoresist of composition formed as discussed above again. Afterwards, utilize photoresist that hard mask layer is patterned, it is possible to remove photoresist. It is then possible to use the hard mask of composition, layer of gate electrode material is patterned. This hard mask can be removed, it is also possible to is retained in the gate line top obtained.
In this example, gate line 208a and 208b is will really for the device gate polar curve of device operation according to device design. In device layout, they are adjacent one another are, but design according to device, they corresponding source/drain regions (be respectively formed in fin and divide the opposite sides of gate line 208a, 208b in 202b-1,202b-2, be i.e. the left and right sides in Fig. 3 (b)) need electrically isolated from one. For this, define dummy grid line 208D-a and 208D-b between which. In this example, the sidewall of dummy grid line 208D-a and 208D-b side is substantially aligned with the sidewall that corresponding fin divides 202b-1,202b-2.
In the context of the disclosure, the structure that " adjacent gate line/grid are stacking " is adjacent one another are when referring to stacking for gate line (including device gate polar curve and dummy grid line)/grid (including stacking/pseudo-grid of device gate stacking) overall consideration, and " adjacent device gate polar curve/device gate is stacking " refer to individually consider that device gate polar curve/device gate is stacking and be left out dummy grid line/puppet grid structure adjacent one another are time stacking (, certain two device gate polar curve/device gate stacking " adjacent ", but it is stacking to would be likely to occur one or more dummy grid line/puppet grid between them).
After defining gate line, it is possible to conventionally technique processes. For example, it is possible to carry out ion implanting (forming extension area, source/drain etc.), side wall (spacer) formation etc. At this, it should be pointed out that these concrete technologies (such as ion implanting etc.), there is no direct correlation with the purport of the present invention, be not described in detail at this. They can adopt prior art to realize, it would however also be possible to employ the technology of development realizes in the future.
Fig. 4 (Fig. 4 (a) is top view, and Fig. 4 (b) is the sectional view of AA ' line along Fig. 4 (a)) has illustrated the situation after forming side wall 210 on the sidewall of gate line and forming source/drain region S/D in fin. Side wall 210 can include single or multiple lift configuration, and can include various suitable dielectric substance such as SiO2��Si3N4, any one or its combination in SiON. Between adjacent gate polar curve (including device gate polar curve and dummy grid line), the source/drain region S/D of adjacent devices can link together.
Due to as mentioned above, in this example, the sidewall of dummy grid line 208D-a and 208D-b side is substantially aligned with the sidewall that corresponding fin divides 202b-1,202b-2, thus the side wall of dummy grid line 208D-a and 208D-b side also extends into and cover the sidewall that fin divides 202b-1,202b-2.
Further, it is also possible at the surface Epitaxial growth semiconductor layer (not shown) that fin is exposed by gate line and side wall, to expand source/drain region area. According to an advantageous example, this semiconductor layer can include band stress material, to apply stress to fin (particularly channel region therein), thus improving device performance further. Specifically, for n-type device, semiconductor layer can band tension; And for p-type device, semiconductor layer can band compressive stress. Such as, when fin includes Si, semiconductor layer can include Si:C (n-type device) or SiGe (p-type device). Further, it is also possible to the exposed portion of fin is carried out silicidation, to reduce contact resistance.
Subsequently, as shown in Fig. 5 (Fig. 5 (a) is top view, and Fig. 5 (b) is the sectional view of AA ' line along Fig. 5 (a)), it is possible to such as by depositing on substrate, form conductive material 212. Conductive material 212 can be completely covered the structure shown in Fig. 4. Then, it is possible to conductive material 212 is carried out planarization process, for instance chemically mechanical polishing (CMP), until exposing each gate line (can side wall 201 be planarization halt, namely stop) when spacer material being detected. When gate line top is formed with hard mask layer, planarization halt can be hard mask layer. Then, conductive material is limited between each gate line to extend, and the contact site of the source-drain area S/D therefore formed between respective gates line. Conductive material 212 can include the contact site material that Cu, Al, W etc. are conventional, or can include the conductive material (for n-type device band tension, for p-type device band compressive stress) with stress.
According to an advantageous example, after exposing gate line, it is possible to application replacement gate process. Specifically, for instance selective etch can be passed through and remove (sacrifice) gate line and remove (sacrifice) gate dielectric layer alternatively, inside side wall 210, form grid groove. In grid groove, for instance by depositing and being etched back, it is possible to sequentially form real gate dielectric layer and real grid conductor.
It addition, before depositing conductive material 212, it is also possible to the lining (not shown) that first deposit is a layer thin. Such as, lining can include nitride, and thickness is about 10nm. This lining can be completely covered the structure shown in Fig. 4, then patterned to expose source/drain region. Then, it is possible on this lining, form conductive material.
As shown in Figure 5, in a first direction, the source-drain area S/D of adjacent cells device (each self-corresponding unit component of gate line 208a, 208b) is electrically isolated from one due to the existence of the side wall 210 on dummy grid line 208D-a and 208D-b and each of which sidewall. Thus it is possible to by corresponding contact site 212, apply the signal of telecommunication to the source-drain area S/D of adjacent cells device respectively, or therefrom draw the signal of telecommunication.
Additionally, in second direction, the source/drain region of adjacent unit component (device that such as, adjacent fin and same gate line respectively constitute) is connected to each other. Shown in top view in Fig. 6, it is possible to carry out being dielectrically separated from portion 214 between the presumptive area place formation device isolated at needs according to layout. As such, it is possible to by the source/drain region contact site electric isolution of adjacent cells device in second direction. For example, it is possible to conductive material 212 is cut off at presumptive area place, to realize this electric isolution. Certainly, this isolation can also extend through gate line, also can electrically insulate so that the grid of adjacent cells device are stacking in second direction. As a rule, inactive regions (field) top between fin is as cut off on STI, and the width of otch is generally 1-10nm. When etching otch, it is possible to the sealing coat 204 of lower section is stop-layer. Can to filling dielectric material in otch to form device interval far from portion 214; Or, the interlevel dielectric layer that otch can be subsequently formed is filled.
Or, really not cutting off in the above process, and can be by such as injecting to incision site oxygen, making the material layer oxidation exposed, thus forming the oxide of insulation. Certainly, the element of injection is not limited to oxygen, and those skilled in the art according to the conductive material used, can also suitably select gas or the chemical substance injected, make them react thus generating insulant, and therefore realize electric isolution.
Thus, the semiconductor structure according to disclosure embodiment is obtained. As illustrated in Figures 5 and 6, this semiconductor structure can include being formed on the substrate 200 in the first direction (such as, horizontal direction in figure) fin (202b) that extends and formed on the substrate 200 along the second direction intersected with first direction (such as, vertical direction in figure) multiple device gate stacking (208a/206,208b/206) of extending, the sidewall (such as, the sidewall of the left and right sides in figure) that device gate is stacking is formed with side wall 210. Each device gate stacking with under fin match, obtain unit component (FinFET). This semiconductor structure includes multiple such unit component, can connect by device design between each unit device. This semiconductor structure be additionally may included in adjacent device gate stacking between the pseudo-grid stacking (208D-a/206,208D-b/206) that formed, the sidewall (such as, the sidewall of the left and right sides in figure) that pseudo-grid are stacking is also formed with side wall 210. Conductive material 212 between each grid are stacking (specifically, device gate is stacking and device gate stacking between, between the stacking and pseudo-grid of device gate are stacking, and/or the pseudo-stacking and pseudo-grid of grid stacking between) extend, and be therefore formed into the contact site of the source/drain region of each unit device. In this example, conductive material 212 can be full of the space between adjacent gate stacks.
Additionally, in this example, fin 202b is divided into two part 202b-1 and the 202b-2 (can certainly be divided into the more parts being isolated from each other) being isolated from each other. The stacking 208a/206 of device gate intersects with Part I 202b-1, and the stacking 208b/206 of device gate intersects with Part I 202b-2. The pseudo-stacking 208D-a/206 of grid can form the edge at Part I 202b-1, thus it extends on the sidewall of Part I 202b-1 towards the side wall of the pseudo-stacking 208D-b/206 side of grid. Equally, the pseudo-stacking 208D-b/206 of grid can form the edge at Part II 202b-2, thus it extends on the sidewall of Part I 202b-2 towards the side wall of the pseudo-stacking 208D-a/206 side of grid.
For realizing required isolation, this semiconductor device can also include the isolation part 214 at presumptive area place. As shown in Figure 6, the source and drain contacts of some unit component that second direction is adjacent is isolated by corresponding isolation part 214. These isolation parts 214 may be located on sealing coat 204 (or, STI).
In the embodiment above, between adjacent device gate stacking (208a/206,208b/206), define two pseudo-grid stacking (208D-a/206,208D-b/206). But, the disclosure is not limited to this. For example, it is possible to it is stacking to form more or less of pseudo-grid. Additionally, the edge that the stacking position of pseudo-grid is also not necessarily limited to fin is directed at. Fig. 7 illustrates between adjacent device gate stacking (208a/206,208b/206), forms the example of single pseudo-grid stacking (208D/206). Due to the existence of the side wall 210 on the pseudo-stacking 208D/206 of grid and its sidewall, the source and drain contacts 212 of adjacent unit component (unit component that the unit component of the stacking 208a/206 of device gate and fin 202b-1 composition and the stacking 208b/206 of device gate and fin 202b-2 are constituted) is electrically isolated from one. Also show side wall 210 in the figure 7 to be formed on the sidewall of fin 202b-1 and 202b-2.
Fig. 8 illustrates another sample semiconductor structure. As shown in Figure 8, between the adjacent devices grid stacking (208a/206,208b/206) that continuous print fin 202 intersects, the equally possible pseudo-grid of formation stacking (208D/206). Due to the existence of the side wall 210 on the pseudo-stacking 208D/206 of grid and its sidewall, the source and drain contacts 212 of adjacent unit component (unit component that the stacking 208a/206 of device gate is constituted with fin 202 with the unit component of fin 202 composition and the stacking 208b/206 of device gate) is electrically isolated from one. In this example, the pseudo-stacking 208D/206 of grid can also constitute pseudo-device with fin 202. In this case, it is also possible to by applying certain control voltage to the pseudo-stacking 208D/206 of grid, make this puppet device end, strengthen the electric isolution between the unit of both sides.
In the above description, the ins and outs such as the composition of each layer, etching are not described in detail. It should be appreciated to those skilled in the art that by various technological means, the layer of required form, region etc. can be formed. It addition, in order to form same structure, those skilled in the art can be devised by method not identical with process as described above. Although it addition, respectively describing each embodiment above, but it is not intended that the measure in each embodiment can not be advantageously combined use.
Embodiment of this disclosure is described above. But, the purpose that these embodiments are merely to illustrate that, and it is not intended to restriction the scope of the present disclosure. The scope of the present disclosure is limited by claims and equivalent thereof. Without departing from the scope of the present disclosure, those skilled in the art can make multiple replacement and amendment, and these substitute and amendment all should fall within the scope of the present disclosure.
Claims (10)
1. a semiconductor structure, including:
Substrate;
The fin extended in a first direction on substrate;
Along the second direction extension intersected with first direction thus stacking with multiple device gate that fin intersects on substrate, each device gate is stacked on sidewall and is formed with side wall, and the plurality of device gate is stacking includes that the first adjacent device gate is stacking and the second device gate is stacking;
The pseudo-grid formed between and the second device gate stacking in the first device gate is stacking are stacking, and pseudo-grid are stacked on sidewall and are formed with side wall;
The conductive material extended between each grid are stacking.
2. semiconductor structure according to claim 1, wherein, fin includes the Part I and the Part II that are isolated from each other, and the first device gate is stacking to intersect with Part I, and the second device gate is stacking intersects with Part II.
3. semiconductor structure according to claim 2, wherein, it is formed with two pseudo-grid stacking between and the second device gate stacking in the first device gate is stacking, stacking including the first pseudo-grid and the second puppet grid are stacking, the stacking side wall towards the second pseudo-stacking side of grid of first pseudo-grid extends on the sidewall of Part I of fin, and the stacking side wall towards the first pseudo-stacking side of grid of the second pseudo-grid extends on the sidewall of Part II of fin.
4. semiconductor structure according to claim 1, also includes: isolation part, and described conductive material segregation is the part being isolated from each other.
5. semiconductor structure according to claim 1, wherein, described conductive material bands stress.
6. the method manufacturing semiconductor structure, including:
Substrate is formed the fin extended in a first direction;
Forming a plurality of gate line of the second direction extension that edge intersects with first direction on substrate, described a plurality of gate line includes the device gate polar curve for forming device grids and the dummy grid line between described device gate polar curve;
The sidewall of gate line is formed side wall; And
Filled conductive material between each gate line.
7. method according to claim 6, wherein, filled conductive material includes:
At deposited on substrates conductive material; And
The substrate being deposited with conductive material is planarized, until exposing gate line.
8. method according to claim 6, also includes:
In formation isolation part, certain area place, conductive material to be divided into the part being isolated from each other.
9. method according to claim 6, wherein, fin includes the Part I and the Part II that are isolated from each other, the first device gate polar curve in described gate line intersects with Part I, the second device gate polar curve in described gate line intersects with Part II, there is at least one dummy grid line between the first and second device gate polar curves.
10. method according to claim 9, wherein, there are two dummy grid lines between the first and second device gate polar curves, including the first dummy grid line and the second dummy grid line, first dummy grid line extends on the sidewall of Part I of fin towards the side wall of the second dummy grid line side, and the second dummy grid line extends on the sidewall of Part II of fin towards the side wall of the first dummy grid line side.
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