CN105632907A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN105632907A CN105632907A CN201410587117.4A CN201410587117A CN105632907A CN 105632907 A CN105632907 A CN 105632907A CN 201410587117 A CN201410587117 A CN 201410587117A CN 105632907 A CN105632907 A CN 105632907A
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Abstract
The present invention provides a semiconductor device manufacturing method. The method comprises: a substrate is provided, and an adhesion layer and an electrode material layer are formed in order on the substrate; a protective layer is formed for coating the peripheral edges of the electrode material layer; a patterning first photoresist layer is formed on the surface of exposed electrode material layer; the patterning first photoresist layer and the protective layer are masks, and the electrode material layer and the adhesion layer are etched to form electrodes; and the patterning first photoresist layer is removed. According to the invention, the problem is avoided that the edge etching rate of an electrode material layer and an adhesion layer is higher than the center etching rate of the electrode material layer and the adhesion layer in the process of wet etching, so that weak spots cannot be generated at the edges of a wafer and electrode peeling cannot occur, therefore the yield rate and the performances of a device are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the manufacture method particularly to a kind of semiconductor device.
Background technology
Gold is widely used in the electrical connection material in semiconductor device due to its excellent transport properties and chemical inertness. But owing to gold adsorptivity in nonmetallic materials is poor, cause preparing thicker gold electrode layer, thus have impact on the conductivity performance of electrode. In addition, the adsorptivity that gold is poor on nonmetal film, also have a strong impact on the retrofit to gold electrode, be unfavorable for the gold miniaturization as electrode device. Currently in order to the problem solving gold electrode adsorptivity difference, when often adopting micro-synthesis technique such as process deposits such as magnetron sputtering and evaporation to form gold electrode, thereunder form one layer of adhesion layer (such as, chromium), to increase the adhesive force between gold electrode from different interfaces.
In process prepared by gold electrode, in addition it is also necessary to it is carried out wet etching, and wet etching is higher than the etch rate of crystal circle center for the etch rate of the Au/Cr of crystal round fringes. Therefore in the weak spot of crystal round fringes, be then likely to cause the stripping of gold electrode, and then affect performance and the yield of device.
Therefore, it is necessary to propose the manufacture method of a kind of new semiconductor device, to solve above-mentioned technical problem.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will further describe in detailed description of the invention part. The Summary of the present invention is not meant to the key feature and the essential features that attempt to limit technical scheme required for protection, does not more mean that the protection domain attempting to determine technical scheme required for protection.
In order to overcome the problem that presently, there are, the present invention provides the manufacture method of a kind of semiconductor device, including:
Substrate is provided, sequentially forms adhesion layer and electrode material layer on the substrate;
Form the protective layer of the edge covering described electrode material layer;
The surface of the described electrode material layer exposed is formed the first photoresist layer of patterning;
With the first photoresist layer of described patterning and described protective layer for mask, etch described electrode material layer and adhesion layer, to form electrode;
Remove the first photoresist layer of described patterning.
Further, the material of described adhesion layer is Cr.
Further, the material of described electrode material layer is gold.
Further, described protective layer is toroidal.
Further, the method forming described protective layer comprises the following steps:
Formation of deposits protection material layer on described electrode material layer;
Forming the second photoresist layer of patterning on described protection material layer, the second photoresist layer of wherein said patterning covers the marginal area of described protection material layer;
With the second photoresist layer of described patterning for mask, etch described protective layer material layer until exposing described electrode material layer, to form described protective layer;
Remove the second photoresist layer of described patterning.
Further, magnetron sputtering technique is adopted to form described adhesion layer and electrode material layer.
Further, the material of described protective layer is oxide.
Further, the thickness of described protective layer is
Further, before forming described adhesion layer and electrode material layer, it is additionally included in described substrate the step of formation of deposits dielectric layer.
Further, adopt the method for wet etching that described adhesion layer and described electrode material layer are performed etching.
In sum, manufacture method according to the present invention, in wet etching process, avoid the generation of the etch rate of the adhesion layer for edge and the electrode material layer problem higher than the etch rate at center, therefore weak spot will not be produced at the edge of wafer, cause stripping electrode, and then improve yield and the performance of device.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention. Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining principles of the invention.
In accompanying drawing:
Figure 1A-1D illustrates that the processing technology of existing gold electrode implements the generalized section of obtained device successively;
Fig. 2 A-2G illustrates that the embodiment of the invention implements the generalized section of the obtained device of step successively;
Fig. 3 illustrates that the embodiment of the invention implements the process chart of step successively.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention. It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more. In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to embodiments presented herein. On the contrary, provide these embodiments will make openly thoroughly with complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, in order to clear, the size in Ceng He district and relative size are likely to be exaggerated. Same reference numerals represents identical element from start to finish.
It is understood that, when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or during layer, its can directly on other element or layer, adjacent thereto, be connected or coupled to other element or layer, or can there is element between two parties or layer. On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or during layer, then be absent from element between two parties or layer. Although it should be understood that and term first, second, third, etc. can being used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not be limited by these terms. These terms are used merely to distinguish an element, parts, district, floor or part and another element, parts, district, floor or part. Therefore, without departing under present invention teach that, the first element discussed below, parts, district, floor or part are represented by the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of shown in description figure a element or feature and other element or feature for convenient description. It should be understood that except the orientation shown in figure, spatial relationship term is intended to also include the different orientation of the device in using and operating. Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ". Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be included. Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
As used herein term only for purpose of describing specific embodiment and the restriction not as the present invention. When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural form, unless context is expressly noted that other mode. It is also to be understood that term " composition " and/or " including ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but be not excluded for one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation. When using at this, term "and/or" includes any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to the technical scheme that the explaination present invention proposes. Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions, the present invention can also have other embodiments.
Below with reference to Figure 1A-1D, the manufacture method of existing gold electrode is made a brief description.
First, as shown in Figure 1A, it is provided that substrate 100, formation of deposits dielectric layer 101 in described substrate 100. Described substrate 100 is Silicon Wafer.
Then, as shown in Figure 1B, described dielectric layer 101 sequentially forms adhesion layer and electrode material layer 102. Described adhesion layer is Cr, and described electrode material layer is Au.
Then, as shown in Figure 1 C, described electrode material layer 102 is formed the photoresist layer 103 of patterning.
Then, as shown in figure ip, with the photoresist layer 103 of described patterning for mask, adopt the method for wet etching that described electrode material layer and adhesion layer are performed etching, to form gold electrode 102a. In this step, the etch rate for the Au/Cr of crystal round fringes is higher than the etch rate of crystal circle center. Therefore in the weak spot of crystal round fringes, be then likely to cause the stripping of gold electrode, and then affect performance and the yield of device.
Existence in view of the above problems, the present invention proposes a kind of new manufacture method.
[exemplary embodiment]
Below with reference to Fig. 2 A-2G and Fig. 3, the manufacture method of the gold electrode of the present invention is described in detail.
First, as shown in Figure 2 A, it is provided that substrate 200, formation of deposits dielectric layer 201 in described substrate 200.
Described substrate 200 can be any semi-conducting material containing silicon, for instance Silicon Wafer, it is also possible to for substrate of glass, long substrate or the single crystal substrates etc. having nonmetal film material.
The material of described dielectric layer 201 can be silicon oxide (SiO2) or silicon oxynitride (SiON). The oxidation technology known by those skilled in the art such as furnace oxidation, rapid thermal annealing oxidation (RTO), original position steam oxidation (ISSG) etc. can be adopted to form the dielectric layer of silicon oxide material. Silicon oxide being performed nitriding process and can form silicon oxynitride, wherein, described nitriding process can be that high temperature furnace pipe nitrogenizes, rapid thermal annealing nitrogenizes or pecvd nitride, it is, of course, also possible to adopt other nitriding process, repeats no more here.
Then, as shown in Figure 2 B, described dielectric layer 201 sequentially forms adhesion layer and electrode material layer 202.
In order to simplicity, adhesion layer and electrode material layer only illustrate with one layer, it is conceivable that adhesion layer and electrode material layer can be the retes of two kinds of different materials, adhesion layer is positioned at the lower section of electrode material layer.
The formation process forming described adhesion layer and described electrode material layer 202 can adopt any prior art well known to those skilled in the art, for instance: the techniques such as electron beam evaporation plating, chemical vapour deposition (CVD), magnetron sputtering or physical vapour deposition (PVD). In the present embodiment, it is preferred that select magnetron sputtering.
Alternatively, the material of described adhesion layer is Cr, and described electrode material layer is Au. Exemplarily, the thickness of described adhesion layer isThe thickness of described electrode material layer isAbove-mentioned thickness range is only exemplarily, can be adjusted according to practical situation.
In one example, substrate is put into many targets and spatters in magnetron sputtering cavity altogether, a sputtering target is installed crome metal target, a sputtering target is installed gold target material. First crome metal target is sputtered, form predetermined thickness (such as,) layers of chrome as adhesion layer. Again gold target material is sputtered, form predetermined thickness (such as,) layer gold as electrode material layer.
Then, as shown in Figure 2 C, formation of deposits protection material layer 203 on described electrode material layer 202.
Protection material layer 203 can include any of several dielectric substances. Limiting examples includes oxide, nitride and nitrogen oxides, especially, and the oxide of silicon, nitride and nitrogen oxides, but do not include the oxide of other elements, nitride and nitrogen oxides. It is preferred that described protection material layer is oxide. Alternatively, the thickness of described protection material layer 203 is 500��1500 angstroms. Can use and include but not limited to: the method for chemical gaseous phase depositing process and physical gas-phase deposite method forms protection material layer 203.
Then, as shown in Figure 2 D, forming the second photoresist layer 204 of patterning on described protection material layer 203, the second photoresist layer 204 of wherein said patterning covers the marginal area of described protection material layer 203. The left figure of Fig. 2 D is generalized section, and the right figure of Fig. 2 D is top view, by top view it can be seen that the second photoresist layer 204 of patterning is in annular, covers the marginal area of described protection material layer 203. But being not limited merely to toroidal, it can be different according to the shape of substrate or electrode material layer, for instance when substrate is square, then electrode material layer is also square, and accordingly, the second photoresist layer being positioned at the patterning of edge surrounding can be block form.
Then, as shown in Figure 2 E, with the second photoresist layer 204 of described patterning for mask, described protection material layer 203 is etched until exposing described electrode material layer 202, to form the protective layer 203a of the edge covering described electrode material layer.
Specifically, the described etching to described protection material layer 203 both can select dry etching can also adopt wet etching. Dry etching can adopt the anisotropic etching method based on carbon fluoride gas. Wet etching can adopt hydrofluoric acid solution, for instance Fluohydric acid. buffer solution (buffersolutionofhydrofluoricacid (BHF)) or buffered oxide etch agent (bufferoxideetchant (BOE)). In this enforcement, it is preferred that adopt wet method lithography that described protection material layer 203 is performed etching.
Exemplarily, when described substrate is circular (such as, Silicon Wafer), described protective layer is toroidal. It is not limited to toroidal, it can also be other square frame-shaped, or polygonal annular, is specifically dependent upon the shape of electrode material layer.
After forming described protective layer 203a, remove the second photoresist layer of described patterning. Any applicable method well known to those skilled in the art can be adopted to remove the second photoresist layer of described patterning, for instance cineration technics etc.
Then, as shown in Figure 2 F, the surface of the described electrode material layer 202 exposed is formed the first photoresist layer 205 of patterning. First photoresist layer 205 definition of described patterning has the pattern of electrode.
Then, as shown in Figure 2 G, with the first photoresist layer 205 of described patterning and protective layer 203a for mask, described adhesion layer and electrode material layer 202 are etched, to form electrode 202a.
Alternatively, the thickness of described first photoresist layer is 20000��60000 angstroms. After definition can be adopted to have the mask plate of electrode pattern that the first photoresist layer is exposed and is developed, form the first photoresist layer 205 of patterning.
Exemplarily, adopt the method for wet etching that described adhesion layer and electrode material layer 202 are performed etching. In one example, when described adhesion layer is Cr, and electrode material layer is Au, the solution of described wet etching is chloroazotic acid, it is also possible to be the solution including I2 and KI. In wet etching process; owing to the first photoresist layer 205 patterned and protective layer 203a are collectively as mask; avoid the generation of the etch rate of the adhesion layer for edge and the electrode material layer problem higher than the etch rate at center; therefore defect will not be produced at the edge of wafer, cause stripping electrode problem.
Also including the step of the first photoresist layer and the protective layer removing described patterning afterwards, therefore not to repeat here.
In sum, manufacture method according to the present invention, in wet etching process, avoid the generation of the etch rate of the adhesion layer for edge and the electrode material layer problem higher than the etch rate at center, therefore weak spot will not be produced at the edge of wafer, cause stripping electrode, and then improve yield and the performance of device.
With reference to Fig. 3, illustrated therein is the flow chart of the step that method according to embodiments of the present invention is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 301, it is provided that substrate, adhesion layer and electrode material layer are sequentially formed on the substrate;
In step 302, the protective layer of the edge covering described electrode material layer is formed;
In step 303, the surface of the described electrode material layer exposed is formed the first photoresist layer of patterning;
In step 304, with the first photoresist layer of described patterning and described protective layer for mask, described electrode material layer and adhesion layer are etched, to form electrode;
In step 305, the first photoresist layer of described patterning is removed.
The present invention is illustrated already by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments. In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within present invention scope required for protection. Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, including:
Substrate is provided, sequentially forms adhesion layer and electrode material layer on the substrate;
Form the protective layer of the edge covering described electrode material layer;
The surface of the described electrode material layer exposed is formed the first photoresist layer of patterning;
With the first photoresist layer of described patterning and described protective layer for mask, etch described electrode material layer and adhesion layer, to form electrode;
Remove the first photoresist layer of described patterning.
2. manufacture method according to claim 1, it is characterised in that the material of described adhesion layer is Cr.
3. manufacture method according to claim 1, it is characterised in that the material of described electrode material layer is gold.
4. manufacture method according to claim 1, it is characterised in that described protective layer is toroidal.
5. manufacture method according to claim 1, it is characterised in that the method forming described protective layer comprises the following steps:
Formation of deposits protection material layer on described electrode material layer;
Forming the second photoresist layer of patterning on described protection material layer, the second photoresist layer of wherein said patterning covers the marginal area of described protection material layer;
With the second photoresist layer of described patterning for mask, etch described protective layer material layer until exposing described electrode material layer, to form described protective layer;
Remove the second photoresist layer of described patterning.
6. manufacture method according to claim 1, it is characterised in that adopt magnetron sputtering technique to form described adhesion layer and electrode material layer.
7. manufacture method according to claim 1, it is characterised in that the material of described protective layer is oxide.
8. manufacture method according to claim 1, it is characterised in that the thickness of described protective layer is
9. manufacture method according to claim 1, it is characterised in that before forming described adhesion layer and electrode material layer, is additionally included in described substrate the step of formation of deposits dielectric layer.
10. manufacture method according to claim 1, it is characterised in that adopt the method for wet etching that described adhesion layer and described electrode material layer are performed etching.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111740717A (en) * | 2020-02-10 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device and method of forming the same |
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| CN1118110A (en) * | 1994-06-22 | 1996-03-06 | Lg电子株式会社 | Method of forming metal thin film of semiconductor device |
| JP2000299559A (en) * | 1999-04-12 | 2000-10-24 | Fujitsu Ten Ltd | Power module substrate |
| US20050014364A1 (en) * | 2003-07-18 | 2005-01-20 | Infineon Technologies North America Corp. | Method of suppressing the effect of shining spots present at the edge of a wafer |
| CN101916722A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for preventing metallic coatings at edges of wafers from peeling |
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- 2014-10-28 CN CN201410587117.4A patent/CN105632907B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1118110A (en) * | 1994-06-22 | 1996-03-06 | Lg电子株式会社 | Method of forming metal thin film of semiconductor device |
| JP2000299559A (en) * | 1999-04-12 | 2000-10-24 | Fujitsu Ten Ltd | Power module substrate |
| US20050014364A1 (en) * | 2003-07-18 | 2005-01-20 | Infineon Technologies North America Corp. | Method of suppressing the effect of shining spots present at the edge of a wafer |
| CN101916722A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for preventing metallic coatings at edges of wafers from peeling |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111740717A (en) * | 2020-02-10 | 2020-10-02 | 中芯集成电路制造(绍兴)有限公司 | Semiconductor device and method of forming the same |
| CN111740717B (en) * | 2020-02-10 | 2024-01-05 | 绍兴中芯集成电路制造股份有限公司 | Semiconductor device and method of forming the same |
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