CN105632902B - A kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate - Google Patents
A kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate Download PDFInfo
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- CN105632902B CN105632902B CN201511011062.3A CN201511011062A CN105632902B CN 105632902 B CN105632902 B CN 105632902B CN 201511011062 A CN201511011062 A CN 201511011062A CN 105632902 B CN105632902 B CN 105632902B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000013078 crystal Substances 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 235000012149 noodles Nutrition 0.000 claims abstract description 11
- 230000000694 effects Effects 0.000 claims abstract description 10
- 238000001816 cooling Methods 0.000 claims abstract description 9
- 238000001994 activation Methods 0.000 claims description 10
- 238000012545 processing Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000009916 joint effect Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 112
- 230000003028 elevating effect Effects 0.000 description 8
- 239000004519 grease Substances 0.000 description 5
- 229920001296 polysiloxane Polymers 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 235000014347 soups Nutrition 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005411 Van der Waals force Methods 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910008051 Si-OH Inorganic materials 0.000 description 1
- 229910006358 Si—OH Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-L Sulfate Chemical compound [O-]S([O-])(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-L 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005660 hydrophilic surface Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005057 refrigeration Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002352 surface water Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
A kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, step are：Wafer is fitted on wafer pressure head → huyashi-chuuka (cold chinese-style noodles) and the wafer pressure head of semiconductor chilling plate fit to carry out being bonded under wafer cooling → ram pressures effect → hot face and the wafer pressure head of semiconductor chilling plate fit to wafer heating → annealing.The huyashi-chuuka (cold chinese-style noodles) that one aspect of the present invention passes through semiconductor chilling plate, the bonding process of wafer is implemented to intervene, the temperature of wafer is reduced in thermo-conducting manner, make the gas liquefaction near crystal column surface, then under certain external force and the effect of hydrone double factor, the R OH at originally empty is connected by the bridge joint effect of hydrone, empty formation is bonded in advance to reach reduction or even eradicate wafer；On the other hand by the hot face of semiconductor chilling plate, the temperature for being bonded wafer is raised in thermo-conducting manner, makes it complete to anneal at a certain temperature, to reach the purpose of the quantity and increase wafer bonding boundary strength that further reduce cavity.
Description
Technical field
The invention belongs to field of semiconductor manufacture, is related to one kind and utilizes semiconductor chilling plate to carry out the controllable wafer key of high/low temperature
The method of conjunction.
Background technology
Manufacturing industry is high performance simultaneously in pursuit device in recent years, and multifunction electronic/optics/biomedical devices integrate
Also as one of key drivers of novel electronic product.Connection（Also known as " it is bonded "）Technique is to integrate diversification complication system
Irreplaceable important step.As semiconductor process technique constantly promotes, manufacturing industry towards high-volume low cost direction
Development, because the wafer direct bonding of large area can simplify device Making programme, production cost is reduced, increasingly by industrial circle institute
Concern.
Traditional wafer bond techniques be using the solution such as the RCA crystal column surface clean to polishing carry out cleaning formed it is hydrophilic
Surface, then at room temperature（~25 DEG C）Two wafers with water-wetted surface are joined together in atmospheric environment, the process
It is referred to as pre- bonding.The Van der Waals force between the water molecule layer of two crystal column surfaces absorption is only relied on due to the wafer after pre- bonding
Or the effect of hydrogen bond, bond strength is very weak at room temperature, needs that the wafer after pre- bonding exists using annealing process after bonding
The bond strength that some hours can reach enough is heated in the range of 100~800 DEG C.Up to now the bonding method developed
The optimization to annealing process is mainly focused on bonding apparatus（Such as heating-up temperature, annealing time, heating environment etc.）.And annealing
Pre- bonding process before technique is most important.Because wafer has certain warpage in itself（~10 microns）, pre- bonding process
In often because crystal column surface Water Molecular Adsorption deficiency, gap is excessive between the crystal column surface of warpage（More than Van der Waals force or hydrogen
The sphere of action of key）, which results in the wafer after pre- bonding to have the non-bond area of large area and defect.And these problems only according to
The continuous more difficult improvement of annealing process rearward.
Therefore, the various problems that above-mentioned wafer low-temperature-direct-bonding occurs how are overcome to be caused as those skilled in the art
Power is in the direction of research.
The content of the invention
For above-mentioned problem, the controllable wafer of high/low temperature is carried out using semiconductor chilling plate the invention provides a kind of
The method of bonding.
The purpose of the present invention is achieved through the following technical solutions：
A kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, wafer is realized according to following steps
Direct Bonding：Wafer is fitted on wafer pressure head → and huyashi-chuuka (cold chinese-style noodles) and the wafer pressure head of semiconductor chilling plate fit and wafer cooled
Under the effect of → ram pressures be bonded → hot face and the wafer pressure head of semiconductor chilling plate fit to wafer heating → to crystalline substance
Circle is annealed, and specific implementation step is as follows：
First, to the first wafer and the second crystal column surface is cleaned respectively and activation process；
2nd, the first wafer and the second wafer crossed cleaning and activation process are fitted in the first wafer pressure head and second respectively
On wafer pressure head；
3rd, it is bonded by the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate with wafer pressure head and the first wafer and the second wafer is carried out at cooling
Reason（- 25 DEG C are cooled to from 25 DEG C）；
4th, in ram pressures（0~300 kgf）It is bonded the first wafer and the second wafer under effect；
5th, the wafer for being bonded para-linkage with wafer pressure head by the hot face of semiconductor chilling plate is moved back at a certain temperature
Fire processing（>100 DEG C, 1 ~ 48 hour）.
In the present invention, the size of first wafer and the second wafer is any.
In the present invention, first wafer and the second wafer can be identical size or different sizes.
In the present invention, first wafer and the second wafer can be same material or foreign material.
In the present invention, the first wafer pressure head and the second wafer pressure head can be arbitrary shapes.
In the present invention, the method for the activation process includes：Wet-process activation processing, dry activation processing and plasma method
Activation process etc..
In the present invention, it is bonded by the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate with wafer pressure head to the first wafer and the progress of the second wafer
During cooling processing, it is that wafer is dropped in thermo-conducting manner by the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate to implement cooling to wafer
Temperature.
In the present invention, it is bonded by the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate with wafer pressure head to the first wafer and the progress of the second wafer
During cooling processing, the first wafer and the second wafer can be reduced to mutually synthermal, can also be reduced to different temperatures.
In the present invention, the wafer of para-linkage is bonded at a certain temperature with wafer pressure head by the hot face of semiconductor chilling plate
When being made annealing treatment, it is that wafer is carried out in thermo-conducting manner by the hot face of semiconductor chilling plate to implement heating to wafer
Heating.
In the present invention, the wafer of para-linkage is bonded at a certain temperature with wafer pressure head by the hot face of semiconductor chilling plate
When being made annealing treatment, the first wafer and the second wafer can be increased to mutually synthermal, can also be increased to different temperatures.
In the present invention, the temperature of wafer can be reduced to the scope of -50 DEG C of environment temperature in bonding process.
In the present invention, the heating-up temperature after bonding can reach the scope of+80 DEG C of environment temperature.
In the present invention, the local humidity of the gas near crystal column surface can be regulated and controled in bonding process, Local Phase
Humidity can be controlled 40~100%（Vapor dew point）In the range of.
One aspect of the present invention is implemented to intervene, with heat transfer by the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate to the bonding process of wafer
Mode reduce the temperature of wafer, make the gas liquefaction near crystal column surface, so as to improve the local humidity of atmosphere residing for wafer,
Then under the increased hydrone double factor effect of certain external force and institute, the bridge that makes the R-OH originally at cavity pass through hydrone
The effect of connecing connects, to reach the formation for reducing or even eradicating wafer and be bonded cavity in advance；On the other hand semiconductor refrigerating is passed through
The hot face of piece, raises the temperature for being bonded wafer in thermo-conducting manner, makes it complete to anneal at a certain temperature, to reach
Further reduce the quantity in cavity and the purpose of increase wafer bonding boundary strength.
Brief description of the drawings
Fig. 1 is pressure head side sectional view；
Fig. 2 is being bonded for Si wafers and pressure head；
Fig. 3 is that the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate is bonded with wafer pressure head；
Fig. 4 is that Si wafers are bonded in advance；
Fig. 5 is that the hot face of semiconductor chilling plate is bonded with wafer pressure head；
In figure：1- wafer pressure heads；2- semiconductor chilling plates；3- semiconductor chilling plate fixed mounts；4- lifting screws；5- heat conduction
Silicone grease；The heating face of 6- semiconductor chilling plates；The chill surface of 7- semiconductor chilling plates；8- vacuum soup sticks；9-Si wafers.
Embodiment
Technical scheme is further described below in conjunction with the accompanying drawings, but is not limited thereto, it is every to this
Inventive technique scheme is modified or equivalent substitution, without departing from the spirit and scope of technical solution of the present invention, all should cover
In protection scope of the present invention.
The invention provides a kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, specific implementation
Step is as follows：
（1）Materials：
The first wafer, the second wafer, the first wafer pressure head required for preparing experiment, the second wafer pressure head, semiconductor system
Cold, heat-conducting silicone grease and the experimental article related to activation process etc..
（2）Coated with thermally conductive silicone grease：
To the uniform coated with thermally conductive silicone grease of upper and lower surface of semiconductor chilling plate, it is easy to semiconductor chilling plate to wafer pressure head
Transmit heat and absorb heat.
（3）Clamping semiconductor chilling plate：
As shown in figure 1, wafer indenter device is mainly by wafer pressure head 1, semiconductor chilling plate fixed mount 3, elevating lever 4 and true
The part of suction bar 8 four forms, wherein, semiconductor chilling plate fixed mount 3 is located at the hollow position of wafer pressure head 1, and elevating lever 4 is perpendicular
Nogata can only rotate to being fixed on wafer pressure head 1.Semiconductor chilling plate fixed mount 3 and elevating lever 4 are with screw thread
Relation is combined together, and forms screw pair.The axis of vacuum soup stick 8 and the axis of wafer pressure head 1 coincide, and and wafer
The front end of pressure head 1 forms thread seal connection.When elevating lever 4 rotates, the two can be made to produce relative motion, because elevating lever 4 exists
Vertical direction is fixed, so can move up and down semiconductor chilling plate fixed mount 3.The effect of suction is produced in vacuum soup stick 8
Under, wafer can be attracted on wafer pressure head 1.Semiconductor chilling plate 2 is fixed on the semiconductor system inside wafer indenter device
On cold fixed mount 3, when semiconductor chilling plate 2 is being passed through 12V or so direct currents, refrigeration can be produced respectively in its upper and lower surface
Face 6 and heating face 7.As needed, starting elevating lever 4 drives semiconductor chilling plate fixed mount 3 to move up, and
Mobile terminating point is in close contact with wafer pressure head 1 by heat-conducting silicone grease 5, real to wafer pressure head 1 in thermo-conducting manner
Apply the control of cooling and heating.
（4）Si wafer cleanings and activation：Si wafers are immersed into acetone, and with certain time is cleaned by ultrasonic, remove Si wafers
A certain amount of organic matter in surface, then uses deionized water rinsing；Again by Si wafers be immersed at room temperature (~ 25 DEG C) mixing
H2SO4+H2O2（3:1）Mixed solution 10 minutes, the impurity particle of Si crystal column surfaces is set to generate the sulfate for being dissolved in water, Ran Houyong
A large amount of deionized water rinsing Si crystal column surfaces；Finally, blown 1 ~ 2 minute using nitrogen gun and dry up crystal column surface, remove wafer table
The water in face.
（5）It is bonded Si wafers：The nonbonding face of wafer is fitted on wafer pressure head, because wafer pressure head center has
There are vacuum sucking holes, when wafer pressure head surface is pressed close on the nonbonding surface of wafer, can be adsorbed automatically, as shown in Figure 2.
（6）Si wafers are cooled：Start elevating lever, the huyashi-chuuka (cold chinese-style noodles) and wafer pressure head for making semiconductor chilling plate closely paste
Close, in thermo-conducting manner, wafer is fallen below 5 ~ 15 DEG C of environment temperature, now surrounding air liquefies, wafer to be bonded
The humidity of atmosphere residing for surface increased, the progress being bonded in advance beneficial to wafer, as shown in Figure 3.
（7）Si wafers are bonded in advance：In the presence of wafer pressure head, make the to be bonded of the first wafer and the second wafer
Surface is in certain pressure（50 kgf）Effect is lower to be bonded in advance, and maintenance 1 hour, as shown in Figure 4.Due to（6）During, it is brilliant
The increase of atmosphere humidity residing for circular surfaces, crystal column surface can hang with a certain amount of hydrone, can so make original generation cavity
Place, Si-OH of two crystal column surfaces bridge joint occurs in the presence of hydrone, effectively reduce the generation machine in cavity
Rate.
（8）Si wafers are annealed：Start elevating lever, the hot face and wafer pressure head for making semiconductor chilling plate are closely pasted
Close, in thermo-conducting manner, wafer is raised to 120 DEG C, and maintain 24 hours, as shown in Figure 5.Then it is again started up lifting dress
Put, semiconductor chilling plate is departed from wafer pressure head, allow Si wafers natural cooling at room temperature, complete annealing.On the one hand,
Even disappear completely due to the migration of hydrone empty further reduce；On the other hand, can be due to thickness of diffusion layer
Increase and then add the intensity of bonded interface.
Claims (5)
- A kind of 1. method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, it is characterised in that methods described step It is as follows：First, to the first wafer and the second crystal column surface is cleaned respectively and activation process；2nd, the first wafer and the second wafer crossed cleaning and activation process are fitted in the first wafer pressure head and the second wafer respectively On pressure head；3rd, it is bonded by the huyashi-chuuka (cold chinese-style noodles) of semiconductor chilling plate with wafer pressure head and cooling processing is carried out to the first wafer and the second wafer, In the cooling processing procedure, temperature cools to -25 DEG C from 25 DEG C；4th, it is bonded the first wafer and the second wafer under ram pressures effect, in the bonding process, the temperature of wafer It is reduced to the scope of -50 DEG C of environment temperature；5th, the wafer for being bonded para-linkage with wafer pressure head by the hot face of semiconductor chilling plate is carried out at annealing at a certain temperature Reason.
- 2. the method according to claim 1 that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, its feature It is 0 ~ 300 kgf to be the ram pressures.
- 3. the method according to claim 1 that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, its feature It is the annealing temperature>100 DEG C, the time is 1 ~ 48 hour.
- 4. the method according to claim 1 that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, its feature It is the scope that the heating-up temperature after the bonding is+80 DEG C of environment temperature.
- 5. the method according to claim 1 that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate, its feature In the bonding process, the local humidity of the gas near crystal column surface is regulated and controled, local relative humidity control exists In the range of 40~100%.
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| CN201511011062.3A CN105632902B (en) | 2015-12-30 | 2015-12-30 | A kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate |
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| CN201511011062.3A CN105632902B (en) | 2015-12-30 | 2015-12-30 | A kind of method that the controllable wafer bonding of high/low temperature is carried out using semiconductor chilling plate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108054087B (en) * | 2017-12-07 | 2020-05-29 | 德淮半导体有限公司 | Annealing device and annealing method in wafer bonding |
| CN111223812B (en) * | 2018-11-27 | 2022-07-12 | 昆山微电子技术研究院 | Wafer bonding pressurizing device and wafer bonding equipment |
| CN110767541A (en) * | 2019-10-28 | 2020-02-07 | 苏师大半导体材料与设备研究院(邳州)有限公司 | Wafer bonding method |
| CN111243972B (en) * | 2020-02-24 | 2022-06-10 | 哈尔滨工业大学 | Multi-step synergistic surface activation low-temperature mixed bonding method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1086926A (en) * | 1992-11-10 | 1994-05-18 | 东南大学 | Silicon chip directive bonding method |
| CN1949454A (en) * | 2005-10-13 | 2007-04-18 | 中国科学院半导体研究所 | Wafer bonding method of changing different thermal expansion coefficient material using temp. |
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2015
- 2015-12-30 CN CN201511011062.3A patent/CN105632902B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1086926A (en) * | 1992-11-10 | 1994-05-18 | 东南大学 | Silicon chip directive bonding method |
| CN1949454A (en) * | 2005-10-13 | 2007-04-18 | 中国科学院半导体研究所 | Wafer bonding method of changing different thermal expansion coefficient material using temp. |
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