CN105632886A - Forming method of semiconductor structure - Google Patents
Forming method of semiconductor structure Download PDFInfo
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- CN105632886A CN105632886A CN201410598410.0A CN201410598410A CN105632886A CN 105632886 A CN105632886 A CN 105632886A CN 201410598410 A CN201410598410 A CN 201410598410A CN 105632886 A CN105632886 A CN 105632886A
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Abstract
A forming method of a semiconductor structure comprises providing a substrate, forming a medium layer on the substrate, forming a hard mask layer on the medium layer, forming a first photoresist layer with a first opening on the hard mask layer, performing curing processing on the first photoresist layer, performing silanization processing on a surface of the first photoresist layer, forming a silanization layer on the surface of the photoresist layer, forming a filling layer of the silanization layer, forming a second photoresist layer with first through holes on the filling layer, etching the filling layer along the first through holes, forming second through holes in the filling layer in first openings, etching the hard mask layer and the medium layer along the first and second through holes to forming third through holes, removing the second photoresist layer and the filling layer to expose a surface of the silanization layer, forming third openings in the hard mask layer, etching the medium layer along the third openings, and forming fourth openings in the medium layer. Through the method, photoetching technological process and etching technological process are simplified, and process stability is improved.
Description
Technical field
The present invention relates to field of semiconductor fabrication, particularly to the forming method of a kind of semiconductor structure.
Background technology
In semiconductor integrated circuit, signal transmission between semiconductor device needs highdensity metal interconnecting wires, but the big resistance that brings of these metal interconnecting wires and parasitic capacitance have become as the principal element that restriction RC (resistancecapacitance) postpones to continue to reduce.
In traditional semiconductor technology, metallic aluminium is typically used for the metal interconnecting wires between semiconductor device, development along with semiconductor technology, metallic aluminium interconnection line part is substituted by metallic copper interconnection line, this is because compared with aluminum, copper has less resistance value, adopts metallic copper interconnection line can reduce RC and postpones; On the other hand, the main component of the dielectric layer that low dielectric constant insulating material is used as between metal level, decrease the parasitic capacitance between metal level, in actual applications, low dielectric constant insulating material is generally called low k dielectric by us. The damascene structure that Damascus technics is formed is utilized to be widely used in the semiconductor structure of production line rear end (backendofline, BEOL). RC in order to reduce integrated circuit postpones, improve the RC performance of integrated circuit, along with the development of semiconductor technology, the dielectric layer material in damascene structure replaces with low k (a kind of dielectric constant) dielectric material from silicon oxide, replaces with ultra low k dielectric materials from low k dielectric again.
The manufacture method of existing damascene structure has multiple, and common method has: 1. all-pass hole precedence method (fullviafirst); 2. partial through holes precedence method (partialviafirst); 3. full groove-priority method (fulltrenchfirst); 4. part of trench precedence method (partialtrenchfirst); 5. self aligned approach (self-alignmentmethod). Below with regard to the manufacture method of one of which damascene structure---partial through holes precedence method makes general description, and described manufacture method includes:
Refer to Fig. 1, it is provided that substrate 101, in described substrate 101, be formed with underlying metal interconnection structure 103; Described substrate 101 is formed dielectric layer 102; Described dielectric layer 102 is formed hard mask layer 104; Described hard mask layer 104 is formed the first photoresist layer 105, described first photoresist layer 105 has the opening exposing hard mask layer 104 surface;
With reference to Fig. 2, with described first photoresist layer 105 for mask, etch described hard mask layer 104, hard mask layer 104 is formed the first opening 106 exposing dielectric layer 102 surface.
With reference to Fig. 3, remove described first photoresist layer (with reference to Fig. 2), form the second photoresist layer 107 covering described hard mask layer 104, and described second photoresist layer 107 fills full first opening 106 (with reference to Fig. 2), the second photoresist layer 107 in described first opening 106 has the first through hole 108 exposing dielectric layer 102 surface.
With reference to Fig. 4, with described second photoresist layer 107 for mask, etch described dielectric layer 102 along the first through hole 108, described dielectric layer 102 is formed the second through hole 109.
With reference to Fig. 5, remove described second photoresist layer 107 (with reference to Fig. 4).
With reference to Fig. 6, with described mask layer 104 for mask, etch described dielectric layer 102 along the first opening, dielectric layer 102 is formed the second opening 110, and etching the dielectric layer bottom the second through hole 109 simultaneously so that the second through hole 109 exposes underlying metal interconnection structure 103 surface of bottom.
With reference to Fig. 7, in described second opening 110 and the second through hole 109 (with reference to Fig. 6), fill full metal, form metal plug 111.
The formation process stability of existing damascene structure still has much room for improvement.
Summary of the invention
The problem that this invention address that is how to improve the stability of Damascus technics.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: substrate is provided, forms dielectric layer on the substrate; Described dielectric layer is formed hard mask layer; Described hard mask layer is formed the first photoresist layer, described first photoresist layer is formed with the first opening; The surface of described the first photoresist layer being formed with the first opening is carried out silanization treatment, the Other substrate materials on the first photoresist layer surface is converted into silanization layer; Formed and cover described silanization layer and fill the packed layer of full first opening; Forming the second photoresist layer on described packed layer, form the first through hole in described second photoresist layer, described first through hole is positioned at the first overthe openings; The second anti-reflecting layer along the first opening described in the first via etch and packed layer, form the second through hole in the packed layer in the first opening; Along the first anti-reflecting layer, hard mask layer and dielectric layer described in the first through hole and the second via etch, described hard mask layer and dielectric layer form third through-hole; Remove described second photoresist layer and packed layer, expose the surface of silanization layer; Etch described hard mask layer along the first opening, hard mask layer is formed the 3rd opening; With described hard mask layer for mask, etching described dielectric layer along the 3rd opening, form the 4th opening in the dielectric layer, described 4th opening and third through-hole run through mutually.
Optionally, described first photoresist layer material is negative photoresist or positive photoetching rubber.
Optionally, when described first photoresist layer material is positive photoetching rubber, in the front and back carrying out silanization treatment, also including step, the first photoresist layer being formed with the first opening is carried out cured, described cured is UV photo-irradiation treatment or heat treatment.
Optionally, described heat treated temperature is 100��250 degrees Celsius, and the time is 0.5��10 minute.
Optionally, described first photoresist layer material has resin, described resin includes hydroxyl functional group, carboxylic acid group's functional group, amido functional group or mercapto functional group, when carrying out silanization treatment, the protium in functional group in the Other substrate materials on the surface of the first photoresist layer is substituted by silylation, forms silanization layer.
Optionally, the reactant that described silanization treatment adopts is hexamethyldisiloxane, tetramethyl-disilazane, double; two dimethylamino methyl silica-based dimethylamine of silane dimethyl, the silica-based diethylamine of dimethyl, TMSDMA, TMSDEA or dimethylamino pentamethyl disilane.
Optionally, when carrying out silanization treatment, described reactant feeds reaction chamber in gaseous form, and the temperature of silanization treatment is 100��160 degrees Celsius, and the time is 0.5��10 minute.
Optionally, described silanization layer includes oxygen element, element silicon, carbon and protium.
Optionally, the material of described packed layer is Organic substance.
Optionally, in described Organic substance, carbon and protium content are more than 90%, and without element silicon in Organic substance.
Optionally, the formation process of described packed layer is spin coating proceeding.
Optionally, the thickness of described packed layer is 100nm-300nm, and the thickness of the first photoresist layer is 50nm-150nm.
Optionally, also include: before forming the first photoresist layer, described hard mask layer forms the first ARC; Before forming the second photoresist layer, described packed layer forms the second siliceous ARC.
Optionally, in the first photoresist layer, the first opening is formed by exposed and developed technique.
Optionally, described exposed and developed technique, curing process and silanization treatment technique are all carry out in photoetching equipment.
Optionally, described dielectric layer material is low-K dielectric constant material.
Optionally, described hard mask layer is single or multiple lift stacked structure.
Optionally, described substrate is formed with underlying metal interconnection structure.
Optionally, the bottom-exposed of third through-hole goes out the surface of underlying metal interconnection structure.
Optionally, also including: filler metal in the 4th opening and third through-hole, form Damascus metal interconnection structure, described Damascus metal interconnection structure electrically connects with underlying metal interconnection structure.
Compared with prior art, technical scheme has the advantage that
The forming method of semiconductor structure, forms the first photoresist layer on described hard mask layer, is formed with the first opening exposing hard mask layer surface in described first photoresist layer, the surface of described first photoresist layer is carried out silanization treatment, the Other substrate materials on the first photoresist layer surface is converted into silanization layer, the different in kind of the character of silanization layer and the first photoresist layer, the hardness of silanization layer and density are more than the hardness of the first photoresist layer and density, silanization layer protects the first photoresist layer to be damaged, thus after forming silanization layer, etching hard mask layer can not be made directly, hard mask layer carries out the step of the 3rd opening, and it is by silanization layer to form packed layer, packed layer is formed the second photoresist layer, second photoresist layer is formed the step of the second through hole, thus in the present invention, before forming the second photoresist layer, described hard mask layer is to maintain complete (being absent from opening in hard mask layer), when the second photoresist layer is exposed technique, the focal plane detecting step carried out before exposure technology and alignment mark detection step will not be subject to the impact of the imperfect state of hard mask layer, thus improve focal plane detecting step and the precision of alignment mark detection step, the precision making the first through hole formed in the second photoresist layer improves, additionally, first photoresist layer can synchronize to remove when etch media layer forms four openings, because removing described first photoresist layer without extra etch step, prevent the damage to dielectric layer in technical process.
Further, described photoetching glue victim layer material includes hydroxyl functional group, carboxylic acid group's functional group, amido functional group or mercapto functional group, the protium in functional group in part photoetching glue victim layer material is substituted by silylation, thus can conveniently change the character of photoetching glue victim layer surface portion material, the sidewall of photoetching glue victim layer and top section Other substrate materials are converted into silanization layer.
Further, before forming the second photoresist layer, formed and cover described silanization layer and fill the packed layer of full first opening so that there is when being subsequently formed the second photoresist layer smooth carrier surface so that the second photoresist layer of formation has higher thickness evenness.
Accompanying drawing explanation
Fig. 1��Fig. 7 is the cross-sectional view of prior art Damascus forming process;
Fig. 8��Figure 19 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
Detailed description of the invention
As background technology sayed, the formation process stability of existing damascene structure still has much room for improvement.
Research finds, the forming process of the damascene structure of prior art has two step photoetching processes, first time is for forming the first photoresist layer, then with the first photoresist layer for hard mask layer described in mask etching, hard mask layer is formed the first opening, second time, for forming the second photoresist layer, then with the second photoresist layer for dielectric layer described in mask etching, forms the second through hole in the dielectric layer. after hard mask layer is formed the first opening, need to remove the first photoresist layer, in the process removing the first photoresist layer, easily the dielectric layer of bottom is caused damage, when particularly dielectric layer is low-K dielectric constant material, this damage is particularly evident, further study show that, refer to Fig. 3, after hard mask layer 104 is formed the first opening, then the second photoresist layer 107 is being formed, when the second photoresist layer 107 is exposed technique (technique forming the first through hole 108), the precision of exposure technology can be produced impact by the hard mask layer with the first opening, concrete reason: before the second photoresist layer 107 is exposed, need to carry out focal plane detecting step and alignment mark detection step, focal plane detecting step is that Semiconductor substrate 101 is illuminated by light source, then pass through reception detection light and judge that whether the focal plane of Semiconductor substrate 101 is good, alignment mark detection step is to be illuminated by the alignment mark in light source Semiconductor substrate 101, then pass through the reflection light receiving alignment mark or alignment mark is identified by diffraction light, when carrying out focal plane detecting step and alignment mark detection step, owing to hard mask layer 104 is not complete (there is the first opening), the intensity irradiating the diverse location after light transmission hard mask layer 104 and after the first opening that light source is launched is different (reflection coefficient and the specific absorbance of hard mask material layer and the second Other substrate materials are different), the light that intensity is different there is also difference at the light intensity being radiated at Semiconductor substrate back reflection, or the light that intensity is different there is also difference in the intensity of the light irradiating alignment mark back reflection or diffraction, thus the precision of focal plane detecting step and alignment mark detection step is affected, after making focal plane detecting step and alignment mark detection step, the precision that second photoresist layer is exposed step is affected, the precision of the second through hole formed in the second photoresist layer is restricted.
The invention provides the forming method of a kind of semiconductor structure, after forming silanization layer, etching hard mask layer can not be made directly, hard mask layer carries out the step of the 3rd opening, and it is by silanization layer to form packed layer, packed layer is formed the second photoresist layer, second photoresist layer is formed the step of the second through hole, thus in the present invention, before forming the second photoresist layer, described hard mask layer is to maintain complete (being absent from the 3rd opening in hard mask layer), when the second photoresist layer is exposed technique, focal plane detecting step in exposure technology and alignment mark detection step will not be subject to the impact of the imperfect state of hard mask layer, thus improve focal plane detecting step and the precision of alignment mark detection step, the precision making the first through hole formed in the second photoresist layer improves, additionally, first photoresist layer can synchronize to remove when etch media layer forms four openings, because removing described first photoresist layer without extra etch step, prevent the damage to dielectric layer in technical process.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail. When describing the embodiment of the present invention in detail, for purposes of illustration only, schematic diagram can disobey general ratio makes partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this. Additionally, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 8��Figure 19 is the cross-sectional view of the forming process of embodiment of the present invention semiconductor structure.
With reference to Fig. 8, it is provided that substrate 200, described substrate 200 forms dielectric layer 203; Described dielectric layer 203 is formed hard mask layer 204.
Described substrate 200 includes Semiconductor substrate 201 and the underlying dielectric layer 202 being positioned in Semiconductor substrate 201, described Semiconductor substrate 201 is formed with semiconductor device, such as transistor etc., being formed with underlying metal interconnection structure 205 in described underlying dielectric layer 202, described underlying metal interconnection structure 205 can electrically connect with the semiconductor device in Semiconductor substrate 201.
The material silicon (Si) of described Semiconductor substrate 201, germanium (Ge) or SiGe (GeSi), carborundum (SiC); Can also being silicon-on-insulator (SOI), germanium on insulator (GOI), described semiconductor device can be formed in Semiconductor substrate 201 by existing MOS technique or CMOS technology.
Described metal interconnection structure 205 can be metal plug or metal interconnecting wires or includes metal plug and be connected metal interconnecting wires with metal plug.
Described underlying dielectric layer 202 can be single or multiple lift (>=2 layers) stacked structure, and described underlying dielectric layer 202 material is silicon oxide or low K (K��3.5) dielectric constant material.
In other embodiments of the invention, described substrate can be the substrate of other structures, and such as substrate can be layer of dielectric material etc.
Described dielectric layer 203 is subsequently formed Damascus metal interconnection structure. In order to reduce the parasitic capacitance between interconnection structure, in the present embodiment, described dielectric layer material is low K (K��3.5) dielectric constant material, and in a specific embodiment, dielectric layer 203 material is SiCOH, and the thickness of dielectric layer is 2000��3000 angstroms.
Mask when described hard mask layer 204 is as subsequent etching dielectric layer, described hard mask layer 204 can be single or multiple lift (>=2 layers) stacked structure.
In the present embodiment, described hard mask layer 204 is three level stack structure, including the first silicon oxide layer 21 being positioned on dielectric layer 203, the titanium nitride layer 22 being positioned on the first silicon oxide layer 21 surface, the second silicon oxide layer 23 of being positioned on titanium nitride layer surface. Described first silicon oxide layer 21 is as the cushion of dielectric layer 203 with titanium nitride layer 22, and can as follow-up stop-layer in hard mask layer during formation three opening, described second silicon oxide layer 23 is as the cushion between the first photoresist layer being subsequently formed and titanium nitride layer 22, hard mask layer 204 includes titanium nitride layer 22, during subsequent etching dielectric layer 203, improve the etching selection ratio of dielectric layer material and hard mask material layer
With reference to Fig. 9, described hard mask layer 204 forms the first photoresist layer 205.
Described first photoresist layer 205 adopts spin coating proceeding to be formed, and the thickness of the first photoresist layer 205 is 50nm-150nm.
Before forming the first photoresist layer 205, being additionally included on described hard mask layer 204 and form the first bottom antireflective coating, described first bottom antireflective coating for reducing the reflection of bottom light when the first photoresist layer is exposed.
Described first photoresist layer 205 material has resin, described resin includes hydroxyl functional group, carboxylic acid group's functional group, amido functional group or mercapto functional group, follow-up carry out silanization treatment time, in described functional group, protium is substituted by silylation, form silanization layer, to realize the change of the character to the first photoresist layer 205 surfacing.
Described first photoresist layer 205 material can be negative photoresist or positive photoetching rubber. In this enforcement, owing to the resolution of positive photoetching rubber is higher than the resolution of stock photoresist, the precision of the figure that the precision of the figure that positive photoetching rubber is formed is formed higher than negative photoresist, in the present embodiment, the material of described first photoresist layer 205 is positive photoetching rubber, the damascene structure higher to form precision.
With reference to Figure 10, described first photoresist layer 205 is formed with the first opening 210 exposing hard mask layer 204 surface.
Forming the first opening 210 by exposed and developed technique in described first photoresist layer 205, described first opening 210 is positioned at the top of underlying metal interconnection structure 205.
In the present embodiment, the material of described first photoresist layer 205 is positive photoetching rubber, after first photoresist layer 205 is formed the first opening 210, also include: the first photoresist layer 205 after forming opening 210 is carried out cured, to increase hardness and the consistency of the first photoresist layer 205, it is prevented that solvent diffuse in the packed layer being subsequently formed and the second photoresist layer and dissolve part the first photoresist layer material.
In other embodiments of the invention, if the material of described first photoresist layer 205 is negative photoresist layer, then without carrying out cured step.
Described cured is UV photo-irradiation treatment or heat treatment, when carrying out cured, and the first photoresist layer material cross-links reaction so that the first photoresist layer solidifies.
Described UV irradiates the UV light source irradiation can passed through in exposure device.
Described heat treatment can be undertaken by the thermal processing chamber in gluing or developing unit, and described heat treated temperature is 100��250 degrees Celsius, and the time is 0.5��10 minute.
With reference to Figure 11, the surface of the first photoresist layer 205 after described cured is carried out silanization treatment 31, the Other substrate materials on the first photoresist layer 205 surface after cured is converted into silanization layer 206.
When carrying out silanization treatment 31, the functional group in the Other substrate materials on the surface of the first photoresist layer 205 is substituted by silylation, forms silanization layer.
The reactant that described silanization treatment 31 adopts is hexamethyldisiloxane, tetramethyl-disilazane, double; two dimethylamino methyl silane, the silica-based dimethylamine of dimethyl, the silica-based diethylamine of dimethyl, TMSDMA, TMSDEA or dimethylamino pentamethyl disilane.
In one embodiment, when carrying out silanization treatment, described reactant feeds reaction chamber in gaseous form, the temperature of silanization treatment is 100��160 degrees Celsius, time is 0.5��10 minute, improve the efficiency of silanization treatment, and it is uniform to form silanization layer 206 thickness, and there is good surface topography.
In one embodiment, when carrying out silanization treatment, in the Other substrate materials on the surface of the first photoresist layer, the described functional group of 20��80% is substituted by silylation.
Described silanization layer 206 after silanization treatment includes oxygen element, element silicon, carbon and protium, the characteristic of silanization layer 206 and the characteristic of Other substrate materials is made to complete to change, if the functional group in photoresist expendable material is amido functional group or mercapto functional group, described silanization layer 206 also includes nitrogen element or element sulphur, the different in kind of the character of silanization layer and the first photoresist layer, the hardness of silanization layer and density are more than the hardness of the first photoresist layer and density, silanization layer can protect the first photoresist layer to be damaged, it is possible to prevent in the packed layer that is subsequently formed and the second photoresist layer solvent to the diffusion of the first photoresist layer 205, and when can improve subsequent etching hard mask layer 204 and dielectric layer 203, hard mask material layer and dielectric layer material are relative to the etching selection ratio of the first photoresist layer material.
In other embodiments of the invention, if the material of described first photoresist layer 205 is negative photoresist layer, then directly the first photoresist layer 205 being formed with the first opening 210 is carried out cured.
In the embodiment of the present invention, form the spin coating proceeding of the first photoresist layer 205, first photoresist layer 205 is formed the exposed and developed technique of the first opening 210, and the technique of the technique that the first photoresist layer 205 solidified and silanization treatment all carries out in a photoetching equipment, improve the efficiency of technique, save the time of technique.
In other embodiments of the invention, after carrying out silanization treatment, also include: described silanization layer is carried out oxidation processes, silanization layer is converted into hardness and the higher silicon oxide layer of compactness.
Described oxidation processes is that oxygen-containing plasma oxidation processes, and when carrying out oxidation processes, removes the carbon in silanization layer and protium so that remain oxygen element in silanization layer and element silicon is cross-linked to form silicon oxide layer.
With reference to Figure 12, formed and cover described silanization layer 206 and fill the packed layer 207 of full first opening 210 (with reference to Figure 11).
The purpose of formation packed layer 207 has smooth carrier surface when being so that and be subsequently formed the second photoresist layer so that the second photoresist layer of formation has higher thickness evenness.
The material of described packed layer 207 is Organic substance. In one embodiment, described Organic substance is the Organic substance of carbon elements and protium, and in Organic substance, carbon and protium content are more than 90%, and without element silicon in Organic substance.
The formation process of described packed layer 207 is spin coating proceeding, and the thickness of described packed layer is 100nm-300nm.
With reference to Figure 13, described packed layer 207 is formed the second photoresist layer 208, being formed with the first through hole 209 exposing packed layer 207 surface in described second photoresist layer 208, described first through hole 209 is positioned at the first opening 210 (with reference to Figure 11) top.
Form described second photoresist layer 208 and adopt spin coating proceeding, in described second photoresist layer 208, form the first through hole 209 by exposed and developed technique.
In the present embodiment, when the second photoresist layer 208 is exposed technique, described hard mask layer 204 is to maintain complete (being absent from opening in hard mask layer 204), the focal plane detecting step carried out before exposure technology and alignment mark detection step will not be subject to the impact of the imperfect state of hard mask layer (when focal plane detecting step and alignment mark detection step light are irradiated, by the light intensity of diverse location after hard mask layer 204 is equal or gap is only small), thus improve focal plane detecting step and the precision of alignment mark detection step, the precision making the first through hole formed in the second photoresist layer 208 improves.
Before forming the second photoresist layer 208, forming the second ARC (not shown) on described packed layer 207, the second ARC is as a part for the second photoresist layer 208, and the first throughhole portions is positioned at the second ARC. Second anti-reflective coating layer material is siliceous anti-reflective coating layer material, when subsequent etching when packed layer and dielectric layer, increase dielectric layer material and the packed layer material etching selection ratio relative to Other substrate materials so that the size of the first through hole will not change in etching process.
In other embodiments, before forming the second photoresist layer, described packed layer is formed silicon oxide layer, silicon oxide layer is formed the second ARC.
With reference to Figure 14, etch the packed layer 207 in described first opening 210 (with reference to Figure 11) along the first through hole 209, the packed layer 207 in the first opening 210 is formed the second through hole 211.
Etch described packed layer 207 and adopt anisotropic dry etch process, can be such as plasma etching industrial.
When etching packed layer 207, using hard mask layer 204 as stop-layer.
With reference to Figure 15, etch described hard mask layer 204 and dielectric layer 203 along the first through hole 209 and the second through hole 211, described hard mask layer 204 and dielectric layer 203 are formed third through-hole 212.
Etch described hard mask layer 204 and dielectric layer 203 adopts anisotropic dry etch process, can be such as plasma etching industrial.
With reference to Figure 16, remove described second photoresist layer 208 (with reference to Figure 15) and packed layer 207 (with reference to Figure 15), expose the surface of silanization layer 206.
Remove described second photoresist layer 208 (with reference to Figure 15) and packed layer 207 (with reference to Figure 15) can using plasma cineration technics.
With reference to Figure 17, etch described hard mask layer 204 along the first opening 210, hard mask layer 204 is formed the 3rd opening 213.
Etch described hard mask layer 204 and adopt anisotropic dry etch process, can be such as plasma etching industrial.
When forming three openings 213, it is possible to the first silicon oxide layer 21 is stop-layer or with the surface of dielectric layer 203 for stop-layer.
With reference to Figure 18, with described hard mask layer 204 for mask, etching described dielectric layer 203 along the 3rd opening 213, form the 4th opening 214 in dielectric layer 203, described 4th opening 214 runs through mutually with third through-hole 212.
In the process of the dielectric layer 203 bottom etching the 3rd opening 213, etching the dielectric layer bottom third through-hole 212, the degree of depth of third through-hole 212 increases, and the bottom-exposed of third through-hole 212 goes out the surface of underlying metal interconnection structure 205 simultaneously.
In the process of etch media layer 203, removal silanization layer 206 (with reference to Figure 17) and the first photoresist layer 205 (with reference to Figure 17) can be etched simultaneously.
With reference to Figure 19, described 4th opening 214 (with reference to Figure 18) and third through-hole 212 (with reference to Figure 18) fill full metal, forming Damascus metal interconnection structure 215, described Damascus metal interconnection structure 215 electrically connects with underlying metal interconnection structure 205.
Damascus metal interconnection structure 215 forming process is: form the metal level covering described hard mask layer 204 (with reference to Figure 18) surface, and described metal level fills full 3rd opening 213 (with reference to Figure 18), the 4th opening 214 (with reference to Figure 18) and third through-hole 212 (with reference to Figure 18); Metal level described in chemical-mechanical planarization, with the first silicon oxide layer 21 for stop-layer, forms Damascus metal interconnection structure 215 filling full described 4th opening 214 (with reference to Figure 18) and third through-hole 212 (with reference to Figure 18).
The material of described metal level can be W, Al, Cu, Ti, Ag, Au, Pt, Ni one of which or several.
Before forming metal level, can also forming diffusion impervious layer at described 3rd opening 213 (with reference to Figure 18), the 4th opening 214 (with reference to Figure 18) and third through-hole 212 (with reference to Figure 18) sidewall and lower surface, described diffusion impervious layer is for stoping the metallic atom in Damascus metal interconnection structure 215 to spread in dielectric layer 203.
The material of described diffusion impervious layer is one or more in Ti, Ta, TiN, TaN, TiAl, TaC, TaSiN, TiAlN. In a specific embodiment, described diffusion impervious layer is Ti layer and the double stacked structure of TiN double stacked structure or Ta layer and TaN.
Although present disclosure is as above, but the present invention is not limited to this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a semiconductor structure, it is characterised in that including:
Substrate is provided, forms dielectric layer on the substrate;
Described dielectric layer is formed hard mask layer;
Described hard mask layer is formed the first photoresist layer, described first photoresist layer is formed with the first opening;
The surface of described the first photoresist layer being formed with the first opening is carried out silanization treatment, the Other substrate materials on the first photoresist layer surface is converted into silanization layer;
Formed and cover described silanization layer and fill the packed layer of full first opening;
Forming the second photoresist layer on described packed layer, form the first through hole in described second photoresist layer, described first through hole is positioned at the first overthe openings;
Packed layer in the first opening described in the first via etch, forms the second through hole in the packed layer in the first opening;
Along hard mask layer and dielectric layer described in the first through hole and the second via etch, described hard mask layer and dielectric layer form third through-hole;
Remove described second photoresist layer and packed layer, expose the surface of silanization layer;
Etch described hard mask layer along the first opening, hard mask layer is formed the 3rd opening;
With described hard mask layer for mask, etching described dielectric layer along the 3rd opening, form the 4th opening in the dielectric layer, described 4th opening and third through-hole run through mutually.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described first photoresist layer material is negative photoresist or positive photoetching rubber.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterized in that, when described first photoresist layer material is positive photoetching rubber, in the front and back carrying out silanization treatment, also include step, the first photoresist layer being formed with the first opening is carried out cured, and described cured is UV photo-irradiation treatment or heat treatment.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that described heat treated temperature is 100��250 degrees Celsius, and the time is 0.5��10 minute.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterized in that, described first photoresist layer material has resin, described resin includes hydroxyl functional group, carboxylic acid group's functional group, amido functional group or mercapto functional group, when carrying out silanization treatment, the protium in functional group in the Other substrate materials on the surface of the first photoresist layer is substituted by silylation, forms silanization layer.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterized in that, the reactant that described silanization treatment adopts is hexamethyldisiloxane, tetramethyl-disilazane, double; two dimethylamino methyl silica-based dimethylamine of silane dimethyl, the silica-based diethylamine of dimethyl, TMSDMA, TMSDEA or dimethylamino pentamethyl disilane.
7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that when carrying out silanization treatment, described reactant feeds reaction chamber in gaseous form, and the temperature of silanization treatment is 100��160 degrees Celsius, and the time is 0.5��10 minute.
8. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that described silanization layer includes oxygen element, element silicon, carbon and protium.
9. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of described packed layer is Organic substance.
10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that in described Organic substance, carbon and protium content are more than 90%, and without element silicon in Organic substance.
11. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the formation process of described packed layer is spin coating proceeding.
12. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the thickness of described packed layer is 100nm-300nm, and the thickness of the first photoresist layer is 50nm-150nm.
13. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that also include: before forming the first photoresist layer, form the first ARC on described hard mask layer; Before forming the second photoresist layer, described packed layer forms the second siliceous ARC.
14. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that form the first opening in the first photoresist layer by exposed and developed technique.
15. the forming method of semiconductor structure as claimed in claim 14, it is characterised in that described exposed and developed technique, curing process and silanization treatment technique are all carry out in photoetching equipment.
16. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described dielectric layer material is low-K dielectric constant material.
17. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described hard mask layer is single or multiple lift stacked structure.
18. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that be formed with underlying metal interconnection structure in described substrate.
19. the forming method of semiconductor structure as claimed in claim 18, it is characterised in that the bottom-exposed of third through-hole goes out the surface of underlying metal interconnection structure.
20. the forming method of semiconductor structure as claimed in claim 19, it is characterized in that, also including: filler metal in the 4th opening and third through-hole, form Damascus metal interconnection structure, described Damascus metal interconnection structure electrically connects with underlying metal interconnection structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107946184A (en) * | 2017-11-24 | 2018-04-20 | 长江存储科技有限责任公司 | A kind of lithography alignment method for photolithographic patterning process |
| CN114686057A (en) * | 2020-12-28 | 2022-07-01 | 中国科学院微电子研究所 | Anti-reflection coating composition for patterning and patterning method |
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| JP2005033168A (en) * | 2003-07-10 | 2005-02-03 | Samsung Electronics Co Ltd | Method of forming metal wiring in semiconductor element |
| CN1614764A (en) * | 2003-11-06 | 2005-05-11 | 株式会社瑞萨科技 | Manufacture of semiconductor device |
| US20060292854A1 (en) * | 2005-06-22 | 2006-12-28 | Chih-Jung Wang | Manufacturing method of dual damascene structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005033168A (en) * | 2003-07-10 | 2005-02-03 | Samsung Electronics Co Ltd | Method of forming metal wiring in semiconductor element |
| CN1614764A (en) * | 2003-11-06 | 2005-05-11 | 株式会社瑞萨科技 | Manufacture of semiconductor device |
| US20060292854A1 (en) * | 2005-06-22 | 2006-12-28 | Chih-Jung Wang | Manufacturing method of dual damascene structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107946184A (en) * | 2017-11-24 | 2018-04-20 | 长江存储科技有限责任公司 | A kind of lithography alignment method for photolithographic patterning process |
| CN114686057A (en) * | 2020-12-28 | 2022-07-01 | 中国科学院微电子研究所 | Anti-reflection coating composition for patterning and patterning method |
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| CN105632886B (en) | 2018-08-10 |
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