CN105610438B - One kind removing tri-frequency divider circuit - Google Patents
One kind removing tri-frequency divider circuit Download PDFInfo
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- CN105610438B CN105610438B CN201510973659.XA CN201510973659A CN105610438B CN 105610438 B CN105610438 B CN 105610438B CN 201510973659 A CN201510973659 A CN 201510973659A CN 105610438 B CN105610438 B CN 105610438B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
One kind removing tri-frequency divider circuit, including the first delay unit, the second delay unit and third delay unit, P1, P2 and P3, N1, N2 and N3, the data output end of first delay unit is connected with the data input pin of the second delay unit, the data output end of second delay unit is connected with the data input pin of third delay unit, and the data output end of third delay unit is connected with the data input pin of the first delay unit；Wherein, the drain electrode of the Q and P1 of the first delay unit are connected, and the source electrode ground connection of P1, the source electrode of the QB and N1 of the first delay unit is connected, and the drain electrode of N1 accesses power supply；The source electrode of the Q and N2 of second delay unit are connected, and the drain electrode of N2 accesses power supply, and the source electrode of the QB and P2 of the second delay unit are connected, the grounded drain of P2；Third delay unit is identical as the first delay unit connection type.When " removing 3 " frequency divider enters " endless loop " state, can be jumped out with lock-on circuit " endless loop ".
Description
Technical field
The present invention relates to frequency dividing circuit technical fields, more particularly to one kind to remove tri-frequency divider circuit.
Background technique
There is frequency mixer in general Receiver And Transmitter, the frequency mixer in receiver produces high-frequency signal and chip interior
Raw orthogonal local oscillation signal mixing generates low frequency signal and gives late-class circuit processing；Frequency mixer in transmitter is by low frequency signal
The orthogonal local oscillation signal mixing generated with chip interior generates the power amplifier circuit processing that high-frequency signal gives rear class.It can
See, regardless of receiver or transmitter, requires chip interior and generate orthogonal local oscillation signal.
And orthogonal local oscillation signal is generally generated by oscillator by frequency divider.Frequency divider is generally cascaded by multistage frequency divider and is given birth to
At.If generating orthogonal local oscillation signal, it is required that afterbody frequency division coefficient is " except 2 ", and afterbody is required to divide
The duty ratio of device input signal is 50%.In order to reach this requirement, the frequency division coefficient of penultimate stage frequency divider is often selected
Even number, such as " removing 2 " (as shown in Figure 1), " removing 4 ".
In order to reduce the requirement to oscillator frequency covering, to reduce design cost, first order frequency divider is often used
Multi-mode structure, such as two mode field (as shown in Figure 2), three mode structures (as shown in Figure 3).If penultimate stage frequency divider uses
Three mode structures are then required when " removing 3 " frequency divider operation, and output signal duty ratio is 50%.
Table 1
| D | CK | QB |
| 0 | 0 | 1 |
| 1 | 1 | 0 |
| 0 | 1 | Hold |
| 1 | 0 | Hold |
" removing 3 " frequency divider is realized using circuit structure as shown in Figure 4 in the prior art.Fig. 4 is differential mode structural circuit, is
For the sake of simple, analyze by taking the single-ended signal as an example.Referring to table 1, Fig. 5 and Fig. 6 it is found that circuit uses 3bit in total, there are 8 shapes
State.And the design has only used 6 states therein, there are also 2 states " 000 " and " 111 " not to use.By analyzing and emulating
Verifying discovery will recycle between the two states always once circuit state enters any one of the two states
(i.e. " endless loop "), circuit work will be abnormal.
Summary of the invention
Being designed to provide for the application is a kind of improved except tri-frequency divider circuit.
First aspect of the embodiment of the present invention provides a kind of except tri-frequency divider circuit, comprising:
The data output end of first delay unit is connected with the data input pin of the second delay unit, and second delay is single
The data output end of member is connected with the data input pin of third delay unit, the data output end of the third delay unit and institute
The data input pin for stating the first delay unit is connected；
The data output end includes the first data output end Q and the second data output end QB, and the level of Q and QB output
Inequality；
The Q of first delay unit is connected with the drain electrode of the first PMOS, the source electrode of the first PMOS ground connection, and described the
The QB of one delay unit is connected with the source electrode of the first NMOS, and the drain electrode of the first NMOS accesses power supply；
The Q of second delay unit is connected with the source electrode of the 2nd NMOS, and the drain electrode of the 2nd NMOS accesses power supply, institute
The QB for stating the second delay unit is connected with the source electrode of the 2nd PMOS, the grounded drain of the 2nd PMOS；
The Q of the third delay unit is connected with the drain electrode of the 3rd PMOS, the source electrode of the 3rd PMOS ground connection, and described the
The QB of three delay units is connected with the source electrode of the 3rd NMOS, and the drain electrode of the 3rd NMOS accesses power supply；
When circuit enters endless loop state, first, second, and third PMOS and described first, second, and third
NMOS conducting.
In the technical scheme, when circuit enters endless loop state, i.e. the Q of the first delay unit, the second delay unit
Q and the Q of third delay unit when exporting " 0 ", " 0 ", " 0 " or " 1 ", " 1 ", " 1 " respectively, the first, the 3rd PMOS and second
NMOS conducting, and the first PMOS conducting is forced to draw the Q of the first delay unit as low level, pressure is connected by second in the 2nd NMOS
It is high level that the Q of delay unit, which is drawn, and the 3rd PMOS conducting is forced to draw the Q of third delay unit as low level, to force electricity
Road enters " 010 " state, realizes and jumps out automatically " endless loop ", and enters normal operating conditions.
In the first possible implementation of the first aspect, the circuit further include the first NAND gate, second with it is non-
Door, third NAND gate and NOT gate, in which:
The input terminal of first NAND gate is connected with the Q output of three delay units respectively；
The input terminal of second NAND gate is connected with the QB output end of three delay units respectively；
The input terminal of the third NAND gate output end phase with first NAND gate and second NAND gate respectively
Even；
The output end of the third NAND gate respectively with the grid and the NOT gate of first, second, third PMOS
Input terminal be connected；
The output end of the NOT gate respectively with described first, second and the 3rd the grid of NMOS be connected.
In the technical scheme, when circuit enters endless loop state, i.e. the Q of the first delay unit, the second delay unit
Q and third delay unit Q export respectively " 0 ", " 0 ", " 0 " or respectively export " 1 ", " 1 ", " 1 " when, to export respectively
For " 1 ", " 1 ", " 1 ", the input terminal of the first NAND gate inputs " 1 ", " 1 ", " 1 " respectively, then output is " 0 ", correspondingly, described
The input terminal of second NAND gate then inputs " 0 ", " 0 ", " 0 ", and output end then exports " 1 ", and the input of third NAND gate is respectively " 0 "
" 1 ", then output is " 1 ", and the output of NOT gate is " 0 ", when the output of third NAND gate is 1, the first, second, third PMOS
Conducting, when NOT gate output is " 0 ", the first, second, third NMOS conducting.
With reference to first aspect or the first possible realization of first aspect, in the second possible implementation, institute
Stating the first, second, and third delay unit is d type flip flop.
Using the embodiment of the present invention, have the advantages that
In the technical scheme, when " removing 3 " frequency divider enters " endless loop " state, it can be jumped out and " extremely be followed with lock-on circuit
Ring ", into normal operating conditions.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 shows the schematic diagram of a kind of oscillator and frequency divider；
Fig. 2 shows a kind of schematic diagrames of dual-mode frequency divider；
Fig. 3 shows a kind of schematic diagram of three mould frequency dividers；
Fig. 4 shows the schematic diagram of " except 3 " divider circuit in the prior art；
Fig. 5 is the timing diagram of divider circuit shown in Fig. 4；
Fig. 6 is the state machine diagram of divider circuit shown in Fig. 4；
Fig. 7 is the schematic diagram of " removing 3 " divider circuit provided in an embodiment of the present invention；
Fig. 8 is the state machine diagram of divider circuit shown in Fig. 7；
Fig. 9 is the one mode schematic diagram that three carrier waves work at the same time；
Figure 10 is another pattern diagram that three carrier waves work at the same time.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
Referring to Fig. 7, Fig. 7 is the schematic diagram of " removing 3 " divider circuit provided in an embodiment of the present invention；As shown in fig. 7, institute
Stating circuit includes: DelayCell1 (i.e. the first delay unit), DelayCell2 (i.e. the second delay unit) and DelayCell3
(i.e. third delay unit), P1 (i.e. the first PMOS), P2 (i.e. and PMOS) and P3 (i.e. the 3rd PMOS), N1 (i.e. first
NMOS), N2 (i.e. the and NMOS) and N3 (i.e. the 3rd NMOS), CK and CKB are clock signal, in which:
The data output end of DelayCell1 is connected with the data input pin of DelayCell2, and the data of DelayCell2 are defeated
Outlet is connected with the data input pin of DelayCell3, and the data output end of DelayCell3 and the data of DelayCell1 input
End is connected, and each data output end includes the first data output end Q and the second data output end QB, and the electricity of Q and QB output
Flat inequality；
The drain electrode of the Q and P1 of DelayCell1 are connected, the source electrode ground connection of P1, the source electrode phase of the QB and N1 of DelayCell1
Even, the drain electrode of N1 accesses power supply；
The source electrode of the Q and N2 of DelayCell2 are connected, and the drain electrode of N2 accesses power supply, the source electrode of the QB and P2 of DelayCell2
It is connected, the grounded drain of P2；
The drain electrode of the Q and P3 of DelayCell3 are connected, and the source electrode ground connection of P3, the source electrode of the QB and N3 of P3 is connected, the leakage of N3
Power supply is accessed in pole；
Since the connection type of DelayCell1 and DelayCell3 is identical, and therefore, Fig. 7 is omitted in DelayCell3
The connection schematic diagram of portion's circuit diagram and DelayCell3 and P3 and N3.The circuit is difference channel, the shape of Q1 Q2 Q3
The state inequality of state and Q1B Q2B Q3B, if the state of Q1 Q2 Q3 is " 010 ", then the state of Q1B Q2B Q3B is " 101 "；
For another example, the state of Q1 Q2 Q3 is " 111 ", then the state of Q1B Q2B Q3B is " 000 ".Therefore, it in order to avoid repeating, analyzes
When analyzed for single-ended.
The state machine of improved " remove 3 " divider circuit as shown in figure 8, in the technical scheme, when circuit enter it is dead
When recurrent state, i.e., when the state of Q1 Q2 Q3 is " 000 " or " 111 ", P1, P2, P3, N1, N2 and N3 conducting, and P1 is led
Logical to force to draw the Q of DelayCell31 as low level, N2 conducting is forced to draw the Q of DelayCell2 as high level, and P3 is connected by force
The Q of DelayCell3 is drawn and realizes so that lock-on circuit enters " 010 " state for low level and jump out " endless loop " automatically by system,
And enter normal operating conditions, wherein reset=1 indicates that P1, P2 and P3 are high level, and set=0 indicates that N1, N2 and N3 are low
The conducting of level, i.e. P1, P2, P3, N1, N2 and N3.
As shown in fig. 7, " remove 3 " divider circuit further include Y1 (i.e. the first NAND gate), Y2 (the second NAND gate), Y3 (i.e.
Third NAND gate) and Y4 (i.e. NOT gate), in which:
The input terminal of Y1 is connected with the Q output of DelayCell1, DelayCell2 and DelayCell3 respectively, i.e. Y1's
Input is Q1Q2Q3；
The input terminal of Y2 is connected with the QB output end of DelayCell1, DelayCell2 and DelayCell3 respectively, i.e. Y2
Input be Q1BQ2BQ3B；
The input terminal of Y3 is connected with the output end of Y1 and Y2 respectively；
The output end of Y3 is connected with the input terminal of the grid of P1, P2, P3 and Y4 respectively；
The output end of Y4 is connected with the grid of N1, N2 and N3 respectively.
In the technical scheme, when circuit enters endless loop state, i.e., the state of Q1 Q2 Q3 be " 000 " or
When " 111 ", by taking " 111 " as an example, the input terminal of Y1 is " 111 ", then output is " 0 ", and correspondingly, the input of Y2 is " 000 ", output
End then exports " 1 ", and the input of Y3 is respectively " 0 " and " 1 ", then output is " 1 ", and the output of Y4 is " 0 ", when Y3 output is 1,
P1, P2, P3 conducting, when Y4 output is " 0 ", N1, N2 and N3 conducting.
Optionally, DelayCell1, DelayCell2 and DelayCell3 can be d type flip flop.
It should be pointed out that the embodiment of the present invention shown in Fig. 7 removes the circuit that tri-frequency divider circuit is differential mode structure, at it
In his alternative embodiment, the tri-frequency divider circuit that removes of the embodiment of the present invention can also be that common mode configuration is circuit, i.e., each delay
Unit all only one input end of clock, a data input pin and a data output end, working principle and differential mode structure
Similar, details are not described herein.
The present invention is illustrated in handset transceiver work in three carrier waves while received mode below in conjunction with Fig. 9 Figure 10
In application.
As shown in figure 9, low-noise amplifier (LNA) by antenna by received carrier signal input mixer (Mixer),
Oscillator (VCO) outputs it signal after frequency divider also into frequency mixer simultaneously.When three carrier waves (Band1, Band3,
When Band5) working at the same time, it is assumed that there is no " except 6 " frequency divider, then the wherein frequency range (3610 of second oscillator (VCO2)
~3760MHz) understand with the frequency range (3476~3576MHz) of third oscillator (VCO3) relatively, due to inductance
Interaction, two close inductance of frequency are easy to cause its frequency to influence each other.And if one of frequency divider can use
" removing 6 ", as shown in Figure 10, then the frequency separation of three oscillators can pull open biggish distance, it is possible to prevente effectively from inductance
Between influence each other.
Frequency coverage needed for " removing 3 " frequency divider provided in an embodiment of the present invention can effectively reduce oscillator,
Relative to the circuit for not having the frequency divider " except 3 ", the coverage area of oscillator 1.584GHz is reduced.
The above disclosure is only the preferred embodiments of the present invention, cannot limit the right model of the present invention with this certainly
It encloses, therefore equivalent changes made in accordance with the claims of the present invention, is still within the scope of the present invention.
Claims (1)
1. one kind removes tri-frequency divider circuit characterized by comprising
The data output end of first delay unit is connected with the data input pin of the second delay unit, second delay unit
Data output end is connected with the data input pin of third delay unit, the data output end of the third delay unit and described the
The data input pin of one delay unit is connected；
The data output end includes the first data output end Q and the second data output end QB, and the level of Q and QB output is mutual
It is different；
The Q of first delay unit is connected with the drain electrode of the first NMOS, and the source electrode ground connection of the first NMOS, described first prolongs
The QB of Shi Danyuan is connected with the drain electrode of the first PMOS, and the source electrode of the first PMOS accesses power supply；
The Q of second delay unit is connected with the drain electrode of the 2nd PMOS, and the source electrode of the 2nd PMOS accesses power supply, and described the
The QB of two delay units is connected with the drain electrode of the 2nd NMOS, the source electrode ground connection of the 2nd NMOS；
The Q of the third delay unit is connected with the drain electrode of the 3rd NMOS, and the source electrode ground connection of the 3rd NMOS, the third is prolonged
The QB of Shi Danyuan is connected with the drain electrode of the 3rd PMOS, and the source electrode of the 3rd PMOS accesses power supply；
When circuit enters endless loop state, first, second, and third PMOS and first, second, and third NMOS
Conducting；
Wherein, further includes:
First NAND gate, the second NAND gate, third NAND gate and NOT gate, in which:
The input terminal of first NAND gate is connected with the Q output of three delay units respectively；
The input terminal of second NAND gate is connected with the QB output end of three delay units respectively；
The input terminal of the third NAND gate is connected with the output end of first NAND gate and second NAND gate respectively；
The output end of the third NAND gate is defeated with the grid of first, second, third PMOS and the NOT gate respectively
Enter end to be connected；
The output end of the NOT gate respectively with described first, second and the 3rd the grid of NMOS be connected.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910141350.2A CN109936364B (en) | 2015-12-22 | 2015-12-22 | Divide-by-three circuit |
| CN201510973659.XA CN105610438B (en) | 2015-12-22 | 2015-12-22 | One kind removing tri-frequency divider circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510973659.XA CN105610438B (en) | 2015-12-22 | 2015-12-22 | One kind removing tri-frequency divider circuit |
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| CN201910141350.2A Division CN109936364B (en) | 2015-12-22 | 2015-12-22 | Divide-by-three circuit |
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| CN105610438B true CN105610438B (en) | 2019-03-08 |
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| CN201510973659.XA Active CN105610438B (en) | 2015-12-22 | 2015-12-22 | One kind removing tri-frequency divider circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109936364A (en) * | 2015-12-22 | 2019-06-25 | 华为技术有限公司 | One kind removing tri-frequency divider circuit |
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| US5359635A (en) * | 1993-04-19 | 1994-10-25 | Codex, Corp. | Programmable frequency divider in a phase lock loop |
| CN101098142A (en) * | 2007-06-14 | 2008-01-02 | 复旦大学 | Frequency synthesizer of multi-sideband OFDM ultra-broadband system radio frequency transceiver |
| CN102361455A (en) * | 2011-08-18 | 2012-02-22 | 天津朗波微电子有限公司 | Dividing-two frequency divider used for local oscillator generation circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1159850C (en) * | 1999-10-08 | 2004-07-28 | 威盛电子股份有限公司 | Low-voltage low-frequency offset control oscillator |
| KR100513809B1 (en) * | 2003-03-28 | 2005-09-13 | 주식회사 하이닉스반도체 | Circuit for generating phase comparison signal |
| WO2006117859A1 (en) * | 2005-04-28 | 2006-11-09 | Thine Electronics, Inc. | Phase locked loop circuit |
| JP2010035098A (en) * | 2008-07-31 | 2010-02-12 | Sony Corp | Phase synchronization circuit, recording and reproducing device, and electronic device |
| CN203104408U (en) * | 2012-12-26 | 2013-07-31 | 陕西航天导航设备有限公司 | Practical and highly-reliable power supply of motor |
| CN109936364B (en) * | 2015-12-22 | 2022-07-22 | 华为技术有限公司 | Divide-by-three circuit |
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2015
- 2015-12-22 CN CN201910141350.2A patent/CN109936364B/en active Active
- 2015-12-22 CN CN201510973659.XA patent/CN105610438B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359635A (en) * | 1993-04-19 | 1994-10-25 | Codex, Corp. | Programmable frequency divider in a phase lock loop |
| CN101098142A (en) * | 2007-06-14 | 2008-01-02 | 复旦大学 | Frequency synthesizer of multi-sideband OFDM ultra-broadband system radio frequency transceiver |
| CN102361455A (en) * | 2011-08-18 | 2012-02-22 | 天津朗波微电子有限公司 | Dividing-two frequency divider used for local oscillator generation circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109936364A (en) * | 2015-12-22 | 2019-06-25 | 华为技术有限公司 | One kind removing tri-frequency divider circuit |
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| CN109936364B (en) | 2022-07-22 |
| CN105610438A (en) | 2016-05-25 |
| CN109936364A (en) | 2019-06-25 |
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