CN105609470B - Semiconductor devices and its manufacturing method with the distribution of uniform threshold voltage - Google Patents
Semiconductor devices and its manufacturing method with the distribution of uniform threshold voltage Download PDFInfo
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- CN105609470B CN105609470B CN201510516131.XA CN201510516131A CN105609470B CN 105609470 B CN105609470 B CN 105609470B CN 201510516131 A CN201510516131 A CN 201510516131A CN 105609470 B CN105609470 B CN 105609470B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000009826 distribution Methods 0.000 title abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000002019 doping agent Substances 0.000 claims abstract description 46
- 230000000295 complement effect Effects 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims description 101
- 239000007924 injection Substances 0.000 claims description 101
- 238000002513 implantation Methods 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 25
- 229910052787 antimony Inorganic materials 0.000 claims description 10
- 229910052785 arsenic Inorganic materials 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 10
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 9
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 9
- 229910052771 Terbium Inorganic materials 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 18
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- 239000007943 implant Substances 0.000 description 3
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- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Provide a kind of semiconductor devices and its manufacturing method with the distribution of uniform threshold voltage.According to embodiment, semiconductor devices may include: the fin formed on a substrate extended in a first direction；The grid that edge formed on a substrate extends with the second direction that first direction intersects stack, it includes the gate dielectric layer and Metal gate layer stacked gradually that wherein grid, which stack, wherein, relative to side wall of the Metal gate layer in the opposite sides of fin, roof of the Metal gate layer on the top surface of fin includes the dopant of the higher first kind and the dopant of the higher Second Type complementary with the first kind, so that substantially uniform first kind doping is presented in Metal gate layer on the whole.
Description
Technical field
This disclosure relates to semiconductor field, more particularly, to a kind of semiconductor device with the distribution of uniform threshold voltage
Part and its manufacturing method.
Background technique
As the size of planar-type semiconductor device is smaller and smaller, short-channel effect is further obvious.It is proposed to this end that three-dimensional
Type semiconductor devices such as FinFET (fin formula field effect transistor).In general, FinFET includes being vertically formed on substrate
Fin and the grid intersected with fin stack.Grid stacking may include high K/ metal gate configuration.By injection, the work content of metal gate is adjusted
Number, the threshold voltage of adjustable FinFET.But with this method, it is difficult to keep the ion of injection uniform in metal gate
Distribution, to be difficult to realize being uniformly distributed for threshold voltage.
Summary of the invention
The purpose of the disclosure be at least partly to provide a kind of semiconductor devices with the distribution of uniform threshold voltage and
Its manufacturing method.
According to one aspect of the disclosure, a kind of method of manufacturing semiconductor devices is provided, comprising: be formed on the substrate
The fin extended in a first direction；It is formed on the substrate and is stacked along the grid that the second direction intersected with first direction extends, wherein grid
Stacking includes the gate dielectric layer and Metal gate layer stacked gradually；The first inclination injection is carried out using the dopant of the first kind,
In the first inclination injection side wall of the direction towards Metal gate layer on the first side of fin；It is carried out using the dopant of the first kind
Second inclination injection, wherein the direction of the second inclination injection is towards Metal gate layer in second side opposite with the first side of fin
Side wall；Third injection is carried out using the dopant of the Second Type complementary with the first kind, the direction that wherein third is injected is substantially
Perpendicular to the surface of substrate.
According to another aspect of the present disclosure, a kind of semiconductor devices is provided, comprising: formed on a substrate along first party
To the fin of extension；The grid that edge formed on a substrate extends with the second direction that first direction intersects stack, and wherein grid stack packet
Include the gate dielectric layer and Metal gate layer stacked gradually, wherein relative to side wall of the Metal gate layer in the opposite sides of fin, metal
Roof of the grid layer on the top surface of fin includes the dopant and higher complementary with the first kind the of the higher first kind
The dopant of two types, so that substantially uniform first kind doping is presented in Metal gate layer on the whole.
In accordance with an embodiment of the present disclosure, the inclination injection of the first kind twice can be carried out.In this way, Metal gate layer is in fin two
Two side walls on side can receive substantially uniform doping.On the other hand, roof of the Metal gate layer on the top surface of fin receives
More first kind doping.It can carry out the vertical injection of the Second Type complementary with the first kind.Then, Metal gate layer
Roof receive more compensation, so that Metal gate layer can show the doping of the substantially uniform first kind.In this way, metal
The available substantially uniform adjusting of the work function of grid layer, therefore semiconductor devices can show the threshold value being substantially evenly distributed
Voltage.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1-Figure 20 C is according to the schematic diagram of the manufacturing semiconductor devices process of the embodiment of the present disclosure, and wherein Fig. 9 A is edge
The sectional view of AA ' line in Fig. 9；Figure 11 A is the sectional view of the AA ' line along Figure 11, and Figure 11 B is the sectional view of the BB ' line along Figure 11,
And Figure 11 C is the sectional view of the CC ' line along Figure 11；Figure 12 A is the sectional view of the AA ' line along Figure 12, and Figure 12 B is along Figure 12
The sectional view of BB ' line, and Figure 12 C is the sectional view of the CC ' line along Figure 12；Figure 13 A, 13B, 13C be respectively with Figure 12 A, 12B,
The corresponding sectional view of 12C；Figure 20 A is the sectional view of the AA ' line along Figure 20, and Figure 20 B is the sectional view of the BB ' line along Figure 20, and
Figure 20 C is the sectional view of the CC ' line along Figure 20；.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
In accordance with an embodiment of the present disclosure, be formed on the substrate fin and the grid intersected with fin stack (including gate dielectric layer and
Metal gate layer) after, Metal gate layer can be injected, to adjust its work function.For uniformity, this injection can divide more
Secondary progress.For example, the dopant that can use the first kind carries out the first inclination injection, wherein the direction court of the first inclination injection
To side wall of the Metal gate layer on the side of fin；The dopant that can use the first kind carries out the second inclination injection, wherein the
Side wall of the direction of two inclination injections towards Metal gate layer on the other side of fin.The direction of first inclination injection and the second inclination
The direction of injection can be substantially symmetric about the direction perpendicular to substrate surface, and the Implantation Energy of the two and implantation dosage can be with
It is roughly the same.In this way, side wall of the Metal gate layer in this two sides can be adulterated substantially evenly.But Metal gate layer is in fin
Roof on top surface receives more first kind doping.Therefore, the Second Type complementary with the first kind can be carried out
Vertical injection, which is approximately perpendicular to substrate surface.The Implantation Energy and implantation dosage injected vertically can be with
It is roughly the same with the Implantation Energy of the first and second inclination injections and implantation dosage.Then, the roof of Metal gate layer receive compared with
More compensation, so as to realize substantially uniform first kind doping on the side wall with Metal gate layer.
First inclination injection, the second inclination injection and the sequence injected vertically can change.In addition, in each injection
Injection direction, Implantation Energy and implantation dosage also can change.
Then, such a semiconductor devices has been obtained, which includes that fin and the grid intersected with fin stack
(including gate dielectric layer and Metal gate layer).Relative to the side wall of Metal gate layer, the roof of Metal gate layer may include higher
The dopant of the dopant of one type and the higher Second Type complementary with the first kind, so that Metal gate layer is on the whole
Existing substantially uniform first kind doping.
Therefore, substantially uniform work function, which is adjusted, to be realized to Metal gate layer, and therefore can had with semiconductor devices
The threshold voltage being substantially evenly distributed.
The disclosure can be presented in a variety of manners, some of them example explained below.In the following description, it provides perhaps
More details, adequately to be illustrated.However, it should be understood that can be real in the case where not having these part or all of details
Apply the technology of the disclosure.
As shown in Figure 1, providing substrate 1002.The substrate 1002 can be various forms of substrates, such as, but not limited to body
Semiconductive material substrate such as body Si substrate, semiconductor-on-insulator (SOI) substrate, SiGe substrate etc..In the following description, it is
Facilitate explanation, is described by taking body Si substrate as an example.
In substrate 1002, N-shaped trap 1002-1 and p-type trap 1002-2 can be formed, for being then respectively formed p wherein
Type device and n-type device.For example, N-shaped trap 1002-1 can by substrate 1002 implant n-type impurity such as P or As formed,
P-type trap 1002-2 can by substrate 1002 implanted with p-type impurity such as B formed.If desired, after injection it can be with
It anneals.Those skilled in the art are it is conceivable that various ways form N-shaped trap, p-type trap, and details are not described herein.
It is to be herein pointed out although illustrating to form complementor in N-shaped trap and p-type trap respectively in the following description
The technique of part, but the present disclosure is not limited thereto.For example, the disclosure is equally applicable to incomplementarity technique.Moreover, being related to complementation below
Some processing of device, it is necessary for not being in some implementations.
Then, substrate 1002 can be patterned, to form fin.For example, this can be carried out as follows.Specifically, it is serving as a contrast
The photoresist 1004 of composition is formed on bottom 1002 by design.In general, photoresist 1004 is patterned to along first direction (in figure vertically
In the direction of paper) extend series of parallel equidistant lines.Then, as shown in figure 3, the photoresist 1004 with composition is
Mask carries out selective etch such as reactive ion etching (RIE) to substrate 1002, to form the fin extended in a first direction
Structure 1006-1,1006-2 and 1006-3.
In the case where complementary process, can also as shown in Figures 4 and 5, between n-type region and p-type area formed every
From.Specifically, as shown in figure 4, photoresist 1008 can be formed on substrate 1002, and photoresist 1008 is patterned, with
Expose the certain area between n-type region and p-type area around interface.Then, as shown in figure 5, for example by selective etch
RIE removes substrate portions (including fin structure 1006-3) existing for the region.To be formed between n-type region and p-type area
Isolator band, isolator band can then be filled by dielectric for this.It is then possible to remove photoresist 1008.
It can be seen that the etch step for forming fin structure enters in trap 1002-1,1002-2 in the operation of Fig. 3；So
Afterwards, by the operation in Figure 4 and 5, the contact area (that is, area of the pn-junction formed) between p-type trap and N-shaped trap can be made
It is smaller.But the present disclosure is not limited thereto.For example, in incomplementarity technique, or in the part of single type (p-type or N-shaped) device
Region can not enter in trap the etching of substrate 1002 in Fig. 3；Operation shown in Figure 4 and 5 may also be not necessary
's.
In the example of fig. 3, by being directly patterned to substrate 1002, fin structure is formd.But the disclosure is unlimited
In this.For example, it is also possible to by being formed on the substrate and (e.g., depositing) other semiconductor layer, and the semiconductor layer other to this
It is patterned to form fin structure.There is the case where enough Etch selectivities between the other semiconductor layer and substrate
Under, etching can stop at substrate, so as to the height of the fin structure controlled well.Therefore, in the language of the disclosure
In border, statement " fin (structure) is formed on the substrate " includes being formed on the substrate in any suitable manner fin (structure), is stated
" fin (structure) formed on a substrate " includes any appropriate fin (structure) formed on a substrate.
In addition, the shape for being formed by groove (between fin structure) due to the characteristic of etching can be from top to bottom gradually
Contracting.It should be pointed out that being formed by the position of fin structure, number and layout is not limited to example shown in Fig. 3.
In the example depicted in fig. 3, the interface between N-shaped trap 1002-1 and p-type trap 1002-2, also forms fin knot
Structure 1006-3.Formation process is isolated as shown in Figure 4 and 5, which is also removed.
After forming fin structure by above-mentioned processing, the grid that can be developed across fin structure are stacked, and are formed finally
Semiconductor devices.
For isolated gate stacking and substrate, separation layer can be formed on the substrate.For example, separation layer can be formed.
Specifically, as shown in fig. 6, dielectric substance 1010 can be formed and (e.g., deposited) on the substrate 1002 for being formed with fin structure.Electricity
Dielectric material 1010 may include oxide (for example, silica), and thickness is enough to cover fin structure 1006-1 and 1006-2
Entire height.The dielectric substance 1010 of deposit can be planarized, such as (CMP) be chemically-mechanicapolish polished, to make it have
Substantially planar surface.Then, as shown in fig. 7, being etched back to dielectric substance 1010 so that fin structure 1006-1 and
1006-2 exposes.Dielectric substance after eatch-back forms separation layer 1010 '.Fin structure 1006-1 and 1006-2 expose part with
It is used as the real fin of resulting devices afterwards.Here, the top surface of separation layer 1010 ' can be big with the top surface of well region 1002-1,1002-2
It is fair or slightly lower (difference in height between them is not showed that in figure) to cause.
Optionally, in order to improve device performance, break-through blocking portion (PTS) can be formed in the substrate below fin.For n
Type device and p-type device, PTS can be respectively formed.For example, can use above photoresist overlay N-shaped trap 1002-1, then into
Row ion implanting.The ion of injection can be diffused into via separation layer 1010 ' and be isolated in the substrate that layer 1010 ' is surrounded.It is right
The n-type device to be formed in p-type trap 1002-2, can be injected n-type impurity, such as B, BF2Or In.The peak concentration of injection is for example
It can be about 1E18-2E19cm-3.Then photoresist can be removed.Likewise it is possible to utilize photoresist overlay p-type trap 1002-2
Then top carries out ion implanting.For p-type device to be formed in N-shaped trap 1002-1, p-type impurity can be injected, such as As or
Sb.The peak concentration of injection for example can be about 1E18-2E19cm-3.Then photoresist can be removed.Due to the form factor of fin
(elongate), most of ion can scatter fin, to be conducive to form precipitous dopant profiles in depth direction.It can be into
Row annealing, to activate the impurity of injection.
Then, it can be stacked in the sacrificial gate that separation layer 1010 ' is above developed across fin.For example, this can be carried out as follows.
Specifically, as shown in figure 8, being formed for example by deposit and sacrificing gate dielectric layer 1012-1 and 1012-2.For example, sacrificial
Domestic animal gate dielectric layer 1012-1 and 1012-2 may include oxide, with a thickness of about 0.8-1.5nm.In the example depicted in fig. 8, only
Show the sacrifice gate dielectric layer of " ∏ " shape.But sacrificing gate dielectric layer also may include prolonging on the top surface of separation layer 1010 '
The part stretched.Then, such as by deposit, sacrificial gate conductor layer 1014 is formed.For example, sacrificial gate conductor layer 1014 may include
Polysilicon.Sacrificial gate conductor layer 1014 can fill the gap between fin, and can carry out planarization process such as CMP.Later,
Sacrificial gate conductor layer 1014 is patterned, to form sacrificial gate stacking.As shown in Fig. 9 and 9A, 1014 quilt of sacrificial gate conductor layer
Be patterned into along intersects with first direction (for example, vertical) second direction (horizontal direction in Fig. 9) extension bar shaped 1014-1 and
1014-2, to intersect respectively with corresponding fin.It according to another embodiment, can be with the sacrificial gate conductor layer 1014-1 after composition
It is mask with 1014-2, further sacrifice gate dielectric layer 1012-1 and 1012-2 is patterned.It can be stacked as covering with sacrificial gate
Mould carries out the injection of source drain extension area；Optionally, haloing injection can also be carried out.For n-type device and p-type device, source/drain is prolonged
Stretch area's injection, haloing injection can carry out (when injecting a kind of device, can use mask such as photoresist and blocking respectively
Another device).
Next, as shown in Figure 10, can be stacked in sacrificial gate (in this example, sacrificial gate conductor 1014-1 with
On side wall 1014-2), grid side wall 1016-1 and 1016-2 is formed.For example, dielectric layer (example can be formed on separation layer
Such as, the nitride that thickness is about 5-30nm), and anisotropic etching is carried out to dielectric layer, to form side wall.Art technology
Personnel know various ways to form this side wall, and details are not described herein.Sacrificial gate can stack to (mainly sacrificial gate is led
Body) height be set as twice of at least fin height, such side wall can be substantially not formed on the side wall of fin.It can be sacrificial
Domestic animal grid stack and grid side wall is mask, carry out source drain implant.For n-type device and p-type device, source drain implant can respectively into
Row (when being injected to a kind of device, can use mask such as photoresist and block another device).Then, it can be moved back
Therefore fire to activate the ion of injection, and forms source region and drain region.
After being respectively formed the source/drain region of n-type device and p-type device as described above, replacement gate process can be carried out, with
It substitutes sacrificial gate to stack, the real grid for forming resulting devices stack.For example, this can be carried out as follows.
As shown in Figure 11,11A, 11B and 11C, such as by deposit, form dielectric layer 1018.Place near the steps dielectric layer 1018
It such as may include oxide.Then, planarization process such as CMP is carried out to the dielectric layer 1018.The CMP can be stopped at
Side wall 1016-1,1016-2, to expose sacrificial gate conductor 1014-1,1014-2.
Then, as shown in Figure 12,12A, 12B and 12C, such as pass through TMAH solution, selective removal sacrificial gate conductor
1014-1,1014-2, to form grid slot 1020-1,1020-2 on the inside of side wall 1016-1,1016-2.Shown according to another
Example can also be removed further and sacrifice gate dielectric layer 1012-1,1012-2.
Then, as shown in Figure 13 A, 13B and 13C, in grid slot 1020-1,1020-2, in the table of fin 1006-1,1006-2
Boundary layer 1022-1,1022-2 are formed on face.For example, boundary layer 1022-1,1022-2 may include oxide (for example, passing through
Thermal oxide or deposit and formed), with a thickness of about 0.2-1.1nm.It is then possible to form (example in grid slot 1020-1,1020-2
Such as, deposit) gate dielectric layer 1024-1,1024-2 and Metal gate layer 1026-1,1026-2.Gate dielectric layer 1024-1,1024-2 can
To include high-K gate dielectric such as HfO2, with a thickness of about 1-5nm.Metal gate layer 1026-1,1026-2 may include that metallicity grid are led
Body such as TiN.It is to be herein pointed out gate dielectric layer/Metal gate layer stacking can have for n-type device and p-type device
Different configurations (material difference and/or thickness difference etc.).In this case, shape can be distinguished for n-type device and p-type device
It is stacked at grid.In this example, gate dielectric layer and Metal gate layer are not completely filled with grid slot 1020-1,1020-2.
In accordance with an embodiment of the present disclosure, the work function of Metal gate layer 1026-1,1026-2 can be adjusted by injecting, and
Therefore the threshold voltage of adjusting means.For example, this can be carried out as follows.
As shown in figure 14, it can use photoresist 1028-1 masking p-type device region.Photoresist 1028-1 preferably extends
Onto the dielectric layer 1018 between p-type device region and n-type device region, to ensure to block p-type device region completely.So
Afterwards, the first inclination can be carried out using the dopant of the first kind to this side (in particular, Metal gate layer 1026-2) of n-type device
Injection.Here, so-called " inclination ", referred to relative to substrate surface inclination (that is, deviateing the direction vertical with substrate surface).First
The direction for tilting injection can be (in figure right towards first side of the Metal gate layer 1026-2 in second direction (horizontal direction in figure)
Side) side wall.Here, so-called refer to relative to vertical injection " towards side wall " (that is, injection direction is approximately perpendicular to substrate table
Face), angle formed by normal direction of the injection direction with the side wall is smaller.In the example in figure 14, the direction of the first inclination injection is in paper
In facial plane (that is, second direction and plane defined by the direction perpendicular to substrate surface).But the present disclosure is not limited thereto,
The direction of first inclination injection can also deviate paper plane.For n-type device, the dopant of the first inclination injection may include
P, one of As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of, Implantation Energy can be about 0.2-30keV, injectant
Amount can be about 1E13-1E15cm-2。
Then, as shown in figure 15, it can use the dopant with same type in the first inclination injection, carry out the second inclination
Injection.The direction of second inclination injection can towards Metal gate layer 1026-2 in second direction (horizontal direction in figure) with first
The side wall of opposite second side in side (left side in figure).In the example of fig. 15, the direction of the second inclination injection is in paper plane.
But the present disclosure is not limited thereto, the direction of the second inclination injection can also deviate paper plane.For n-type device, the second inclination
The dopant of injection may include one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of, and Implantation Energy can be with
It is about 0.2-30keV, implantation dosage can be about 1E13-1E15cm-2。
Preferably, the direction of the first inclination injection and the direction of the second inclination injection are about the direction perpendicular to substrate surface
It is substantially symmetric, and the Implantation Energy of the two and implantation dosage are roughly the same.In this case, at left and right sides of Metal gate layer 1026-2
Side wall by roughly the same injection rate, so that there is each the first kind of roughly the same (and uniformly) to adulterate (example
Such as, doping concentration C).
But the present disclosure is not limited thereto.It can be according to the actual situation (for example, the side at left and right sides of Metal gate layer 1026-2
Wall tilt condition) the first inclination of adjustment is injected and respective direction, Implantation Energy and implantation dosage are injected in the second inclination, as long as side
Wall can obtain roughly the same doping.
On the other hand, the roof of Metal gate layer 1026-2 tilts first and second and receives injection in injection, and because
This with relatively high first kind doping (for example, doping concentration is about 2C, this is because in each injection, roof with
The case where side wall is influenced by injection is roughly the same, and except non-implanted tilt angle is excessive, this is uncommon).
For the roof of Metal gate layer 1026-2, can compensate.Specifically, as shown in figure 16, it can use and the
The dopant of the Second Type of one type complementation carries out third injection, and the direction of the injection is approximately perpendicular to substrate surface.In addition,
(and therefore third injection can have roughly the same Implantation Energy and roughly the same implantation dosage with the first and second injections
Lead to the compensation rate of about-C at roof；For side wall, vertical injection influences smaller).For n-type device, the doping of third injection
Agent may include In, B, BF2, one of Ru, W, Mo, A1, Ga and Pt or a variety of, Implantation Energy can be about 0.2-30keV,
Implantation dosage can be about 1E13-1E15cm-2.In this way, reducing the roof of Metal gate layer 1026-2, (upper right is to lower left in figure
To oblique scribing line at) at first kind doping, keep the first kind doping of itself and the side-walls of Metal gate layer 1026-2
Roughly the same (for example, 2C+ (- C)=C).To realize the roof and side-walls substantially uniform the of Metal gate layer 1026-2
The doping of one type.
It is to be herein pointed out the roof and side wall of Metal gate layer 1026-2 described herein refer to Metal gate layer
1026-2 is located at roof and side wall on fin 1006-2.And the other parts that Metal gate layer 1026-2 extends in grid slot 1020-2
(for example, be located at side wall 1016-2 on part) due to not directly affecting device threshold voltage, so in these parts
Doping concentration herein not pay special attention to.In addition, the dopant used in the first, second inclination injection is injected in third
Used in dopant can exchange.Specifically, the dopant of Second Type can be used in the first, second inclination injection,
Such as In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of, mixing for the first kind can be used in third injection
Miscellaneous dose, such as one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of.
After realizing to the roof of Metal gate layer 1026-2 and the Uniform Doped of side wall, photoresist can be removed
1028-1.Then, similar operation can be carried out to p-type device.
Specifically, as shown in figure 17, it can use photoresist 1028-2 masking n-type device region.Photoresist 1028-2 is excellent
Selection of land extends on the dielectric layer 1018 between p-type device region and n-type device region, to ensure to block n-type device completely
Region.It is then possible to be carried out to this side (in particular, Metal gate layer 1026-1) of p-type device using the dopant of Second Type
First inclination injection.The direction of first inclination injection can be towards Metal gate layer 1026-1 in second direction (horizontal direction in figure)
On the first side (in figure right side) side wall.In the example of Figure 17, the direction of the first inclination injection is in paper plane.But
It is that the present disclosure is not limited thereto, the direction of the first inclination injection can also deviate paper plane.For p-type device, the first inclination note
The dopant entered may include In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of, Implantation Energy can be about
0.2-30keV, implantation dosage can be about 1E13-1E15cm-2。
Then, as shown in figure 18, it can use the dopant with same type in the first inclination injection, carry out the second inclination
Injection.The direction of second inclination injection can towards Metal gate layer 1026-1 in second direction (horizontal direction in figure) with first
The side wall of opposite second side in side (left side in figure).In the example of Figure 18, the direction of the second inclination injection is in paper plane.
But the present disclosure is not limited thereto, the direction of the second inclination injection can also deviate paper plane.For p-type device, the second inclination
The dopant of injection may include In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of, Implantation Energy can be about
0.2-30keV, implantation dosage can be about 1E13-1E15cm-2。
Preferably, the direction of the first inclination injection and the direction of the second inclination injection are about the direction perpendicular to substrate surface
It is substantially symmetric, and the Implantation Energy of the two and implantation dosage are roughly the same.In this case, at left and right sides of Metal gate layer 1026-1
Side wall by roughly the same injection rate, so that each has the Second Type doping of roughly the same (and uniformly).
But the present disclosure is not limited thereto.It can be according to the actual situation (for example, the side at left and right sides of Metal gate layer 1026-1
Wall tilt condition) the first inclination of adjustment is injected and respective direction, Implantation Energy and implantation dosage are injected in the second inclination, as long as side
Wall can obtain roughly the same doping.
On the other hand, the roof of Metal gate layer 1026-1 tilts first and second and receives injection in injection, and because
This is adulterated with relatively high Second Type.
For the roof of Metal gate layer 1026-1, can compensate.Specifically, as shown in figure 19, it can use and the
The dopant of the first kind of two types complementation carries out third injection, and the direction of the injection is approximately perpendicular to substrate surface.In addition,
Third injection can have roughly the same Implantation Energy and roughly the same implantation dosage with the first and second injections.For p
The dopant of type device, third injection may include one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of, note
Entering energy can be about 0.2-30keV, and implantation dosage can be about 1E13-1E15cm-2.In this way, reducing Metal gate layer 1026-
Second Type doping at 1 roof (in figure at upper left to the oblique scribing line of lower right), makes itself and Metal gate layer 1026-1's
Second Type doping at roof keeps roughly the same.To which the roof and side-walls for realizing Metal gate layer 1026-1 are substantially
Uniform Second Type doping.
In this way, realizing the uniform Second Type doping to the roof and side wall of Metal gate layer 1026-1.It is then possible to go
Except photoresist 1028-2.
Similarly, the dopant used in the first, second inclination injection can with the dopant used in third injection
With exchange.Specifically, can be used the dopant of the first kind in the first, second inclination injection, for example, P, As, Sb, La,
One of Er, Dy, Gd, Sc, Yb and Tb or a variety of, can be used the dopant of Second Type in third injection, such as In,
B、BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of.
It is to be herein pointed out under this exemplary complementary process condition, to n-type device and p-type device respectively into
Row processing.But the present disclosure is not limited thereto.For example, in incomplementarity technique, it can be without such masking.In addition, at this
In example, p-type device region is first covered, n-type device region is handled.But the present disclosure is not limited thereto.To n-type device
The order that region and p-type device region are handled can exchange.Moreover, being directed to same device, the sequence of each injection can also
To change.
After the work function as described above to Metal gate layer carries out even regulation, the subsequent production of device can be completed.
For example, as shown in Figure 20,20A, 20B and 20C gate electrode layer 1030- can be further formed in grid slot 1020-1,1020-2
1,1030-2.For example, gate electrode layer may include W or TiAl, thickness is enough to fill up grid slot 1020-1,1020-2.Then, may be used
To carry out planarization process such as CMP, to remove the part that gate dielectric layer, Metal gate layer and gate electrode layer are located at except grid slot.It should
Planarization process can be terminal with dielectric layer 1018.Next, interlevel dielectric layer and wherein can also be deposited further
Form contact portion (not shown).
In this way, just having obtained semiconductor devices according to this embodiment.As shown in Figure 20,20A, 20B and 20C, semiconductor
Device include formed on substrate 1002 along first direction (vertical direction in Figure 20) extend fin 1006-1/1006-2 with
And the grid that (horizontal direction in Figure 20) in a second direction formed on substrate 1002 extends stack, grid are stacked including successively heap
Folded gate dielectric layer 1024-1/1024-2 and Metal gate layer 1026-1/1026-2.In a second direction relative to Metal gate layer
Opposite sides (in Figure 20 A left and right sides the) side wall, the roof of Metal gate layer include the dopant of the higher first kind with
And the dopant of the higher Second Type complementary with the first kind, so that Metal gate layer is presented substantially uniform first on the whole
Type doping.In the above description, they are separated by the case where combining n-type device and p-type device using "/".
In addition, in the above examples, being described for replacement gate process.But the present disclosure is not limited thereto.For example,
The disclosure is equally applicable to first grid technique.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from
The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the disclosure
Within the scope of.
Claims (10)
1. a kind of method of manufacturing semiconductor devices, comprising:
The fin extended in a first direction is formed on the substrate；
It is formed on the substrate and is stacked along the grid that the second direction intersected with first direction extends, it includes stacking gradually that wherein grid, which stack,
Gate dielectric layer and Metal gate layer；
The first inclination injection is carried out using the dopant of the first kind, wherein the direction of the first inclination injection exists towards Metal gate layer
Side wall on first side of fin；
The second inclination injection is carried out using first kind dopant, wherein the direction of the second inclination injection is towards Metal gate layer in fin
Second side opposite with the first side on side wall；
Third injection is carried out using the Second Type dopant complementary with the first kind, wherein the direction of third injection is substantially vertical
In the surface of substrate.
2. according to the method described in claim 1, wherein, the direction of the direction of the first inclination injection and the second inclination injection about
It is substantially symmetric perpendicular to the direction of substrate surface, and the Implantation Energy of the two and implantation dosage are roughly the same.
3. according to the method described in claim 1, wherein, third injection has roughly the same injection with the first and second injections
Energy and roughly the same implantation dosage.
4. according to the method described in claim 1, wherein,
First kind dopant includes one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of, and Second Type is mixed
Miscellaneous dose includes In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of；Or
First kind dopant includes In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of, Second Type dopant
Including one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of.
5. according to the method described in claim 1, wherein, the first inclination injection, the second inclination injection and third injection are respective
Implantation Energy is 0.2-30keV, implantation dosage 1E13-1E15cm-2。
6. according to the method described in claim 1, wherein, forming grid stacking includes:
The sacrificial gate extended in a second direction is formed on the substrate to stack, it includes the sacrifice gate medium stacked gradually that sacrificial gate, which stacks,
Layer and sacrificial gate conductor layer；
Grid side wall is formed on the side wall that sacrificial gate stacks；
Dielectric layer is formed on the substrate, and is planarized, to expose sacrificial gate stacking；
Selective removal sacrificial gate stacks, to form grid slot on the inside of grid side wall；
Gate dielectric layer and Metal gate layer are formed in grid slot.
7. according to the method described in claim 6, further include:
Gate electrode layer is further formed in the grid slot for being formed with gate dielectric layer and Metal gate layer.
8. a kind of semiconductor devices, comprising:
The fin formed on a substrate extended in a first direction；
The grid that edge formed on a substrate extends with the second direction that first direction intersects stack, and wherein grid are stacked including successively heap
Folded gate dielectric layer and Metal gate layer,
Wherein, implantation dosage of the Metal gate layer in the roof on the top surface of fin comprising first kind dopant subtracts Second Type
The difference of the implantation dosage of dopant is substantially equal, Second Type with the implantation dosage of the first kind dopant on side wall
Dopant is complementary with first kind dopant.
9. semiconductor devices according to claim 8, wherein
First kind dopant includes one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of, and Second Type is mixed
Miscellaneous dose includes In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of；Or
First kind dopant includes In, B, BF2, one of Ru, W, Mo, Al, Ga and Pt or a variety of, Second Type dopant
Including one of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb or a variety of.
10. semiconductor devices according to claim 8, wherein Metal gate layer includes TiN.
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| CN1691294A (en) * | 2004-04-28 | 2005-11-02 | 国际商业机器公司 | Backgated finfet having diferent oxide thicknesses |
| WO2010079389A1 (en) * | 2009-01-12 | 2010-07-15 | Nxp B.V. | Semiconductor device and method of manufacturing a semiconductor device |
| CN103903985A (en) * | 2012-12-27 | 2014-07-02 | 台湾积体电路制造股份有限公司 | Methods for forming finfets with self-aligned source/drain FinFET |
| CN103943485A (en) * | 2014-04-28 | 2014-07-23 | 上海华力微电子有限公司 | Method for forming grid with variable horizontal direction work function |
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| US6821834B2 (en) * | 2002-12-04 | 2004-11-23 | Yoshiyuki Ando | Ion implantation methods and transistor cell layout for fin type transistors |
| KR101850703B1 (en) * | 2011-05-17 | 2018-04-23 | 삼성전자 주식회사 | Semiconductor device and method for fabricating the device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691294A (en) * | 2004-04-28 | 2005-11-02 | 国际商业机器公司 | Backgated finfet having diferent oxide thicknesses |
| WO2010079389A1 (en) * | 2009-01-12 | 2010-07-15 | Nxp B.V. | Semiconductor device and method of manufacturing a semiconductor device |
| CN103903985A (en) * | 2012-12-27 | 2014-07-02 | 台湾积体电路制造股份有限公司 | Methods for forming finfets with self-aligned source/drain FinFET |
| CN103943485A (en) * | 2014-04-28 | 2014-07-23 | 上海华力微电子有限公司 | Method for forming grid with variable horizontal direction work function |
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