CN105609470A - Semiconductor device with uniform threshold voltage distribution, and manufacturing method thereof - Google Patents
Semiconductor device with uniform threshold voltage distribution, and manufacturing method thereof Download PDFInfo
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- CN105609470A CN105609470A CN201510516131.XA CN201510516131A CN105609470A CN 105609470 A CN105609470 A CN 105609470A CN 201510516131 A CN201510516131 A CN 201510516131A CN 105609470 A CN105609470 A CN 105609470A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 78
- 229910052751 metal Inorganic materials 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000002347 injection Methods 0.000 claims description 41
- 239000007924 injection Substances 0.000 claims description 41
- 238000002513 implantation Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 11
- 229910052787 antimony Inorganic materials 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 9
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 9
- 229910052738 indium Inorganic materials 0.000 claims description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 9
- 229910052771 Terbium Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims 2
- 230000000295 complement effect Effects 0.000 abstract description 5
- 239000002019 doping agent Substances 0.000 abstract description 3
- 229940090044 injection Drugs 0.000 description 35
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 238000000926 separation method Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
There is provided a semiconductor device with uniform threshold voltage distribution, and a manufacturing method thereof. According to an embodiment, the semiconductor device can comprises fins formed on a substrate and extending along a first direction, and a gate stack formed on the substrate and extending along a second direction intersecting with the first direction, wherein the gate stack comprises gate dielectric layers and metal gate layers which are stacked sequentially, and the top wall of each metal gate layer on the top surfaces of the fins contains a higher dopant of a first type and a higher dopant of a second type complementary to the first type when compared with the side walls of the metal gate layer on two opposite sides of the fins, thereby presenting substantially uniform first-type doping on the overall metal gate layers.
Description
Technical field
The disclosure relates to semiconductor applications, more specifically, relates to a kind of semiconductor devices and manufacture method thereof that even threshold voltage distributes that have.
Background technology
Along with the size of planar-type semiconductor device is more and more less, short-channel effect is further obvious. For this reason, solid type semiconductor devices has been proposed as FinFET (fin formula field effect transistor). Generally speaking, FinFET be included on substrate the fin that vertically forms and grid crossing with fin stacking. Grid are stacking can comprise high K/ metal gate configuration. By injecting, regulate the work function of metal gate, can adjust the threshold voltage of FinFET. But profit in this way, is difficult to make the ion injecting to be uniformly distributed at metal gate, thereby is difficult to realize being uniformly distributed of threshold voltage.
Summary of the invention
Object of the present disclosure is to provide a kind of semiconductor devices and manufacture method thereof that even threshold voltage distributes that have at least in part.
According to an aspect of the present disclosure, a kind of method of manufacturing semiconductor devices is provided, comprising: on substrate, form the fin extending along first direction; On substrate, form along the grid of the second direction extension intersecting with first direction stacking, the wherein stacking gate dielectric layer and the metal gate layer that stack gradually of comprising of grid; Utilize the adulterant of the first kind to carry out the first inclination injection, the direction that wherein the first inclination is injected is the sidewall in the first side at fin towards metal gate layer; Utilize the adulterant of the first kind to carry out the second inclination injection, the direction that wherein the second inclination is injected is the sidewall in second side contrary with the first side at fin towards metal gate layer; Utilization is carried out the 3rd injection with the adulterant of the Second Type of first kind complementation, and wherein the 3rd direction of injecting is approximately perpendicular to the surface of substrate.
According to another aspect of the present disclosure, a kind of semiconductor devices is provided, comprising: the fin extending along first direction forming on substrate; The grid that extend along the second direction of intersecting with first direction that form on substrate are stacking, the wherein stacking gate dielectric layer and the metal gate layer that stack gradually of comprising of grid, wherein, sidewall with respect to metal gate layer on the relative both sides of fin, the adulterant of the adulterant that the roof of metal gate layer on the end face of fin comprises the higher first kind and Second Type higher and first kind complementation, thus metal gate layer presents roughly first kind doping uniformly on the whole.
According to embodiment of the present disclosure, can carry out the inclination of twice first kind and inject. Like this, two sidewall of metal gate layer on fin both sides can be accepted roughly to adulterate uniformly. On the other hand, the roof of metal gate layer on the end face of fin accepted more first kind doping. Can carry out the vertical injection with the Second Type of first kind complementation. So the roof of metal gate layer has been subject to more compensation, thereby metal gate layer can show roughly first kind doping uniformly. Like this, the work function of metal gate layer can obtain roughly regulating uniformly, and therefore semiconductor devices can show roughly equally distributed threshold voltage.
Brief description of the drawings
By the description to disclosure embodiment referring to accompanying drawing, above-mentioned and other objects of the present disclosure, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1-Figure 20 C is that wherein Fig. 9 A is the sectional view along AA ' line in Fig. 9 according to the schematic diagram of the manufacture semiconductor devices flow process of disclosure embodiment; Figure 11 A is the sectional view along AA ' line in Figure 11, and Figure 11 B is the sectional view along BB ' line in Figure 11, and Figure 11 C is the sectional view along CC ' line in Figure 11; Figure 12 A is the sectional view along AA ' line in Figure 12, and Figure 12 B is the sectional view along BB ' line in Figure 12, and Figure 12 C is the sectional view along CC ' line in Figure 12; Figure 13 A, 13B, 13C are respectively and Figure 12 A, 12B, sectional view that 12C is corresponding; Figure 20 A is the sectional view along AA ' line in Figure 20, and Figure 20 B is the sectional view along BB ' line in Figure 20, and Figure 20 C is the sectional view along CC ' line in Figure 20; .
Detailed description of the invention
Below, embodiment of the present disclosure is described with reference to the accompanying drawings. But should be appreciated that, these descriptions are exemplary, and do not really want to limit the scope of the present disclosure. In addition, in the following description, omitted the description to known features and technology, to avoid unnecessarily obscuring concept of the present disclosure.
Shown in the drawings according to the various structural representations of disclosure embodiment. These figure not draw in proportion, wherein, for the clear object of expressing, have amplified some details, and may omit some details. The shape of the various regions shown in figure, layer and relative size, the position relationship between them are only exemplary, may be due to manufacturing tolerance or technical limitations in reality and deviation to some extent, and those skilled in the art according to reality required can design in addition there is difformity, the regions/layers of size, relative position.
In context of the present disclosure, when one deck/element is called be positioned at another layer/element " on " time, this layer/element can be located immediately on this another layer/element, or can have intermediate layer/element between them. In addition, if one towards middle one deck/element be positioned at another layer/element " on ", so when turn towards time, this layer/element can be positioned at this another layer/element D score.
According to embodiment of the present disclosure, on substrate, form after fin and grid stacking (comprising gate dielectric layer and metal gate layer) crossing with fin, can inject metal gate layer, to regulate its work function. For uniformity, this injection can be carried out several times. For example, can utilize the adulterant of the first kind to carry out the first inclination injection, the direction that wherein the first inclination is injected is the sidewall in the side at fin towards metal gate layer; Can utilize the adulterant of the first kind to carry out the second inclination injection, the direction that wherein the second inclination is injected is the sidewall on the opposite side at fin towards metal gate layer. The first direction that tilts to inject and the second direction that tilts to inject can be roughly symmetrical about the direction perpendicular to substrate surface, and both Implantation Energies and implantation dosage can be roughly the same. Like this, metal gate layer can roughly be adulterated equably at the sidewall of these both sides. But the roof of metal gate layer on the end face of fin accepted more first kind doping. Therefore, can carry out and the vertical injection of the Second Type of first kind complementation, this direction of vertically injecting is approximately perpendicular to substrate surface. The Implantation Energy vertically injecting and implantation dosage can be roughly the same with Implantation Energy and implantation dosage that the first and second inclinations are injected. So the roof of metal gate layer has been subject to more compensation, thus can with the sidewall of metal gate layer on realize roughly uniformly first kind doping.
First tilts, and injection, second tilts to inject and the vertical order of injecting can change. In addition the injection direction, Implantation Energy and the implantation dosage that inject for each time, also can change.
So, obtaining so a kind of semiconductor devices, this semiconductor devices comprises fin and the grid stacking (comprise gate dielectric layer and metal gate layer) crossing with fin. With respect to the sidewall of metal gate layer, the roof of metal gate layer can comprise the adulterant of the higher first kind and the adulterant of Second Type higher and first kind complementation, thereby metal gate layer presents roughly first kind doping uniformly on the whole.
Therefore, can realize roughly work function uniformly to metal gate layer and regulate, and therefore can there is roughly equally distributed threshold voltage by semiconductor devices.
The disclosure can present by various forms, below will describe some of them example. In the following description, many details are provided, to illustrate fully. But should be appreciated that, can in the situation that not possessing part or all of these details, implement technology of the present disclosure.
As shown in Figure 1, provide substrate 1002. This substrate 1002 can be various forms of substrates, such as but not limited to bulk semiconductor material substrate as body Si substrate, semiconductor-on-insulator (SOI) substrate, SiGe substrate etc. In the following description, for convenience of description, be described as an example of body Si substrate example.
In substrate 1002, can form N-shaped trap 1002-1 and p-type trap 1002-2, for forming respectively therein subsequently p-type device and N-shaped device. For example, N-shaped trap 1002-1 can form as P or As by Implanted n-Type impurity in substrate 1002, and p-type trap 1002-2 can form as B by inject p-type impurity in substrate 1002. If needed, after injecting, can also anneal. Those skilled in the art can expect that various ways forms N-shaped trap, p-type trap, does not repeat them here.
Although it is pointed out that here the technique that forms respectively complementary device in N-shaped trap and p-type trap has been described in the following description, the disclosure is not limited to this. For example, the disclosure is equally applicable to incomplementarity technique. And, below relate to some processing of complementary device, in some implementation, be not necessary.
Subsequently, can carry out composition to substrate 1002, to form fin. For example, this can carry out as follows. Particularly, on substrate 1002, press the photoresist 1004 of design forming composition. Conventionally, photoresist 1004 is patterned to the equidistant lines of the series of parallel of extending along the first direction direction of paper (in the figure perpendicular to). Then, as shown in Figure 3, taking the photoresist 1004 of composition as mask, substrate 1002 is carried out to for example reactive ion etching of selective etch (RIE), thereby form fin structure 1006-1, the 1006-2 and the 1006-3 that extend along first direction.
The in the situation that of complementary process, can also be as shown in Figures 4 and 5, carry out to form isolation between HepXing region, N-shaped region. Particularly, as shown in Figure 4, can on substrate 1002, form photoresist 1008, and photoresist 1008 is carried out to composition, to expose interface certain area around between HepXing region, N-shaped region. Then, as shown in Figure 5, by such as RIE of selective etch, remove the substrate part (comprising fin structure 1006-3) that this region exists. Thereby between HepXing region, N-shaped region, form isolation area, this isolation area can be filled by dielectric subsequently. Then, can remove photoresist 1008.
Can see, in the operation of Fig. 3, the etch step that forms fin structure enters into trap 1002-1,1002-2; Then,, by the operation in Figure 4 and 5, can make the contact area (, the area of the pn of formation knot) between p-type trap and N-shaped trap less. But the disclosure is not limited to this. For example, in incomplementarity technique, or at the regional area of single type (p-type or N-shaped) device, in Fig. 3, can not enter into trap to the etching of substrate 1002; Operation shown in Figure 4 and 5 may be not also necessary.
In the example of Fig. 3, by directly substrate 1002 being carried out to composition, form fin structure. But the disclosure is not limited to this. For example, also can be by form (as, deposit) other semiconductor layer on substrate, and this other semiconductor layer is carried out to composition form fin structure. Between this other semiconductor layer and substrate, have enough Etch selectivities, etching can stop at substrate, thereby can control well the height of the fin structure obtaining. Therefore, in linguistic context of the present disclosure, statement " forming fin (structure) on substrate " comprises and on substrate, forms in any suitable manner fin (structure), and statement " fin (structure) forming on substrate " is included in any appropriate fin (structure) forming on substrate.
In addition, due to the characteristic of etching, the shape of (between the fin structure) groove forming can be convergent from top to bottom. The position, number and the layout that it is pointed out that formed fin structure are not limited to the example shown in Fig. 3.
In the example depicted in fig. 3, the interface between N-shaped trap 1002-1 and p-type trap 1002-2, has also formed fin structure 1006-3. Because the isolation shown in Figure 4 and 5 forms technique, this fin structure is also removed.
After forming fin structure by above-mentioned processing, can form across the grid of fin structure stackingly, and form final semiconductor devices.
For isolated gate heap superimposition substrate, can on substrate, form separation layer. For example, separation layer can be formed. Particularly, as shown in Figure 6, can on the substrate 1002 that is formed with fin structure, form (as, deposit) dielectric substance 1010. Dielectric substance 1010 can comprise oxide (for example, silica), and its thickness is enough to cover the whole height of fin structure 1006-1 and 1006-2. Can carry out planarization to the dielectric substance of deposit 1010, as chemically mechanical polishing (CMP), to make it have smooth in fact surface. Then, as shown in Figure 7, dielectric substance 1010 is eat-back, fin structure 1006-1 and 1006-2 are exposed. Dielectric substance after eat-backing form separation layer 1010 '. The part that fin structure 1006-1 and 1006-2 expose is used as the real fin of resulting devices subsequently. At this, separation layer 1010 ' end face can and the end face of well region 1002-1,1002-2 roughly maintains an equal level or lower slightly (in figure and not shown difference in height between them).
Alternatively, in order to improve device performance, can in the substrate below fin, form break-through stop part (PTS). For N-shaped device and p-type device, PTS can form respectively. For example, can utilize photoresist to cover N-shaped trap 1002-1 top, then carry out Implantation. Inject ion can via separation layer 1010 ' and be diffused into be isolated layer 1010 ' around substrate. For the N-shaped device that will form in p-type trap 1002-2, can inject p-type impurity, as B, BF2Or In. The peak concentration injecting can be for example about 1E18-2E19cm-3. Then can remove photoresist. Similarly, can utilize photoresist to cover p-type trap 1002-2 top, then carry out Implantation. For the p-type device that will form in N-shaped trap 1002-1, can Implanted n-Type impurity, as As or Sb. The peak concentration injecting can be for example about 1E18-2E19cm-3. Then can remove photoresist. Due to the form factor (elongate) of fin, most of ion can scatter fin, thereby is conducive to form precipitous dopant profiles at depth direction. Can anneal, to activate the impurity of injection.
Subsequently, can separation layer 1010 ' on form stacking across the sacrificial gate of fin. For example, this can carry out as follows.
Particularly, as shown in Figure 8, for example, by deposit, form sacrificial gate dielectric layer 1012-1 and 1012-2. For example, sacrificial gate dielectric layer 1012-1 and 1012-2 can comprise oxide, and thickness is about 0.8-1.5nm. In the example depicted in fig. 8, only show the sacrificial gate dielectric layer of " ∏ " shape. But, sacrificial gate dielectric layer also can be included in separation layer 1010 ' end face on the part of extending. Then, for example,, by deposit, form sacrificial gate conductor layer 1014. For example, sacrificial gate conductor layer 1014 can comprise polysilicon. Sacrificial gate conductor layer 1014 can be filled the gap between fin, and can carry out such as CMP of planarization. Afterwards, sacrificial gate conductor layer 1014 is carried out to composition, stacking to form sacrificial gate. As shown in Fig. 9 and 9A, sacrificial gate conductor layer 1014 is patterned to along intersecting with first direction bar shaped 1014-1 and the 1014-2 of second direction (horizontal direction in Fig. 9) extension of (for example, vertical), thereby crossing with corresponding fin respectively. According to another embodiment, sacrificial gate conductor layer 1014-1 and 1014-2 after can also composition be mask, further sacrificial gate dielectric layer 1012-1 and 1012-2 are carried out to composition. Can sacrificial gate be stacked as mask, carry out source/drain extension region and inject; Alternatively, can also carry out haloing injection. For N-shaped device and p-type device, source/drain extension region is injected, haloing inject and can carry out respectively (in the time that a kind of device is injected, can utilize mask as photoresist blocks another kind of device).
Next, as shown in figure 10, can the sidewall of stacking in sacrificial gate (in this example, at sacrificial gate conductor 1014-1 and 1014-2) on, form grid side wall 1016-1 and 1016-2. For example, can on separation layer, form dielectric layer (for example, thickness is about the nitride of 5-30nm), and dielectric layer is carried out to anisotropic etching, form side wall. Those skilled in the art will know that various ways forms this side wall, does not repeat them here. It is at least the twice of fin height that height that can sacrificial gate stacking (being mainly sacrificial gate conductor) is set to, and side wall can not be formed on the sidewall of fin substantially like this. Can sacrificial gate heap superimposition grid side wall be mask, carry out source/leakage and inject. For N-shaped device and p-type device, source/leakage inject and can carry out respectively (in the time that a kind of device is injected, can utilize mask as photoresist blocks another kind of device). Subsequently, can anneal, to activate the ion of injection, and therefore form source region and drain region.
After forming respectively the source/drain region of N-shaped device and p-type device as mentioned above, can carry out replacement gate process, stacking to substitute sacrificial gate, the real grid that form resulting devices are stacking. For example, this can carry out as follows.
As shown in Figure 11,11A, 11B and 11C, for example, by deposit, form dielectric layer 1018. This dielectric layer 1018 for example can comprise oxide. Subsequently, this dielectric layer 1018 is carried out to such as CMP of planarization. This CMP can stop at side wall 1016-1,1016-2, thereby exposes sacrificial gate conductor 1014-1,1014-2.
Subsequently, as shown in Figure 12,12A, 12B and 12C, for example, by TMAH solution, selective removal sacrificial gate conductor 1014-1,1014-2, thus form grid groove 1020-1,1020-2 in side wall 1016-1,1016-2 inner side. According to another example, can also further remove sacrificial gate dielectric layer 1012-1,1012-2.
Then,, as shown in Figure 13 A, 13B and 13C, in grid groove 1020-1,1020-2, on the surface of fin 1006-1,1006-2, form boundary layer 1022-1,1022-2. For example, boundary layer 1022-1,1022-2 can comprise oxide (for example, forming by thermal oxide or deposit), and thickness is about 0.2-1.1nm. Then, can in grid groove 1020-1,1020-2, form (for example, deposit) gate dielectric layer 1024-1,1024-2 and metal gate layer 1026-1,1026-2. Gate dielectric layer 1024-1,1024-2 can comprise such as HfO of high-K gate dielectric2, thickness is about 1-5nm. Metal gate layer 1026-1,1026-2 can comprise that metallicity grid conductor is as TiN. Here it is pointed out that for N-shaped device and p-type device, the stacking of gate dielectric layer/metal gate layer can have different configuration (material difference and/or thickness are not equal). In this case, can form respectively grid for N-shaped device and p-type device stacking. In this example, gate dielectric layer and metal gate layer do not fill up grid groove 1020-1,1020-2 completely.
According to embodiment of the present disclosure, can regulate by injection the work function of metal gate layer 1026-1,1026-2, and therefore regulate the threshold voltage of device. For example, this can carry out as follows.
As shown in figure 14, can utilize photoresist 1028-1 to cover p-type device area. Photoresist 1028-1 extends preferably on the dielectric layer 1018 between p-type device area and N-shaped device area, to guarantee blocking p-type device area completely. Then, can utilize the adulterant of the first kind to carry out the first inclination injection to this side of N-shaped device (particularly, metal gate layer 1026-2). At this, so-called " inclination ", refers to respect to substrate surface to tilt (, departing from the direction vertical with substrate surface). The first direction that tilts to inject can be towards metal gate layer 1026-2 the sidewall of the first side (figure right side) in second direction (figure horizontal direction). At this, so-called " towards sidewall " refers to that injection direction is less with the angle that the normal direction of this sidewall becomes with respect to vertical injection (that is, injection direction is approximately perpendicular to substrate surface). In the example of Figure 14, the first direction that tilts to inject is in paper plane (, second direction and the plane limiting perpendicular to the direction of substrate surface). But the disclosure is not limited to this, the first direction that tilts to inject also can depart from paper plane. For N-shaped device, the first adulterant that tilts to inject can comprise one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb, and Implantation Energy can be about 0.2-30keV, and implantation dosage can be about 1E13-1E15cm-2。
Then, as shown in figure 15, can utilize the adulterant that injects same type with the first inclination, carry out the second inclination injection. The second direction that tilts to inject can be towards metal gate layer 1026-2 at the above sidewall of second side (figure left side) contrary with the first side of second direction (figure horizontal direction). In the example of Figure 15, the second direction that tilts to inject is in paper plane. But the disclosure is not limited to this, the second direction that tilts to inject also can depart from paper plane. For N-shaped device, the second adulterant that tilts to inject can comprise one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb, and Implantation Energy can be about 0.2-30keV, and implantation dosage can be about 1E13-1E15cm-2。
Preferably, the first direction that tilts to inject and the second direction that tilts to inject are roughly symmetrical about the direction perpendicular to substrate surface, and both Implantation Energies and implantation dosage roughly the same. In this case, the sidewall of the metal gate layer 1026-2 left and right sides is subject to roughly the same injection rate, thus the first kind doping (for example, doping content is C) that they have separately roughly the same (and evenly).
But the disclosure is not limited to this. Can be according to actual conditions (for example, the sidewall slope situation of the metal gate layer 1026-2 left and right sides) adjust the first inclination injection and the second direction, Implantation Energy and implantation dosage that tilts to inject separately, as long as sidewall can obtain roughly the same doping.
On the other hand, the roof of metal gate layer 1026-2 injects and has all been subject to injection in the first and second inclinations, and therefore having the relatively high first kind (for example adulterates, doping content is about 2C, this is because inject each, it is roughly the same that roof and sidewall are subject to inject situation about affecting, unless the angle of inclination of injecting is excessive, this is uncommon).
For the roof of metal gate layer 1026-2, can compensate. Particularly, as shown in figure 16, can utilize with the adulterant of the Second Type of first kind complementation and carry out the 3rd injection, the direction of this injection is approximately perpendicular to substrate surface. In addition, the 3rd inject can with the first and second injections have roughly the same Implantation Energy and roughly the same implantation dosage (and therefore cause roof place approximately-compensation rate of C; For sidewall, vertically injection impact is less). For N-shaped device, the 3rd adulterant injecting can comprise In, B, BF2, one or more in Ru, W, Mo, Al, Ga and Pt, Implantation Energy can be about 0.2-30keV, implantation dosage can be about 1E13-1E15cm-2. Like this, reduce the first kind doping that the roof (in figure, upper right is to oblique line place of lower left) of metal gate layer 1026-2 is located, make the first kind doping of the side-walls of itself and metal gate layer 1026-2 keep roughly the same (for example, 2C+ (C)=C). Thereby, realized roof and the roughly first kind doping uniformly of side-walls of metal gate layer 1026-2.
Here the roof and the sidewall that it is pointed out that metal gate layer 1026-2 described herein refer to that metal gate layer 1026-2 is positioned at roof and the sidewall on fin 1006-2. For example, and other parts that metal gate layer 1026-2 extends in grid groove 1020-2 (, being positioned at the part on side wall 1016-2) are owing to directly not affecting device threshold voltage, so refuse special concern for the doping content in these parts at this. In addition, tilting to inject the adulterant using and the adulterant using in the 3rd injection at first, second can exchange. Particularly, tilt to inject the adulterant that can use Second Type, for example In, B, BF at first, second2, one or more in Ru, W, Mo, Al, Ga and Pt, inject the adulterant that can use the first kind, for example, in P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb one or more the 3rd.
After having realized the Uniform Doped of roof to metal gate layer 1026-2 and sidewall, can remove photoresist 1028-1. Then, can similarly operate p-type device.
Particularly, as shown in figure 17, can utilize photoresist 1028-2 to cover N-shaped device area. Photoresist 1028-2 extends preferably on the dielectric layer 1018 between p-type device area and N-shaped device area, to guarantee blocking N-shaped device area completely. Then, can utilize the adulterant of Second Type to carry out the first inclination injection to this side of p-type device (particularly, metal gate layer 1026-1). The first direction that tilts to inject can be towards metal gate layer 1026-1 the sidewall of the first side (figure right side) in second direction (figure horizontal direction). In the example of Figure 17, the first direction that tilts to inject is in paper plane. But the disclosure is not limited to this, the first direction that tilts to inject also can depart from paper plane. For p-type device, the first adulterant that tilts to inject can comprise In, B, BF2, one or more in Ru, W, Mo, Al, Ga and Pt, Implantation Energy can be about 0.2-30keV, implantation dosage can be about 1E13-1E15cm-2。
Then, as shown in figure 18, can utilize the adulterant that injects same type with the first inclination, carry out the second inclination injection. The second direction that tilts to inject can be towards metal gate layer 1026-1 at the above sidewall of second side (figure left side) contrary with the first side of second direction (figure horizontal direction). In the example of Figure 18, the second direction that tilts to inject is in paper plane. But the disclosure is not limited to this, the second direction that tilts to inject also can depart from paper plane. For p-type device, the second adulterant that tilts to inject can comprise In, B, BF2, one or more in Ru, W, Mo, Al, Ga and Pt, Implantation Energy can be about 0.2-30keV, implantation dosage can be about 1E13-1E15cm-2。
Preferably, the first direction that tilts to inject and the second direction that tilts to inject are roughly symmetrical about the direction perpendicular to substrate surface, and both Implantation Energies and implantation dosage roughly the same. In this case, the sidewall of the metal gate layer 1026-1 left and right sides is subject to roughly the same injection rate, thus the Second Type doping that they have separately roughly the same (and evenly).
But the disclosure is not limited to this. Can be according to actual conditions (for example, the sidewall slope situation of the metal gate layer 1026-1 left and right sides) adjust the first inclination injection and the second direction, Implantation Energy and implantation dosage that tilts to inject separately, as long as sidewall can obtain roughly the same doping.
On the other hand, the roof of metal gate layer 1026-1 injects and has all been subject to injection in the first and second inclinations, and therefore has relatively high Second Type doping.
For the roof of metal gate layer 1026-1, can compensate. Particularly, as shown in figure 19, can utilize with the adulterant of the first kind of Second Type complementation and carry out the 3rd injection, the direction of this injection is approximately perpendicular to substrate surface. In addition, the 3rd injects and can have roughly the same Implantation Energy and roughly the same implantation dosage with the first and second injections. For p-type device, the 3rd adulterant injecting can comprise one or more of P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb, and Implantation Energy can be about 0.2-30keV, and implantation dosage can be about 1E13-1E15cm-2. Like this, reduce the Second Type doping that the roof (in figure, upper left is to oblique line place of lower right) of metal gate layer 1026-1 is located, made it roughly the same with the Second Type doping maintenance at the roof place of metal gate layer 1026-1. Thereby, realized roof and the roughly Second Type doping uniformly of side-walls of metal gate layer 1026-1.
Like this, realized the even Second Type doping of roof to metal gate layer 1026-1 and sidewall. Then, can remove photoresist 1028-2.
Similarly, tilting to inject the adulterant using and the adulterant using in the 3rd injection at first, second can exchange. Particularly, tilt to inject the adulterant that can use the first kind at first, second, for example, in P, As, Sb, La, Er, Dy, Gd, Sc, Yb and Tb one or more, inject the adulterant that can use Second Type, for example In, B, BF the 3rd2, one or more in Ru, W, Mo, Al, Ga and Pt.
Here it is pointed out that under the complementary process condition of this example, N-shaped device and p-type device are processed respectively. But the disclosure is not limited to this. For example, in incomplementarity technique, can not carry out such covering. In addition, in this example, first cover p-type device area, N-shaped device area is processed. But the disclosure is not limited to this. The order that N-shaped device area and p-type device area are processed can exchange. And for same device, the order of injecting for each time also can change.
After as mentioned above the work function of metal gate layer being carried out to even regulation, can complete the follow-up making of device. For example, as shown in Figure 20,20A, 20B and 20C, can in grid groove 1020-1,1020-2, further form gate electrode layer 1030-1,1030-2. For example, gate electrode layer can comprise W or TiAl, and its thickness is enough to fill up grid groove 1020-1,1020-2. Then, can carry out planarization as CMP, be positioned at the part outside grid groove to remove gate dielectric layer, metal gate layer and gate electrode layer. This planarization can dielectric layer 1018 be terminal. Next, can also further deposit interlevel dielectric layer and form therein contact site (not shown).
Like this, just obtain the semiconductor devices according to this embodiment. As shown in Figure 20,20A, 20B and 20C, semiconductor devices is included in the fin 1006-1/1006-2 extending along first direction (vertical direction in Figure 20) forming on substrate 1002 and the grid that extend along second direction (horizontal direction in Figure 20) that form on substrate 1002 is stacking, the stacking gate dielectric layer 1024-1/1024-2 and the metal gate layer 1026-1/1026-2 that stack gradually of comprising of grid. The sidewall of the relative both sides (left and right sides in Figure 20 A) with respect to metal gate layer in second direction, the adulterant of the adulterant that the roof of metal gate layer comprises the higher first kind and Second Type higher and first kind complementation, thus metal gate layer presents roughly first kind doping uniformly on the whole. In the above description, combine the situation of N-shaped device and p-type device, utilize "/" that they are separate.
In addition, in above example, be described for replacement gate process. But the disclosure is not limited to this. For example, the disclosure is equally applicable to first grid technique.
In above description, be not described in detail for the ins and outs such as composition, etching of each layer. But it will be appreciated by those skilled in the art that and can, by various technological means, form layer, the region etc. of required form. In addition, in order to form same structure, those skilled in the art can also design and the not identical method of method described above. In addition, although describing respectively above each embodiment, this and the measure in each embodiment that do not mean that can not advantageously be combined with.
Above embodiment of the present disclosure is described. But these embodiment are only used to the object of explanation, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is limited by claims and equivalent thereof. Do not depart from the scope of the present disclosure, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should fall within the scope of the present disclosure.
Claims (10)
1. a method of manufacturing semiconductor devices, comprising:
On substrate, form the fin extending along first direction;
On substrate, form along the grid of the second direction extension intersecting with first direction stacking, wherein gridThe stacking gate dielectric layer and the metal gate layer that stack gradually of comprising;
Utilize the adulterant of the first kind to carry out the first inclination injection, wherein the first side that tilts to injectTo the sidewall in the first side at fin towards metal gate layer;
Utilize the adulterant of the first kind to carry out the second inclination injection, wherein the second side that tilts to injectTo the sidewall in second side contrary with the first side at fin towards metal gate layer;
Utilize with the adulterant of the Second Type of first kind complementation and carry out the 3rd injection, wherein the 3rdThe direction of injecting is approximately perpendicular to the surface of substrate.
2. method according to claim 1, wherein, the first direction and second that tilts to injectThe direction that tilts to inject is roughly symmetrical about the direction perpendicular to substrate surface, and both injection energyAmount and implantation dosage are roughly the same.
3. method according to claim 1, wherein, the 3rd injects and the first and second injectionsThere is roughly the same Implantation Energy and roughly the same implantation dosage.
4. method according to claim 1, wherein,
The adulterant of the first kind comprise P, As, Sb, La, Er, Dy, Gd, Sc, Yb andOne or more in Tb, the adulterant of Second Type comprises In, B, BF2、Ru、W、Mo、One or more in Al, Ga and Pt; Or
First kind adulterant comprises In, B, BF2, in Ru, W, Mo, Al, Ga and PtOne or more, the adulterant of Second Type comprise P, As, Sb, La, Er, Dy, Gd,One or more in Sc, Yb and Tb.
5. method according to claim 1, wherein, the first inclination is injected, the second inclination noteEntering with the 3rd Implantation Energy injecting is separately about 0.2-30keV, and implantation dosage is about 1E13-1E15cm-2。
6. method according to claim 1, wherein, forms that grid are stacking comprises:
On substrate, form the sacrificial gate of extending along second direction stacking, sacrificial gate is stacking to be comprised successivelyStacking sacrificial gate dielectric layer and sacrificial gate conductor layer;
On the stacking sidewall of sacrificial gate, form grid side wall;
On substrate, form dielectric layer, and carry out planarization, stacking to expose sacrificial gate;
Selective removal sacrificial gate is stacking, thereby forms grid groove in grid side wall inner side;
In grid groove, form gate dielectric layer and metal gate layer.
7. method according to claim 6, also comprises:
In the grid groove that is formed with gate dielectric layer and metal gate layer, further form gate electrode layer.
8. a semiconductor devices, comprising:
The fin extending along first direction forming on substrate;
The grid that extend along the second direction of intersecting with first direction that form on substrate are stacking, whereinThe stacking gate dielectric layer and the metal gate layer that stack gradually of comprising of grid,
Wherein, the sidewall with respect to metal gate layer on the relative both sides of fin, metal gate layer is at finThe adulterant that roof on end face comprises the higher first kind and higher and first kind complementationThe adulterant of Second Type, mix thereby metal gate layer presents roughly the first kind uniformly on the wholeAssorted.
9. semiconductor devices according to claim 8, wherein,
First kind adulterant comprises P, As, Sb, La, Er, Dy, Gd, Sc, Yb and TbIn one or more, the adulterant of Second Type comprises In, B, BF2、Ru、W、Mo、One or more in Al, Ga and Pt; Or
First kind adulterant comprises In, B, BF2, in Ru, W, Mo, Al, Ga and PtOne or more, the adulterant of Second Type comprise P, As, Sb, La, Er, Dy, Gd,One or more in Sc, Yb and Tb.
10. semiconductor devices according to claim 8, wherein, metal gate layer comprises TiN.
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