CN105609078B - Gate driving circuit and liquid crystal display device - Google Patents

Gate driving circuit and liquid crystal display device Download PDF

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Publication number
CN105609078B
CN105609078B CN201610069967.4A CN201610069967A CN105609078B CN 105609078 B CN105609078 B CN 105609078B CN 201610069967 A CN201610069967 A CN 201610069967A CN 105609078 B CN105609078 B CN 105609078B
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CN
China
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signal
end
transistor
gated sweep
electrically connected
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CN201610069967.4A
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Chinese (zh)
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CN105609078A (en
Inventor
于子阳
黎倩
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昆山龙腾光电有限公司
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Priority to CN201610069967.4A priority Critical patent/CN105609078B/en
Publication of CN105609078A publication Critical patent/CN105609078A/en
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Publication of CN105609078B publication Critical patent/CN105609078B/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes

Abstract

The embodiment of the invention discloses a kind of gate driving circuit and liquid crystal display device, the gate driving circuit includes:Multiple gate drive unit circuits, clock cable and line trigger signal, gate drive unit circuit include:Precharge unit, stabilization signal generation unit, drop-down stable unit, output unit and synchronous trigger element, when video card sends new frame picture to the T con of liquid crystal display device, vertical synchronizing signal can be carried at the top of new frame picture, T con are supplied to synchronous trigger element after generating trigger signal according to vertical synchronizing signal, when synchronous trigger element receives trigger signal, can force the control node of current line to end row and gated sweep signal being pulled down to low level.Gate driving circuit and liquid crystal display device of the present invention can eliminate picture tear phenomenon, lift display quality.

Description

Gate driving circuit and liquid crystal display device

Technical field

The present invention relates to display technology field, more particularly to a kind of gate driving circuit and liquid crystal display device.

Background technology

Liquid crystal display device (Liquid Crystal Display, LCD) have image quality is good, small volume, in light weight, low drive The advantages of dynamic voltage, low-power consumption, relatively low radiationless and manufacturing cost, occupied an leading position at present in flat display field.Liquid Crystal device is especially suitable for applying in desktop computer, palmtop computer, personal digital assistant (Personal Digital Assistant, PDA), portable phone, in a variety of office automations and audio-visual equipment such as TV box.

Figure 1A is the schematic diagram of existing liquid crystal display device display picture, and as shown in Figure 1A, video card is every time by frame numbers According in 2 frame write-in frame buffer 4, there is frame buffer 4 enough spaces only to store a frame, and then, frame delays Bottom in the content of storage 4 from the top of picture to picture is sent to the SECO IC of display device 6 by horizontal line 8 (Timing controller, T-con) is shown, video card is again concurrently the picture data corresponding to next frame from picture Write to picture bottom by horizontal line 7 in frame buffer 4 at top.

The SECO IC of liquid crystal display device refreshing frequency is set as fixed value, such as 60H mostly at presentZ, and When running large-scale 3D programs, refreshing frequency of the video card when handling dynamic menu may be greater than or less than this fixed value 60HZ, More than 60HZWhen (time interval between the first frame and the second frame picture is less than 1/60s), the SECO IC of display device The first frame picture can have first been shown, then has completed the display of the second frame picture, frequency 60HZ.And when video card is in processing dynamic menu When refreshing frequency be less than 60HZWhen (time interval between the first frame and the second frame picture is more than 1/60s), display device SECO IC shown the first frame picture after, can repeat display the first frame picture, until video card writes the second frame picture Enter in frame buffer;Now the display time of the first frame picture more than a frame time, if aobvious in the first frame picture second When showing, the second frame picture is write frame buffer by video card, and the SECO IC of display device can force to show the second frame picture, and Now second of display of the first frame picture does not terminate also, and display picture top half also maintains the first frame picture, and lower half Part is but forced to switch to the second frame picture, causes the separation up and down of display picture, this phenomenon is exactly to tear phenomenon.Figure 1B It is that alphabetical A is shown with the first picture, and the second picture to continue is shown as shown in Figure 1B for the schematic diagram of a tear picture Exemplified by letter b, the picture to be shown is temporarily stored in frame buffer, however, the SECO IC of display device frame updating frequency Rate and the frame updating speed of frame buffer are different, if the first picture is shown for the second time, video card writes the second picture Frame buffer, the display of the first picture is caused not yet to be completed, but frame buffer has been updated to the data of the second picture, display device SECO IC can force show the second picture.Consequently, it is possible to will have the tear phenomenon shown in Figure 1B, during actual displayed, The first half 11 of picture shows a part (alphabetical A) for the first picture, but lower half 12 shows a part (letter of the second picture B)。

Tearing the essential reason of phenomenon is:SECO IC of the video card to display device sends picture when showing dynamic menu In data procedures, the picture of write-in of the video card to frame buffer is asynchronous with the SECO IC display pictures of display device to be caused , and with the fast development of desktop graphics processor and mobile graphics processor (video card), the disposal ability of video card is increasingly By force, the demand of the large-scale 3D programs of user's operation can be stronger, therefore picture tear phenomenon is urgently to be resolved hurrily.

In current image display arts, in order to eliminate the tear phenomenon of picture, the mode taken is:Open video card Vertical synchronization function, i.e., by video card refreshing frequency force be limited to (such as 60H identical with display deviceZ).And open video card Vertical synchronization function, the problems such as the performance of video card can be substantially reduced, such as occur to fall frame, interim card, have impact on display effect.

The content of the invention

The present invention provides a kind of gate driving circuit and liquid crystal display device, can eliminate picture tear phenomenon, and lifting is aobvious Show quality.

The technical scheme is as follows:

The invention provides a kind of gate driving circuit, and it includes:Including multiple gate drive unit circuits, clock signal Line and line trigger signal, the gate drive unit circuit include:Precharge unit, stabilization signal generation unit, drop-down are stable Unit, output unit and synchronous trigger element, precharge unit unit stable with the drop-down, the output unit, The synchronous trigger element is electrical connected, the stable unit of drop-down also with the stabilization signal generation unit, it is described synchronously touch Bill member is electrical connected, wherein;The precharge unit, including received for receiving the first the first transmission signal for transmitting signal Hold (111), its output end (113) is connected to control node (Q), transmits signal for receiving first, and pass through its output end (113) line precharge is entered to control node (Q);The output unit, include the gated sweep signal of output gated sweep signal Output end (133), receive the clock signal receiving terminal (141) of clock signal and be electrically connected to control node (Q) control Hold (132), the output unit responds the state of the control node (Q), when the control node (Q) is high level, institute The high level for stating clock signal applies to the output unit, makes gated sweep signal output part (133) the output high level, When the control node (Q) is low level, the gated sweep signal output part (133) maintains low level;The stabilization Signal generation unit, including be electrically connected to first node (QB) control terminal (143), for receive direct current or AC signal with Generation stabilization signal is supplied to the first node (QB), stablizes the control node (Q) with drop-down and believes with the gated sweep Number;The stable unit of drop-down, including the control node (Q) control terminal (142) is electrically connected to, it is supplied to for utilizing The control node (Q) and the gated sweep signal are maintained low level by the stabilization signal of the first node (QB);Institute Synchronous trigger element is stated, is connected with the control node (Q), is drawn when video card sends a new frame to the T-con of liquid crystal display device During face, vertical synchronizing signal can be carried at the top of new frame picture, the T-con is generated according to the vertical synchronizing signal and touched The synchronous trigger element is supplied to after signalling, when the synchronous trigger element receives the trigger signal, can be forced The control node (Q) of current line to end row and the gated sweep signal are pulled down to low level.

In one embodiment of the invention, the output unit includes the first transistor (T1) and bootstrap capacitor (C1), The grid of the first transistor (T1) is electrically connected to the control node (Q), also electrical by the bootstrap capacitor (C1) The gated sweep signal output part (133) is connected to, the first end of the first transistor (T1) receives the clock signal, Second end of the first transistor (T1) is electrically connected to the gated sweep signal output part (133), described for exporting Gated sweep signal.

In one embodiment of the invention, the synchronous trigger element includes second transistor (T2), third transistor (T3), the grid of the second transistor (T2) receives the trigger signal, and the first end of the second transistor (T2) is electrical First voltage output end (VGL) is connected, the second end electric connection gated sweep signal of the second transistor (T2) is defeated Go out end (133), the grid of the third transistor (T3) receives the trigger signal, the first end of the third transistor (T3) The first voltage output end (VGL) is electrically connected with, the second end of the third transistor (T3) is electrically connected with the control section Point (Q).

In one embodiment of the invention, the synchronous trigger element includes the 4th transistor (T4), and the described 4th is brilliant The grid and first end of body pipe (T4) receive the trigger signal, and the second end of the 4th transistor (T4) is electrically connected to institute State first node (QB).

In one embodiment of the invention, the synchronous trigger element includes the 5th transistor (T5), the 6th transistor (T6), the 7th transistor (T7), grid and first end the reception trigger signal of the 5th transistor (T5), the described 5th Second end of transistor (T5) is electrically connected to the first node (QB);Described in the grid of 6th transistor (T6) receives Trigger signal, the first end of the 6th transistor (T6) are electrically connected with first voltage output end (VGL), the 6th transistor (T6) the second end is electrically connected with the gated sweep signal output part (133);The grid of 7th transistor (T7) receives The trigger signal, the first end of the 7th transistor (T7) are electrically connected with the first voltage output end (VGL), and described the Second end of seven transistors (T7) is electrically connected with the control node (Q).

In one embodiment of the invention, the first voltage output end (VGL) connects low level voltage source supplies Device.

In one embodiment of the invention, signal output is transmitted in the afterbody connection end of the gate driving circuit End, signal, the trigger signal and the end transmission signal output part output of the gate driving circuit are transmitted to receive end End transmit signal share a transmission lines.

The invention provides a kind of liquid crystal display device, and it includes display panel, and the panel is included by multiple pixel structures Into two-dimensional array, and a plurality of gate line for the first direction being connected with each pel array and second direction is a plurality of Data wire;Data drive circuit, for providing picture signal to the data wire;Described gate driving circuit, for institute State gate line and gated sweep signal is provided.

The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is:

When sending new frame picture to T-con by video card, vertical synchronization letter can be carried at the top of new frame picture Number, T-con is supplied to synchronous trigger element after generating trigger signal according to vertical synchronizing signal, when synchronous trigger element receives During trigger signal, the control node and gated sweep signal output part of current line to end row can be pulled down to low level, when Preceding scanning is expert at will be maintained at low level state to follow-up all gate lines, and wrong data can not write, and avoid tear Generation, improve display quality.

Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention, And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can Become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, describe in detail as follows.

Brief description of the drawings

Figure 1A is the schematic diagram of existing liquid crystal display device display picture;

Figure 1B is the schematic diagram of a tear picture;

Fig. 2 is the circuit diagram for the gate drive unit circuit that first embodiment of the invention provides;

Fig. 3 A are the gate driving circuit cascade block diagrams that gate drive unit circuit is formed in first embodiment of the invention;

Fig. 3 B are the timing diagrams of Fig. 3 A gate driving circuit;

Fig. 4 is the circuit diagram for the gate drive unit circuit that second embodiment of the invention provides;

Fig. 5 is the circuit diagram for the gate drive unit circuit that third embodiment of the invention provides;

Fig. 6 is the circuit diagram for the gate drive unit circuit that fourth embodiment of the invention provides;

Fig. 7 is trigger signal, the initial signal of initial signal output end output, the end of end transmission signal output part output Transmit the timing diagram of signal in end;

Fig. 8 is trigger signal, the initial signal of initial signal output end output, the end of end transmission signal output part output Transmit another timing diagram of signal in end.

Embodiment

The present invention is described in detail below by specific embodiment and with reference to accompanying drawing.

Liquid crystal display device includes LCDs, drive circuit (SECO IC, gate driving circuit, data-driven Circuit), backlight etc..When liquid crystal display device works, by gate driving circuit to gate line a line on LCDs Scan by line, often scan a line, just all open all pixels point of this line, data drive circuit is just to the pixel of the row Point write-in data voltage, to provide picture signal, pixel voltage is charged to the picture and show required voltage, the liquid of pixel Brilliant molecule deflects under electric field or so, the light of backlight is formed image through the pixel.Because liquid crystal display fills Put using the mode of progressive scan when updating picture, therefore drawn by the gate driving circuit control of the present invention in a new frame When face (such as second frame picture) writes T-con buffer, gate line that positive closing Current Scan is expert to screen bottom All gate lines in portion, can both prevent the write-in of wrong data, can prevent from tearing the generation of phenomenon again, lift display quality.

First embodiment

Fig. 2 is the circuit diagram for the gate drive unit circuit that first embodiment of the invention provides.Referring to Fig. 2, grid drives Moving cell circuit 5 includes:Precharge unit 10, stabilization signal generation unit 20, the stable unit 30 of drop-down, output unit 40 and Synchronous trigger element 50.The unit 30 stable with drop-down of precharge unit 10, output unit 40,50 electrical phase of synchronous trigger element Even, stable unit 30 is pulled down also to be electrical connected with stabilization signal generation unit 20, synchronous trigger element 50.

In embodiments of the present invention, assume that current Gate driver element circuit is n-th grade of gate drive unit circuit, VG [n], VC [n] represent the gated sweep signal and transmission signal of n-th grade of gate drive unit circuit output, VG [n+1], VC respectively [n+1] represents the grid of next stage ((n+1)th grade) gate drive unit circuit output of this grade of gate drive unit circuit respectively Scanning signal and transmission signal, VG [n-1], VC [n-1] represent the upper level ((n-1)th of this grade of gate drive unit circuit respectively Level) gate drive unit circuit output gated sweep signal and transmit signal.

Precharge unit 10, including for receiving the first the first transmission signal receiving end 111 for transmitting signal VG [n-1], Its output end 113 is connected to control node Q, and signal VG [n-1] is transmitted for receiving first, and by its output end 113 to control Node Q processed enters line precharge.

Output unit 40, include output gated sweep signal G [n] gated sweep signal output part 133, receive clock letter Number clock signal receiving terminal 141 and be electrically connected to control node Q control terminal 132.The response control section of output unit 40 Point Q state, when control node Q is high level, the high level of clock signal clk applies to output unit 40, sweeps grid Retouch signal output part 133 and export high level to gate line, and to the precharge of next stage ((n+1)th grade) gate drive unit circuit Unit transmission, when control node Q is low level, gated sweep signal output part 133 maintains low level.Output module 40 Gated sweep signal output part 133 is used to export gated sweep signal G [n], wherein, per the coupling of one-level gate drive unit circuit To a corresponding gate line, in this example, gated sweep signal G [n] quilt of the gate drive unit circuit 5 output It is applied to corresponding gate line.

Stabilization signal generation unit 20, including it is electrically connected to first node QB control terminal 143.For receive direct current or AC signal is supplied to first node QB to generate stabilization signal, to pull down stability contorting node Q and gated sweep signal G [n], And dragged down when gated sweep signal output part 133 is high level by control node Q and gated sweep signal G [n], do not influence grid The normal output of pole driver element circuit.

The stable unit 30 of drop-down, including control node Q control terminal 142 is electrically connected to, it is supplied to first for utilizing Control node Q and gated sweep signal G [n] are maintained low level by node QB stabilization signal.

Synchronous trigger element 50, is connected with control node Q, when video card sends a new frame to the T-con of liquid crystal display device During picture, vertical synchronizing signal V-sync, T-con can be carried at the top of new frame picture according to vertical synchronizing signal V-sync Generation trigger signal after be supplied to synchronous trigger element 50, when synchronous trigger element 50 receives trigger signal, can force by Current line to end row (assuming that scan mode is scan mode from top to bottom) control node Q and gated sweep signal G [n] Low level is pulled down to, i.e., by the gated sweep signal output part 133 of all gate drive unit circuits of current line to end row Pressure is set to low level (such as 0), so it is avoided that follow-up wrong data is written in display device, current line to end row Picture below corresponding screen still maintains the picture of previous frame, it is therefore prevented that tears the generation of phenomenon.What current line referred both to It is that Current Scan is expert at, end row refers to screen bottommost a line.

Specifically, in the first embodiment, output unit 40 includes transistor T1 (the first transistor) and bootstrap capacitor C1.

Transistor T1 grid is electrically connected to control node Q, is also electrically connected to gated sweep by bootstrap capacitor C1 Signal output part 133, transistor T1 first end receive clock signal clk, and transistor T1 the second end is electrically connected to grid Scanning signal output end 133, for exporting gated sweep signal G [n].Bootstrap capacitor C1 is used for the current potential for storing control node Q, When control node Q is high level, the output of gated sweep signal output part 133 of this grade of gate drive unit circuit is high electricity Flat, transistor T1 conductings, the high level of clock signal clk applies to transistor T1 first end, and to next stage ((n+1)th grade) The precharge unit transmission of gate drive unit circuit;When control node Q is low level, the gate drive unit circuit of this grade Gated sweep signal output part 133 be in low level, transistor T1 is closed, and corresponding gate line maintains low level all the time.

The first end of above-mentioned transistor can be source electrode or the drain electrode of transistor, correspondingly, the second end of above-mentioned transistor Can be drain electrode or the source electrode of transistor.Wherein, precharge unit 10, stabilization signal generation unit 20, the stable unit 30 of drop-down The identical structure that can have with the circuit diagram of existing gate drive unit circuit, will not be repeated here.

Fig. 3 A are the gate driving circuit cascade block diagrams that gate drive unit circuit is formed in first embodiment of the invention.This Gate driving circuit includes the gate drive unit circuit as described in Figure 2 of N number of cascade, and the N is the integer more than 1, grid Drive circuit also includes clock cable VA and line trigger signal V-sync trigger signal.

The first clock signal terminal 51CLK1 connections of first order gate drive unit circuit 501 in this gate driving circuit Clock cable VA, to receive clock signal clk.The trigger signal end 51TR connections of first order gate drive unit circuit 501 Line trigger signal V-sync trigger signal, to receive trigger signal.The of first order gate drive unit circuit 501 One transmits signal receiving end 51G [n-1] connection initial signal output ends, to receive initial signal STV.First order raster data model list First circuit 501 may also include voltage receiving terminal, to connect low level voltage output end VSS (not shown)s.First order grid Gated sweep signal output part 51G [n] the output gated sweep signal G [1] of driver element circuit 501.First order raster data model The gated sweep signal output part 51G [n] of element circuit 501 is also connected with the precharge of second level gate drive unit circuit 502 Unit.

First clock signal terminal 52CLK1 connection clock cable VA of second level gate drive unit circuit 502, to connect Receive clock signal clk.The trigger signal end 52TR connection line trigger signals V-sync of second level gate drive unit circuit 502 Trigger signal, to receive trigger signal.The first of second level gate drive unit circuit 502 transmits signal receiving end The gated sweep signal output part 51G [n] of 52G [n-1] connection first order gate drive unit circuit 501.Second level grid drives Moving cell circuit 502 may also include voltage receiving terminal, to connect low level voltage output end VSS (not shown)s.The second level Gated sweep signal output part 52G [n] the output gated sweep signal G [2] of gate drive unit circuit 502.Second level grid The gated sweep signal output part 52G [n] of driver element circuit 502 is also connected with the pre- of third level gate drive unit circuit 503 Charhing unit.

First clock signal terminal 53CLK1 connection clock cable VA of third level gate drive unit circuit 503, to connect Receive clock signal clk.The trigger signal end 53TR connection line trigger signals V-sync of third level gate drive unit circuit 503 Trigger signal, to receive trigger signal.The first of third level gate drive unit circuit 503 transmits signal receiving end The gated sweep signal output part 52G [n] of 53G [n-1] connection second level gate drive unit circuits 502.Third level grid drives Moving cell circuit 503 may also include voltage receiving terminal, to connect low level voltage output end VSS (not shown)s.The third level Gated sweep signal output part 53G [n] the output gated sweep signal G [3] of gate drive unit circuit 503.Third level grid The gated sweep signal output part 53G [n] of driver element circuit 503 is also connected with the pre- of fourth stage gate drive unit circuit 504 Charhing unit.

First clock signal terminal 54CLK1 connection clock cable VA of fourth stage gate drive unit circuit 504, to connect Receive clock signal clk.The trigger signal end 54TR connection line trigger signals V-sync of fourth stage gate drive unit circuit 504 Trigger signal, to receive trigger signal.The first of fourth stage gate drive unit circuit 504 transmits signal receiving end The gated sweep signal output part 53G [n] of 54G [n-1] connection third level gate drive unit circuit 503.Fourth stage grid drives Moving cell circuit 504 may also include voltage receiving terminal, to connect low level voltage output end VSS (not shown)s.The fourth stage Gated sweep signal output part 54G [n] the output gated sweep signal G [4] of gate drive unit circuit 504.Fourth stage grid The gated sweep signal output part 54G [n] of driver element circuit 504 is also connected with the pre- of level V gate drive unit circuit 505 Charhing unit.

First clock signal terminal 55CLK1 connection clock cable VA of level V gate drive unit circuit 505, to connect Receive clock signal clk.The trigger signal end 55TR connection line trigger signals V-sync of level V gate drive unit circuit 505 Trigger signal, to receive trigger signal.The first of level V gate drive unit circuit 505 transmits signal receiving end The gated sweep signal output part 54G [n] of 55G [n-1] connection fourth stages gate drive unit circuit 504.Level V grid drives Moving cell circuit 505 may also include voltage receiving terminal, to connect low level voltage output end VSS (not shown)s.Level V Gated sweep signal output part 55G [n] the output gated sweep signal G [5] of gate drive unit circuit 505.Level V grid The gated sweep signal output part 55G [n] of driver element circuit 505 is also connected with the 6th grade of gate drive unit circuit (in figure not Show) precharge unit.

In above-mentioned gate driving circuit, the annexation of the description first order to level V gate drive unit circuit is only For example, subsequent gate driver element circuit can be with the circulating repetition first order to level V gate drive unit circuit connection Relation, it will not be repeated here.And the afterbody gate drive unit circuit of gate driving circuit can also include the first letter Number receiving terminal STV-D1, it is electrically connected with end and transmits signal output part, and signal STV-D is transmitted to receive end, wherein, end Transmit signal output part and export the end transmission signal STV-D.

Fig. 3 B are the timing diagrams of Fig. 3 A gate drive unit circuit.The timing diagram is by SPICE (Simulation Program with integrated circuit emphasis, simulation of integrated circuit program) simulate what is obtained.In Fig. 3 B Curve 1STV represents the initial signal STV of initial signal output end output voltage change curve, the curve 1V-sync in Fig. 3 B The voltage change curve of trigger signal is represented, curve Q1, Q2, Q3, Q4, Qn in Fig. 3 B represent the first order, the second level, the respectively Three-level, the fourth stage, n-th grade of gate drive unit circuit control node Q voltage change curve, curve 1G1 in Fig. 3 B, 1G2,1G3,1G4,1Gn represent the first order, the second level, the third level, the fourth stage, n-th grade of gate drive unit circuit output respectively Gated sweep signal voltage change curve.It is can be seen that from Fig. 3 B timing diagram when scanning is to the third line, i.e., the 3rd During level gate drive unit circuit scanning, when gate driving circuit receives the trigger signal of high level, current line the (the i.e. the 3rd Low level can OK) be pulled down to the control node Q and gated sweep signal output part VG [n] of end row (i.e. line n), when Proceed to follow-up all gate lines and will be maintained at low level state, wrong data can not write, and avoid the generation of tear.This The new gate driving circuit proposed is invented, coordinates the vertical synchronizing signal V-sync, T-con of video card can generate a triggering Signal, utilize the extra increased synchronous trigger element 50 of gate driving circuit, it is possible to achieve all grid of current line to end row The positive closing of polar curve, avoid the write-in of error signal, it is therefore prevented that tear the generation of phenomenon.And present invention could apply to The 60H of main flow at presentZIn more low-frequency display device, it is not necessary to increase extra cost.

Second embodiment

Fig. 4 is the circuit diagram for the gate drive unit circuit that second embodiment of the invention provides.The present embodiment and Fig. 2 are not It is with part:Synchronous trigger element 50 includes transistor T2 (second transistor), T3 (third transistor).Remainder and figure Gate drive unit circuit shown in 2 is identical, be will not be repeated here.

Wherein, transistor T2 (second transistor) grid receives trigger signal Trigger signal, transistor T2 (the Two-transistor) first end be electrically connected with first voltage output end VGL, transistor T2 (second transistor) the second end electrically connect Connect the gated sweep signal output part 133 for exporting gated sweep signal VG [n].Transistor T3 grid receives trigger signal The second end that Trigger signal, transistor T3 first end are electrically connected with first voltage output end VGL, transistor T3 is electrical Connect control node Q.

In the present embodiment, first voltage output end (VGL) connects low level voltage source supplies device, works as trigger signal When Trigger signal are changed into high level, the control node Q and gated sweep signal output part 133 of current line to end row are equal Low level can be pulled down to, current line to follow-up all gate lines will be maintained at low level state, and wrong data can not write, Avoid the generation of tear.

3rd embodiment

Fig. 5 is the circuit diagram for the gate drive unit circuit that third embodiment of the invention provides.The present embodiment and Fig. 2 are not It is with part:Synchronous trigger element 50 includes transistor T4 (the 4th transistor).Remainder and the raster data model shown in Fig. 2 Element circuit is identical, be will not be repeated here.

Wherein, transistor T4 grid and first end receive trigger signal Trigger signal, and the second of transistor T4 End is electrically connected to first node QB.

In the present embodiment, when trigger signal Trigger signal are changed into high level, first node QB is high level, under Stable unit 30 is drawn to turn on so as to pull down control node Q and gated sweep signal output part 133, so that current line is to end row Control node Q and gated sweep signal output part 133 can be pulled down to low level, and current line to follow-up all gate lines will Low level state is maintained, wrong data can not write, and avoid the generation of tear.

Fourth embodiment

Fig. 6 is the circuit diagram for the gate drive unit circuit that fourth embodiment of the invention provides.The present embodiment and Fig. 2 are not It is with part:Synchronous trigger element 50 includes transistor T5 (the 5th transistor), T6 (the 6th transistor), T7 (the 7th crystal Pipe).Remainder is identical with the gate drive unit circuit shown in Fig. 2, be will not be repeated here.

Wherein, transistor T5 grid and first end receive trigger signal Trigger signal, and the second of transistor T5 End is electrically connected to first node QB.Transistor T6 grid receives the of trigger signal Trigger signal, transistor T6 The second end that one end is electrically connected with first voltage output end VGL, transistor T6 is electrically connected with for exporting gated sweep signal VG The gated sweep signal output part 133 of [n].Transistor T7 grid receives trigger signal Trigger signal, transistor T7 First end be electrically connected with first voltage output end VGL, transistor T7 the second end and be electrically connected with control node Q.

In the present embodiment, first voltage output end (VGL) connects low level voltage source supplies device, works as trigger signal When Trigger signal are changed into high level, the control node Q and gated sweep signal output part 133 of current line to end row are equal Low level can be pulled down to, current line to follow-up all gate lines will be maintained at low level state, and wrong data can not write, Avoid the generation of tear.

It should be noted that in above-mentioned first to fourth embodiment, trigger signal rises with the output of initial signal output end The end transmission signal that signal output part output is transmitted in beginning signal STV and end can be completely independent, and trigger signal is mono- by T-con Solely provide.Fig. 7 is trigger signal, the initial signal STV of initial signal output end output, end transmission signal output part output The timing diagram of signal is transmitted in end, wherein, curve STV-up, V-sync trigger, STV-down in Fig. 7 have been represented respectively The initial signal STV of beginning signal output part output, trigger signal, end transmit the end that signal output part exports and transmit signal Voltage change curve, from figure 7 it can be seen that the initial signal STV of trigger signal, initial signal output end output, end are transmitted It is separate that signal is transmitted in the end of signal output part output.

5th embodiment

The present embodiment and the difference of above-mentioned first to fourth embodiment are:Trigger signal and gate driving circuit The shared transmission lines of signal are transmitted in the end that signal output part output is transmitted in end, i.e. it is defeated to transmit signal for trigger signal and end The end transmission signal for going out end output is combined, and had not both interfered with trigger signal function so and end transmission signal output part is defeated The normal realization of the function of signal is transmitted in the end gone out, can save a transmission lines again.Fig. 8 is trigger signal, initial signal The initial signal STV of output end output, end transmit another timing diagram of the end transmission signal of signal output part output, its In, curve 1STV-up, 1V-sync trigger, 1STV-down in Fig. 8 represent rising for initial signal output end output respectively The voltage change curve that signal is transmitted in the end that signal output part exports is transmitted in beginning signal STV, trigger signal, end, can from Fig. 8 To find out, the end shared transmission lines of transmission signal that trigger signal, end transmit signal output part output are exported.

Also, 3 kinds of embodiments (second to fourth embodiment) of above-mentioned synchronous trigger element and two kinds of realities of trigger signal Applying example, (i.e. signal output is transmitted in the 5th embodiment, the initial signal STV of trigger signal and the output of initial signal output end and end Transmit the completely self-contained embodiment of signal in the end of end output) present invention can be achieved with independent assortment, 6 kinds of situations.

Sixth embodiment

According to above example, sixth embodiment of the invention also discloses a kind of display device, including:Panel, panel bag Include the two-dimensional array being made up of multiple pixels, and a plurality of data lines for the first direction being connected with each pel array and The a plurality of gate line of second direction;Data drive circuit, for providing picture signal to the data wire;Also include embodiment one Gate driving circuit into five, for providing gated sweep signal to the gate line.Pel array is formed in transparent substrates On, and including a plurality of gate line, data wire and multiple switch transistor.Switching transistor be coupled respectively to each gate line and Each data line.Data drive circuit and data wire coupling, and provide data voltage to data wire.Gate driving circuit and grid Polar curve couples, and driving switch transistor.

In summary, the gate driving circuit and liquid crystal display device of the embodiment of the present invention, when by video card to T-con send out When sending new frame picture, it can be believed in the top of new frame picture carrying vertical synchronizing signal V-sync, T-con according to vertical synchronization Synchronous trigger element 50 is supplied to after number V-sync generation trigger signal, when synchronous trigger element 50 receives trigger signal, The control node Q and gated sweep signal output part 133 of current line to end row can be pulled down to low level, Current Scan institute It is expert at and will be maintained at low level state to follow-up all gate lines, wrong data can not writes, and avoid the generation of tear, carry Display quality is risen.And present invention could apply to the 60H of current main flowZIn more low-frequency display device, it is not necessary to Increase extra cost.

The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention, though So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification For the equivalent embodiment of equivalent variations, as long as being the technical spirit pair according to the present invention without departing from technical solution of the present invention content Any simple modification, equivalent change and modification that above example is made, in the range of still falling within technical solution of the present invention.

Claims (8)

1. a kind of gate driving circuit, it is characterised in that it includes multiple gate drive unit circuits, clock cable and triggering Signal wire, the gate drive unit circuit include:Precharge unit, stabilization signal generation unit, the stable unit of drop-down, output Unit and synchronous trigger element, precharge unit unit stable with the drop-down, the output unit, it is described synchronously touch Bill member is electrical connected, and the stable unit of drop-down is also electrical with the stabilization signal generation unit, the synchronous trigger element It is connected, wherein;
The precharge unit, including for receiving the first the first transmission signal receiving end (111) for transmitting signal and connection To control node (Q) output end (113), the precharge unit is used to receive the first transmission signal, and by described Output end (113) enters line precharge to the control node (Q);
The output unit, include the gated sweep signal output part (133) of output gated sweep signal, receive clock signal Clock signal receiving terminal (141) and the control terminal (132) for being electrically connected to control node (Q), the output unit respond institute Control node (Q) state is stated, when the control node (Q) is high level, the high level of the clock signal applies to institute Output unit is stated, makes gated sweep signal output part (133) the output high level, when the control node (Q) is low level When, the gated sweep signal output part (133) maintains low level;
The stabilization signal generation unit, including it is electrically connected to first node (QB) control terminal (143), the stabilization signal Generation unit is supplied to the first node (QB) for receiving direct current or AC signal to generate stabilization signal, to pull down stabilization The control node (Q) and the gated sweep signal;
The stable unit of drop-down, including the control node (Q) control terminal (142) is electrically connected to, the drop-down is stable Unit is used to utilize the stabilization signal for being supplied to the first node (QB) to believe the control node (Q) and the gated sweep Number maintain low level;
The synchronous trigger element, it is connected with the control node (Q), when video card is sent newly to the T-con of liquid crystal display device During one frame picture, vertical synchronizing signal can be carried at the top of new frame picture, the T-con is according to the vertical synchronizing signal The synchronous trigger element is supplied to after generation trigger signal, when the synchronous trigger element receives the trigger signal, It can force the control node (Q) of current line to end row and the gated sweep signal being pulled down to low level.
2. gate driving circuit according to claim 1, it is characterised in that the output unit includes the first transistor (T1) and bootstrap capacitor (C1), the grid of the first transistor (T1) is electrically connected to the control node (Q), and described first The grid of transistor (T1) is also electrically connected to the gated sweep signal output part (133) by the bootstrap capacitor (C1), The first end of the first transistor (T1) receives the clock signal, and the second end of the first transistor (T1) is electrically connected with To the gated sweep signal output part (133), for exporting the gated sweep signal.
3. gate driving circuit according to claim 1, it is characterised in that the synchronous trigger element includes the second crystal (T2), third transistor (T3) are managed, the grid of the second transistor (T2) receives the trigger signal, the second transistor (T2) first end is electrically connected with first voltage output end (VGL), and the second end of the second transistor (T2) is electrically connected with institute Gated sweep signal output part (133) is stated, the grid of the third transistor (T3) receives the trigger signal, and the described 3rd is brilliant The first end of body pipe (T3) is electrically connected with the first voltage output end (VGL), the second end electricity of the third transistor (T3) Property the connection control node (Q).
4. gate driving circuit according to claim 1, it is characterised in that the synchronous trigger element includes the 4th crystal Manage (T4), the grid and first end of the 4th transistor (T4) receive the trigger signal, the 4th transistor (T4) Second end is electrically connected to the first node (QB).
5. gate driving circuit according to claim 1, it is characterised in that the synchronous trigger element includes the 5th crystal (T5), the 6th transistor (T6), the 7th transistor (T7) are managed, described in the grid and first end of the 5th transistor (T5) receive Trigger signal, the second end of the 5th transistor (T5) are electrically connected to the first node (QB);6th transistor (T6) grid receives the trigger signal, and the first end of the 6th transistor (T6) is electrically connected with first voltage output end (VGL), the second end of the 6th transistor (T6) is electrically connected with the gated sweep signal output part (133);Described 7th The grid of transistor (T7) receives the trigger signal, and the first end of the 7th transistor (T7) is electrically connected with first electricity Output end (VGL) is pressed, the second end of the 7th transistor (T7) is electrically connected with the control node (Q).
6. gate driving circuit according to claim 5, it is characterised in that first voltage output end (VGL) connection Low level voltage source supplies device.
7. gate driving circuit according to claim 1, it is characterised in that last cascade of the gate driving circuit Connect end and transmit signal output part, signal, the trigger signal and the end of the gate driving circuit are transmitted to receive end Transmit the shared transmission lines of signal in the end for transmitting signal output part output.
8. a kind of liquid crystal display device, it is characterised in that it includes:
Display panel, the panel includes the two-dimensional array being made up of multiple pixels, and is connected with each pel array The a plurality of gate line of first direction and a plurality of data lines of second direction;
Data drive circuit, for providing picture signal to the data wire;
Such as the gate driving circuit any one of claim 1-7, for giving the gate line to provide gated sweep signal.
CN201610069967.4A 2016-02-01 2016-02-01 Gate driving circuit and liquid crystal display device CN105609078B (en)

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CN103236241A (en) * 2013-04-18 2013-08-07 京东方科技集团股份有限公司 Display panel driving method, driving device and display device
CN104299587A (en) * 2014-10-22 2015-01-21 重庆京东方光电科技有限公司 Display device driving method and display device

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JP5122396B2 (en) * 2008-08-01 2013-01-16 ルネサスエレクトロニクス株式会社 Driver and display device
KR20140053627A (en) * 2012-10-26 2014-05-08 삼성전자주식회사 Display driver circuit and display device
KR101602199B1 (en) * 2012-12-11 2016-03-10 엘지디스플레이 주식회사 Display device with integrated touch screen and method for driving the same

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Publication number Priority date Publication date Assignee Title
CN103236241A (en) * 2013-04-18 2013-08-07 京东方科技集团股份有限公司 Display panel driving method, driving device and display device
CN104299587A (en) * 2014-10-22 2015-01-21 重庆京东方光电科技有限公司 Display device driving method and display device

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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou

Patentee after: Kunshan Longteng Au Optronics Co

Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou

Patentee before: Kunshan Longteng Optronics Co., Ltd.