CN105608029B - Process layer data packet generation method, device and PCI Express systems - Google Patents
Process layer data packet generation method, device and PCI Express systems Download PDFInfo
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- CN105608029B CN105608029B CN201510963001.0A CN201510963001A CN105608029B CN 105608029 B CN105608029 B CN 105608029B CN 201510963001 A CN201510963001 A CN 201510963001A CN 105608029 B CN105608029 B CN 105608029B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The present invention provides a kind of process layer data packet generation method, device and PCI Express systems, this method to include：Control process layer generates initial TLP, and initial TLP includes reserved field, head file, data field and abstract fields, and reserved field includes opening flag field, sequence-number field, LCRC fields and the end mark field of blank；Control data link layer and physical layer calculate and fill in reserved field, generate final TLP.Implementation through the invention, due to need not be shifted to TLP packets, reduces the transmission delay of TLP during generating TLP.
Description
Technical field
The present invention relates to high-speed serial bus fields, more particularly to one kind being used for PCI Express (Peripheral
Component Interconnect Express, high speed outer apparatus interconnection bus) system process layer data packet generation side
Method, device and PCI Express.
Background technology
PCI Express technologies are the 3rd generation high-performance I/O bus skills proposed to adapt to the development of computer technology
The software frame of art, PCI Express technologies is that (Peripheral Component Interconnect, outside is set with PCI
Standby interconnection bus) technology software frame it is completely compatible, from PCI technologies using parallel data transmission different, PCI Express skills
Art is to use serial data transmission.
PCI Express agreements provide that PCI Express are made of physical layer, data link layer and process layer；Wherein
Process layer mainly realizes group packet and the unpacking of TLP (Transaction Layer Packet, process layer data packet)；Data link
The major function of floor is the integrality for the TLP for ensureing to send and receive on each chain road, and data link layer is generated by sequence number
Ensure with detection circuit and LCRC (Link Cyclic Redundancy Check, link layer cycle redundancy check) circuits
Data packet is correctly transmitted.
As shown in Figure 1, TLP structures and each layer in PCI Express of relationship, in the prior art, process layer generates
When TLP, TLP is only generatedDPart, i.e. head file Header, data field Data and abstract fields Digest in Fig. 1, length
Degree is the integral multiple of DW (1DW=4Byte), adds the sequence-number field of 2Byte long when TLP is transferred to data link layer again
The LCRC values of Sequence Number and 1DW long add the opening flag field of 1Byte long again when TLP is transferred to physical layer
The end mark field END of STP and 1Byte long.That is, existing TLP generation methods need to carry out in data link layer and physical layer
Shifting function will increase the transmission delay of TLP.
Therefore, existing TLP generation methods needs can be solved in data link layer and physical layer progress by how providing one kind
The TLP generation methods of shifting function are those skilled in the art's technical problems urgently to be resolved hurrily.
Invention content
The present invention provides a kind of process layer data packet generation method, device and PCI for PCI Express systems
Express needs with physical layer caused by shifting function increase in data link layer to solve existing TLP generation methods
The problem of TLP transmission delays.
The present invention provides a kind of TLP generation methods for PCI Express systems, PCI Express include processing
Layer, data link layer and physical layer, TLP generation methods include：Control process layer generates initial TLP, and initial TLP includes writeeing down characters in advance
Section, head file, data field and abstract fields, reserved field include the opening flag field, sequence-number field, LCRC words of blank
Section and end mark field；Control data link layer and physical layer calculate and fill in reserved field, generate final TLP.
Further, it calculates and fills in reserved field and generate final TLP and include：Control physical layer is determining and fills in beginning
Attribute field and end mark field, control data link layer is determining and fills in sequence-number field, and control LCRC circuit countings are simultaneously
Fill in LCRC fields.
Further, LCRC circuits include the cardiopulmonary bypass in beating heart redundancy check circuit of multiple and different input bit wides；Control LCRC
Circuit counting simultaneously fills in LCRC fields and includes：According to the valid data bit wide of initial TLP, the parallel of corresponding input bit wide is enabled
CRC circuit calculates and fills in LCRC.
Further, enabling the corresponding Parallel CRC circuit counting link CRC for inputting bit wide includes：Detect opening flag
Field determines the valid data bit wide of period 1 based on opening flag field, selects the Parallel CRC circuit of period 1, and
The initial value for generating the Parallel CRC circuit of period 1, calculates output valve；In the selection of next period and internal bus data bit
The corresponding Parallel CRC circuit of width, using the output valve of the Parallel CRC circuit of previous cycle as the Parallel CRC circuit in this period
Initial value calculates output valve；It detects end mark field, the significant figure in last period is determined based on end mark field
According to bit wide, the Parallel CRC circuit in last period is selected, using the output valve of the Parallel CRC circuit of previous cycle as this period
Parallel CRC circuit initial value, calculate output valve, and as LCRC.
Further, further include：When initial TLP is back-to-back TLP, the opening flag field and knot of initial TLP are detected
Back-to-back TLP is split as two pending initial TLP, while handling two pending initial TLP by bundle flag field.
Further, while two pending initial TLP of processing include：It is multiplexed the Parallel CRC electricity of different input bit wides
Road calculates LCRC fields.
The present invention provides a kind of TLP generating means for PCI Express systems, PCI Express include processing
Layer, data link layer and physical layer, TLP generating means include：Reserved module generates initial TLP, initially for control process layer
TLP includes reserved field, head file, data field and abstract fields, and reserved field includes opening flag field, the sequence of blank
Number field, LCRC fields and end mark field；Control module, for controlling data link layer and physical layer is calculated and filled in pre-
It writes down characters section, generates final TLP.
Further, control module fills in opening flag field and end mark field for controlling physical layer, controls number
Sequence-number field is filled according to link layer, control LCRC circuit countings and fills in LCRC fields.
Further, LCRC circuits include the Parallel CRC circuit of multiple and different input bit wides；Control module is used for according to just
The valid data bit wide of beginning TLP, the Parallel CRC circuit counting of enabled corresponding input bit wide simultaneously fill in LCRC.
Further, control module determines the period 1 for detecting opening flag field based on opening flag field
Valid data bit wide, select the Parallel CRC circuit of period 1, and generate the initial value of the Parallel CRC circuit of period 1,
Calculate output valve；Select corresponding with internal bus data bit width Parallel CRC circuit in next period, by previous cycle and
Initial value of the output valve of row CRC circuit as the Parallel CRC circuit in this period, calculates output valve；Detect end mark
Field determines the valid data bit wide in last period based on end mark field, selects the Parallel CRC electricity in last period
Road calculates output using the output valve of the Parallel CRC circuit of previous cycle as the initial value of the Parallel CRC circuit in this period
Value, and as LCRC.
Further, control module is additionally operable to, when initial TLP is back-to-back TLP, detect the opening flag word of initial TLP
Back-to-back TLP is split as two pending initial TLP by section and end mark field, at the same handle two it is pending just
Beginning TLP.
Further, control module is used to be multiplexed the Parallel CRC circuit of different input bit wides, calculates LCRC fields.
The present invention provides a kind of PCI Express systems comprising TLP generating means provided by the invention use TLP
Generating means generate TLP.
Beneficial effects of the present invention：
The present invention provides a kind of new TLP generation methods, generate initial TLP by control process layer, initial TLP includes
Reserved field, head file, data field and abstract fields, reserved field include the opening flag field of blank, sequence-number field,
LCRC fields and end mark field, control data link layer and physical layer calculates and fill in reserved field, generate final
TLP；During generating TLP, due to need not be shifted to TLP packets, the transmission delay of TLP is reduced.Into one
Step, LCRC values are calculated using the structure of full parellel, realizes and handles back-to-back TLP without packet loss, ensure that TLP is transmitted
Bandwidth.Further, to back-to-back TLP deconsolidation process, and to the Parallel CRC circuit multiplexer of different input bit wides, reduce electricity
Road resource overhead.
Description of the drawings
Fig. 1 is TLP structures and each layer in PCI Express of calculated relationship；
Fig. 2 is the structural schematic diagram for the TLP generating means that first embodiment of the invention provides；
Fig. 3 is the flow chart for the TLP generation methods that second embodiment of the invention provides；
Fig. 4 is internal transmission bus bit wide when being 128b it, common back-to-back TLP transmission modes；
Fig. 5 is the LCRC circuit function block diagrams that third embodiment of the invention provides.
Specific implementation mode
Further annotation explanation now is made to the present invention by way of specific implementation mode combination attached drawing.
First embodiment：
Fig. 2 is the structural schematic diagram for the TLP generating means that first embodiment of the invention provides, as shown in Figure 2, in this implementation
In example, TLP generating means 2 provided by the invention include：
Reserved module 21 generates initial TLP for control process layer, and initial TLP includes reserved field, head file, data
Field and abstract fields, reserved field include opening flag field, sequence-number field, LCRC fields and the end mark word of blank
Section；
Control module 22 calculates and fills in reserved field for controlling data link layer and physical layer, generates final
TLP。
In some embodiments, the control module 22 in above-described embodiment fills in opening flag field for controlling physical layer
And end mark field, control data link layer fill in sequence-number field, control LCRC circuit countings and fill in LCRC fields.
In some embodiments, the LCRC circuits in above-described embodiment include the Parallel CRC electricity of multiple and different input bit wides
Road；Control module 22 is used for the valid data bit wide according to initial TLP, enables the Parallel CRC circuit counting of corresponding input bit wide
And fill in LCRC.
In some embodiments, the control module 22 in above-described embodiment is for detecting opening flag field, based on opening
Beginning attribute field determines the valid data bit wide of period 1, selects the Parallel CRC circuit of period 1, and generates the period 1
Parallel CRC circuit initial value, calculate output valve；It is corresponding with internal bus data bit width parallel in the selection of next period
CRC circuit is calculated using the output valve of the Parallel CRC circuit of previous cycle as the initial value of the Parallel CRC circuit in this period
Output valve；It detects end mark field, the valid data bit wide in last period is determined based on end mark field, selection is most
The Parallel CRC circuit in latter period, using the output valve of the Parallel CRC circuit of previous cycle as the Parallel CRC circuit in this period
Initial value, calculate output valve, and as LCRC.
In some embodiments, the control module 22 in above-described embodiment is additionally operable to when initial TLP is back-to-back TLP,
Back-to-back TLP is split as two pending initial TLP by the opening flag field and end mark field for detecting initial TLP,
Two pending initial TLP are handled simultaneously.
In some embodiments, the control module 22 in above-described embodiment is used to be multiplexed the Parallel CRC of different input bit wides
Circuit calculates LCRC fields.
The present invention provides a kind of PCI Express comprising TLP generating means 2 provided by the invention are given birth to using TLP
TLP is generated at device 2.
Second embodiment：
Fig. 3 is the flow chart for the TLP generation methods that second embodiment of the invention provides, from the figure 3, it may be seen that in the present embodiment
In, TLP generation methods provided by the invention include the following steps：
S301：Control process layer generates initial TLP, and initial TLP includes reserved field, head file, data field and abstract
Field, reserved field include opening flag field, sequence-number field, LCRC fields and the end mark field of blank；
S302：Control data link layer and physical layer calculate and fill in reserved field, generate final TLP.
In some embodiments, it the calculating in above-described embodiment and fills in reserved field and generates final TLP and include：Control
Physical layer is determining and fills in opening flag field and end mark field, and control data link layer is determining and fills in sequence number word
Section controls LCRC circuit countings and fills in LCRC fields.
Further, LCRC circuits include the Parallel CRC circuit of multiple and different input bit wides；Control LCRC circuit countings simultaneously
Filling in LCRC fields includes：According to the valid data bit wide of initial TLP, the Parallel CRC circuit counting of corresponding input bit wide is enabled
And fill in LCRC.
In some embodiments, the Parallel CRC circuit counting of the enabled corresponding input bit wide in above-described embodiment links CRC
Including：
It detects opening flag field, determines the valid data bit wide of period 1 based on opening flag field, selection the
The Parallel CRC circuit in one period, and the initial value of the Parallel CRC circuit of period 1 is generated, calculate output valve；
Parallel CRC circuit corresponding with internal bus data bit width is selected in next period, by the Parallel CRC of previous cycle
Initial value of the output valve of circuit as the Parallel CRC circuit in this period, calculates output valve；
It detects end mark field, the valid data bit wide in last period is determined based on end mark field, select
The Parallel CRC circuit in last period, using the output valve of the Parallel CRC circuit of previous cycle as the Parallel CRC in this period electricity
The initial value on road calculates output valve, and as LCRC.
In some embodiments, the method in above-described embodiment further includes：When initial TLP is back-to-back TLP, detection is just
Back-to-back TLP is split as two pending initial TLP, located simultaneously by the opening flag field and end mark field of beginning TLP
Manage two pending initial TLP.
In some embodiments, in above-described embodiment two pending initial TLP are handled while includes：Multiplexing is different
The Parallel CRC circuit of bit wide is inputted, LCRC fields are calculated.
Further annotation explanation is done to the present invention in conjunction with concrete application scene.
3rd embodiment：
The LCRC values of TLP are to be then added to the end of TLP after the completion of LCRC circuit countings in existing PCI Express
Mark, in this way processing need to carry out TLP shift align operations, can increase the transmission delay of TLP；Existing PCI
When the back-to-back TLP of LCRC processing of circuit in Express, calculated using the identical LCRC circuits in 2 tunnels, the money of LCRC circuits
Source expense is very big；It is big for internal data bit wide when the back-to-back TLP of LCRC processing of circuit in existing PCI Express, such as
128b it bit wides, the LCRC circuit schemes that do not announce.
To solve the above-mentioned problems, the present embodiment is in process layer group packet TLP, advance in TLP LCRC values and its
The position of its added value, due to TLP start mark and the bit wide of TLP end of identification be it is unfixed, LCRC circuits needs
It is made of the Parallel CRC circuit of multiple and different input bit wides；The number of CRC circuit is related with internal bus transmission bit wide.
LCRC circuits provided by the invention are made according to testing result using the valid data bit wide of dynamic detection input TLP
The Parallel CRC circuit that bit wide can accordingly be inputted is calculated, and control one switching gate of multiselect correspond to the initial value of CRC circuit with
Input value.Further, by the detection for starting mark and TLP end of identification to TLP, back-to-back TLP packets are split as 2
Independent TLP, and crc value calculating is carried out to 2 TLP simultaneously, 2 TLP are multiplexed the Parallel CRC circuit of different input bit wides.It is logical
The detection to TLP end of identification is crossed, control selections correspond to final LCRC value of the output of CRC circuit as current calculating TLP packets,
And LCRC values are filled into TLP end of identification.
Based on said program the transmission delay of TLP is reduced due to need not be shifted to TLP packets.Using complete
Parallel structure calculates LCRC values, realizes and handles back-to-back TLP packets without packet loss, ensure that TLP transmission bandwidths.To the back of the body
Backrest TLP deconsolidation process, and to the Parallel CRC circuit multiplexer of different input bit wides, reduce circuit resource expense.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with attached drawing 4 and 5, within
The case where portion's transfer bus bit wide is 128b it, technical solution in the embodiment of the present invention is described in detail.
Fig. 1 shows TLP pack arrangements and each layer in PCI Express of relationship.In traditional processing method, processing
When layer generates TLP, TLP is only generatedDThe part (Header, Data and Digest in Fig. 1), the integral multiple of the length of DW
(1DW=4Byte)；The LCRC of the Sequence Number and 1DW long of 2Byte long are added when TLP is transferred to data link layer again
Value；The END of the STP and 1Byte long of 1Byte long are added when TLP is transferred to physical layer again.When conventionally handling, TLP is needed
Shifting function is carried out in data link layer and physical layer.In the present invention when process layer generates TLP, then advance for
The position of Sequence Number, LCRC, STP and END can eliminate the influence of displacement delay, but data link layer in this way
When handling TLP, the processing layer segment of TLP is not that DW is aligned, it is therefore desirable to is further processed, TLP is existed using small end
Preceding transmission mode that is to say that first transmission STP finally transmits END.
With reference to Fig. 4, when showing that internal transmission bus bit wide is 128bit, common several back-to-back TLP transmission modes,
DW0, DW1, DW2 and DW3 on abscissa in each figures of Fig. 4 indicates the 1st DW, the 2nd DW, the 3rd DW of transmission respectively
And the 4th DW；Period on ordinate indicates the scale of time cycle.By taking Fig. 4 a as an example, LCRC's on the 1st period has
It is 120b it that effect, which calculates bit wide, (STP needs not participate in calculating)；N-th of period is upper while having the data of 2 TLP, the 1st frame TLP
Effective calculating bit wide of LCRC be 56bit (LCRC with END need not participate in calculating), effective calculating of the LCRC of the 2nd frame TLP
Bit wide is 24bit (STP needs not participate in calculating)；Effective calculating bit wide of the middle sections TLP is 128bit.Similar approach can be with
Effective calculating bit wide of LCRC when each period in Fig. 4 a-4f transmission modes is obtained, 24bit, 56bit, 88bit, 120bit are shared
And 128bit these types patterns.When for pattern in Fig. 4 b, effective LCRC calculating parts of previous frame TLP and next frame TLP
It is 24bit to divide bit wide simultaneously, therefore needs to calculate the LCRC circuit modules of 2 24bit on same period simultaneously.Therefore, implement
The Parallel CRC circuit module of 1 128bit, 1 120bit, 1 88bit, 1 56bit and 2 24bit are needed in example.
With reference to Fig. 5, show that a kind of LCRC circuits realize structure diagram.TLP_stp and TLP_end is respectively TLP in figure
Effective start bit compiles signal with effective stop bits.Selection_ctrl modules generate more according to TLP_stp values and TLP_end values
Select the control signal of the control signal and in_selection modules of one (MUX).In_selection modules according to
The control signal that selection_ctrl is generated, corresponding CRC module is input to by the useful signal on TLP.MUX modules according to
The control signal that selection_ctrl is generated generates the initial value of corresponding CRC module.The each computation of Period of CRC module goes out
Output valve is exported by register (FF), and initial value when being calculated as next cycle.When TLP_end is effective, then
Selection_ctrl modules generate control signal and select the output of corresponding CRC module, as calculated final LCRC values.
For calculating the LCRC of the TLP in Fig. 4 a：When the 1st period, selection_ctrl modules detect TLP_
Stp effectively (TLP_stp is equal to 1, STP on DW0), then generate control signal and enable CRC32_parallelx120 module works
Make, and control the initial value that MUX selects 32'hffffffff as module, and control in_selection modules generate TLP
[127:8] input calculated as module；When the 2nd period, selection_ctrl modules enable CRC32_
Parallelx128 modules work, and control MUX and the output valve of CRC32_parallelx120 modules is selected to be calculated as current
Initial value, TLP [127:0] as the input evaluation calculated；When 3- (n-1) a periods, selection_ctrl modules make
Can the work of CRC32_parallelx128 modules, and control MUX select the output valves of CRC32_parallelx128 modules as
The initial value currently calculated, TLP [127:0] as the input evaluation calculated；When n-th of period, selection_ctrl modules
It detects TLP_end effectively (TLP_end is equal to 4, END on DW2), then generates control signal and enable CRC32_
Parallelx56 modules work, and it is initial that control MUX selects the output of CRC32_parallelx128 modules to be calculated as module
Value, and control in_selection modules generate TLP [55:0] input calculated as module, and selected according to TLP_end values
Select final LCRC value of the calculating output of CRC32_parallelx56 modules as current TLP；When on n-th of period simultaneously
It also detects TLP_stp effectively (TLP_stp is equal to 8, STP on DW3), therefore can also enable CRC32_ simultaneously
Parallelx24 modules work, identical when computational methods are with the 1st period.
In summary, at least there is following advantageous effect in implementation through the invention：
The present invention provides a kind of new TLP generation methods, generate initial TLP by control process layer, initial TLP includes
Reserved field, head file, data field and abstract fields, reserved field include the opening flag field of blank, sequence-number field,
LCRC fields and end mark field, control data link layer and physical layer calculates and fill in reserved field, generate final
TLP；During generating TLP, due to need not be shifted to TLP packets, the transmission delay of TLP is reduced.Into one
Step, LCRC values are calculated using the structure of full parellel, realizes and handles back-to-back TLP without packet loss, ensure that TLP is transmitted
Bandwidth.Further, to back-to-back TLP deconsolidation process, and to the Parallel CRC circuit multiplexer of different input bit wides, reduce electricity
Road resource overhead.
It the above is only the specific implementation mode of the present invention, limitation in any form not done to the present invention, it is every
Arbitrary simple modification, equivalent variations, combination or the modification that embodiment of above is made according to the technical essence of the invention, still
Belong to the protection domain of technical solution of the present invention.
Claims (13)
1. a kind of process layer data packet generation method for high speed outer apparatus interconnection bus system, the high speed outer equipment
Interconnecting bus system includes process layer, data link layer and physical layer, which is characterized in that the process layer data packet generation method
Including：
It controls the process layer and generates initial treatment layer data packet, the initial treatment layer data packet includes reserved field, head word
Section, data field and abstract fields, the reserved field include that the opening flag field, sequence-number field, link layer of blank are followed
Ring redundancy check field and end mark field；
It controls the data link layer and the physical layer calculates and fill in the reserved field, generate final processing layer data
Packet.
2. process layer data packet generation method as described in claim 1, which is characterized in that the calculating is simultaneously filled in described reserved
Field generates final process layer data packet：It controls the physical layer determination and fills in opening flag field and end mark
Field controls the data link layer determination and fills in the sequence-number field, controls link layer cyclic redundancy check circuit meter
It calculates and fills in the link layer cycle redundancy check field.
3. process layer data packet generation method as claimed in claim 2, which is characterized in that the link layer cycle redundancy check
Circuit includes the cardiopulmonary bypass in beating heart redundancy check circuit of multiple and different input bit wides；The control link layer cycle redundancy check
Circuit counting simultaneously fills in link layer cycle redundancy check field and includes：According to the valid data position of the initial treatment layer data packet
Width, the cardiopulmonary bypass in beating heart redundancy check circuit counting of enabled corresponding input bit wide simultaneously fill in the link layer cycle redundancy check word
Section.
4. process layer data packet generation method as claimed in claim 3, which is characterized in that the enabled corresponding input bit wide
Link layer cycle redundancy check field includes described in cardiopulmonary bypass in beating heart redundancy check circuit counting：Detect the opening flag word
Section, the valid data bit wide of period 1 is determined based on the opening flag field, selects the cardiopulmonary bypass in beating heart redundancy of period 1
Checking circuit, and the initial value of the cardiopulmonary bypass in beating heart redundancy check circuit of the period 1 is generated, calculate output valve；Next
Period selects cardiopulmonary bypass in beating heart redundancy check circuit corresponding with internal bus data bit width, by the cardiopulmonary bypass in beating heart redundancy of previous cycle
Initial value of the output valve of checking circuit as the cardiopulmonary bypass in beating heart redundancy check circuit in this period, calculates output valve；It detects
The end mark field is determined the valid data bit wide in last period based on the end mark field, selects last
The cardiopulmonary bypass in beating heart redundancy check circuit in period, using the output valve of the cardiopulmonary bypass in beating heart redundancy check circuit of previous cycle as this period
Cardiopulmonary bypass in beating heart redundancy check circuit initial value, calculate output valve, and as the link layer cycle redundancy check
Field.
5. such as Claims 1-4 any one of them process layer data packet generation method, which is characterized in that further include：When described
When initial treatment layer data packet is back-to-back process layer data packet, the opening flag field of the initial treatment layer data packet is detected
And end mark field, the back-to-back process layer data packet is split as two pending initial treatment layer data packets, together
When handle described two pending initial treatment layer data packets.
6. process layer data packet generation method as claimed in claim 5, which is characterized in that described while handling described two wait for
The initial treatment layer data packet of processing includes：It is multiplexed the cardiopulmonary bypass in beating heart redundancy check circuit of different input bit wides, calculates the chain
Road floor cyclic redundancy check field.
7. a kind of process layer data packet generating device for high speed outer apparatus interconnection bus system, the high speed outer equipment
Interconnecting bus system includes process layer, data link layer and physical layer, which is characterized in that the process layer data packet generating device
Including：
Reserved module generates initial treatment layer data packet for controlling the process layer, and the initial treatment layer data packet includes
Reserved field, head file, data field and abstract fields, the reserved field include the opening flag field of blank, sequence number
Field, link layer cycle redundancy check field and end mark field；
Control module calculates and fills in the reserved field for controlling the data link layer and the physical layer, generates most
Whole process layer data packet.
8. process layer data packet generating device as claimed in claim 7, which is characterized in that the control module is for controlling institute
It states physical layer and fills in opening flag field and end mark field, control the data link layer and fill in the sequence-number field,
Control link layer cyclic redundancy check circuit counting simultaneously fills in the link layer cycle redundancy check field.
9. process layer data packet generating device as claimed in claim 8, which is characterized in that the link layer cycle redundancy check
Circuit includes the cardiopulmonary bypass in beating heart redundancy check circuit of multiple and different input bit wides；The control module is used for according to the initial place
The valid data bit wide of layer data packet is managed, the cardiopulmonary bypass in beating heart redundancy check circuit counting of enabled corresponding input bit wide is simultaneously filled in described
Link layer cycle redundancy check field.
10. process layer data packet generating device as claimed in claim 9, which is characterized in that the control module is for detecting
To the opening flag field, the valid data bit wide of period 1 is determined based on the opening flag field, is selected first week
The cardiopulmonary bypass in beating heart redundancy check circuit of phase, and the initial value of the cardiopulmonary bypass in beating heart redundancy check circuit of the period 1 is generated, it counts
Calculate output valve；Cardiopulmonary bypass in beating heart redundancy check circuit corresponding with internal bus data bit width is selected in next period, it will be previous
Initial value of the output valve of the cardiopulmonary bypass in beating heart redundancy check circuit in period as the cardiopulmonary bypass in beating heart redundancy check circuit in this period, meter
Calculate output valve；It detects the end mark field, the significant figure in last period is determined based on the end mark field
According to bit wide, the cardiopulmonary bypass in beating heart redundancy check circuit in last period is selected, by the cardiopulmonary bypass in beating heart redundancy check circuit of previous cycle
Output valve as this period cardiopulmonary bypass in beating heart redundancy check circuit initial value, calculate output valve, and as described
Link layer cycle redundancy check field.
11. such as claim 7 to 10 any one of them process layer data packet generating device, which is characterized in that the control mould
Block is additionally operable to, when the initial treatment layer data packet is back-to-back process layer data packet, detect the initial treatment layer data packet
Opening flag field and end mark field, the back-to-back process layer data packet is split as two pending initial places
Layer data packet is managed, while handling described two pending initial treatment layer data packets.
12. process layer data packet generating device as claimed in claim 11, which is characterized in that the control module is for being multiplexed
The cardiopulmonary bypass in beating heart redundancy check circuit of difference input bit wide, calculates the link layer cycle redundancy check field.
13. a kind of high speed outer apparatus interconnection bus system, which is characterized in that including as described in any one of claim 7 to 12
Process layer data packet generating device, use the process layer data packet generating device generate process layer data packet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510963001.0A CN105608029B (en) | 2015-12-17 | 2015-12-17 | Process layer data packet generation method, device and PCI Express systems |
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| CN1148667C (en) * | 1999-05-31 | 2004-05-05 | 德国汤姆森-布兰特有限公司 | Data pack preprocessing method and bus interface and data processing unit thereof |
| CN1719809A (en) * | 2005-08-02 | 2006-01-11 | 威盛电子股份有限公司 | Data processing method and system for serial transmission interface |
| CN101204070A (en) * | 2005-06-21 | 2008-06-18 | Nxp股份有限公司 | Method for parallel data integrity checking of PCI EXPRESS devices |
| CN101681325A (en) * | 2007-06-29 | 2010-03-24 | 国际商业机器公司 | Device, system and method of modification of pci express packet digest |
| CN102349059A (en) * | 2009-04-17 | 2012-02-08 | 株式会社东芝 | TLP processing circuit for PCI Express and relay device equipped with the same |
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| US8234424B2 (en) * | 2006-06-08 | 2012-07-31 | Integrated Device Technology, Inc. | Efficient strip-down and re-alignment of ingressing physical layer/data layer packets in an aggregated PCI-express port having eight lanes |
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| CN1148667C (en) * | 1999-05-31 | 2004-05-05 | 德国汤姆森-布兰特有限公司 | Data pack preprocessing method and bus interface and data processing unit thereof |
| CN101204070A (en) * | 2005-06-21 | 2008-06-18 | Nxp股份有限公司 | Method for parallel data integrity checking of PCI EXPRESS devices |
| CN1719809A (en) * | 2005-08-02 | 2006-01-11 | 威盛电子股份有限公司 | Data processing method and system for serial transmission interface |
| CN101681325A (en) * | 2007-06-29 | 2010-03-24 | 国际商业机器公司 | Device, system and method of modification of pci express packet digest |
| CN102349059A (en) * | 2009-04-17 | 2012-02-08 | 株式会社东芝 | TLP processing circuit for PCI Express and relay device equipped with the same |
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