CN105591027B - Resistor type non-volatile memory device and its manufacturing method - Google Patents
Resistor type non-volatile memory device and its manufacturing method Download PDFInfo
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Abstract
The present invention provides a kind of resistor type non-volatile memory device and its manufacturing method.Wherein, above-mentioned resistor type non-volatile memory device includes a first electrode, wherein having one first admixture in above-mentioned first electrode；One second electrode is set in above-mentioned first electrode；One resistance transition layer, is set between above-mentioned first electrode and above-mentioned second electrode.Resistor type non-volatile memory device provided by the invention and its manufacturing method in hearth electrode by mixing admixture or reducing the modes such as hearth electrode thickness, the crystal grain size of hearth electrode is controlled, to promote the flatness at the interface between hearth electrode and resistance transition layer in final resistor type non-volatile architecture of memory device.The reliability of resistor type non-volatile memory device can thus be promoted.
Description
Technical field
The present invention relates to a kind of resistor type non-volatile memory device and its manufacturing methods, especially with regard to a kind of tool
The resistor type non-volatile memory device and its manufacturing method of high-reliability.
Background technique
Resistor type non-volatile memory (RRAM) because have power consumption it is low, operation voltage it is low, write-in erase the time it is short,
The advantages that durability degree is long, storage time is long, non-destructive is read, multimode stores, component technology is simple and scaling performance, so
Mainstream as emerging nonvolatile memory.The basic structure of existing resistor type non-volatile memory is hearth electrode, electricity
A metal-insulator-metal type (metal-insulator-metal, MIM) layered structure that transition layer and top electrode are constituted is hindered,
And resistance conversion (resistive switching, the RS) resistance characteristic of resistor type non-volatile memory is the important of element
Characteristic.
Summary of the invention
The present invention provides a kind of resistor type non-volatile memory device and its manufacturing method, to promote resistor-type nonvolatile
The reliability of property memory device.
One embodiment of the invention provides a kind of resistor type non-volatile memory device.Above-mentioned resistor type non-volatile
Memory device includes a first electrode, wherein having an admixture in above-mentioned first electrode；One second electrode is set to above-mentioned
On one electrode；One resistance transition layer, is set between above-mentioned first electrode and above-mentioned second electrode.
Another embodiment of the present invention provides a kind of resistor type non-volatile memory device.Above-mentioned resistor-type nonvolatile
Property memory device include a first electrode, wherein above-mentioned first electrode is a layered structure, including one first metal nitride
Layer has a first thickness；One metal oxide layer has a second thickness, and is located in above-mentioned first metal nitride layer；
One second electrode is set in above-mentioned first electrode, wherein above-mentioned first thickness and above-mentioned second thickness are smaller than above-mentioned second
One thickness of electrode；One resistance transition layer, is set between above-mentioned first electrode and above-mentioned second electrode.
Another embodiment of the present invention provides a kind of manufacturing method of resistor type non-volatile memory device.Above-mentioned electricity
The manufacturing method of resistive non-volatile memory device includes providing semiconductor substrate；It is electric in forming one first on aforesaid substrate
Pole；An admixture is adulterated in above-mentioned first electrode；In forming a resistance transition layer in above-mentioned first electrode；In above-mentioned resistance transition
A second electrode is formed on layer.
The embodiment of the invention provides a kind of resistor type non-volatile memory device and its manufacturing methods.By in bottom electricity
The modes such as incorporation admixture or reduction hearth electrode thickness, control the crystal grain size of hearth electrode, to promote final resistance-type in extremely
The flatness at the interface between the hearth electrode in non-volatile memory device structure and resistance transition layer.Electricity can thus be promoted
The reliability of resistive non-volatile memory device.
Detailed description of the invention
Fig. 1 shows the diagrammatic cross-section of the resistor type non-volatile memory device of one embodiment of the invention.
Fig. 2 shows the diagrammatic cross-section of the resistor type non-volatile memory device of another embodiment of the present invention.
Fig. 3 shows the diagrammatic cross-section of the resistor type non-volatile memory device of another embodiment of the present invention.
Fig. 4 A, Fig. 4 B, Fig. 5 show the intermediate work of the resistor type non-volatile memory device of some embodiments of the present invention
The diagrammatic cross-section of skill step.
Fig. 6, Fig. 7, Fig. 8 A~Fig. 8 C, Fig. 9 A, Fig. 9 B show the resistor-type nonvolatile of some other embodiments of the invention
The diagrammatic cross-section of the intervening process steps of property memory device.
Drawing reference numeral explanation:
500a, 500b, 500c~resistor type non-volatile memory device；
250a, 250b, 250c~metal-insulator-metal type are laminated；
200~semiconductor substrate；
202~circuit；
204,218~interlayer dielectric layer；
205,217~top surface；
206~first electrode contact plunger；
216~second electrode contact plunger；
208a~208c~first electrode；
210~resistance transition layer；
212~second electrode；
208b1~metal nitride layer；
208b2~metal oxide layer；
208b3~metal nitride layer；
208c3~metal nitride layer；
210a~resistance transition material layer；
212a~second electrode material layer；
208b1,208b3,208c3~metal nitride layer；
208b2~metal oxide layer；
209~interface；
214~barrier laying；
220~admixture；
222,238,240,242,244~sputtering technology；
233,246~ion implantation technology；
224~sputtering target material；
224a~metal material；
224b~admixture；
230~hard mask pattern；
226~sputtering machine table cavity；
228~microscope carrier；
234,234 '~gas；
308a~first electrode material layer；
308b1,308b3,308c3~metal nitride materials layer；
308b2~metal nitride materials layer；
A1, A2, T1, T2, T3~thickness.
Specific embodiment
In order to which the purpose of the present invention, feature and advantage can be clearer and more comprehensible, special embodiment below, and appended by cooperation
Diagram, is described in detail.Description of the invention provides different embodiments to illustrate the technology of different embodiments of the present invention
Feature.Wherein, each element in embodiment is configured to purposes of discussion, is not intended to limit the invention.And schema in embodiment
The part of label repeats, and is the relevance being not meant as between different embodiments to simplify the explanation.
The embodiment of the invention provides a kind of nonvolatile memory and its manufacturing methods, for example, a resistor-type nonvolatile
Property memory (RRAM) device, can be because between hearth electrode and resistance transition layer to improve existing resistor type non-volatile memory
Interface flat degree it is bad and caused by the big problem of resistance transfer characteristic amount of variability.The above problem is likely due to hearth electrode
It is recrystallized after there is the last part technology (backend on line (BEOL)) of heat treatment (thermal treatment)
Crystal grain (chip) size it is uneven and cause.In resistor type non-volatile memory (RRAM) device of the embodiment of the present invention,
Admixture is mixed in hearth electrode during forming hearth electrode or after forming hearth electrode.Alternatively, forming the bottom electricity with layered structure
Pole has at least one layer of metal nitride layer and one layer of metal oxide layer, and reduces the metal contacted with resistance transition layer
The equivalent thickness of nitride layer.After having the last part technology (BEOL) of heat treatment, the hearth electrode for crystalline state of signing an undertaking can have
Smaller and more uniform crystallite dimension, and the interface flat degree between hearth electrode and resistance transition layer can be promoted.
Fig. 1 shows the diagrammatic cross-section of resistor type non-volatile memory (RRAM) device 500a.As shown in Figure 1, RRAM
Device 500a may be disposed on the semiconductor substrate 200 of such as silicon substrate, and can be connected to and be set on semiconductor substrate 200
A circuit 202.Other a variety of isolated electronic components, above-mentioned electronic component can also be set on above-mentioned semiconductor substrate 200
Can be includes transistor, diode, capacitor, inductance and other actives or non-active semiconductor element.RRAM device 500a's
Main element includes a first electrode contact plunger 206, a first electrode 208a, a resistance transition layer 210, a second electrode
212 and a second electrode contact plunger 216.Above-mentioned first electrode 208a, resistance transition layer 210 and second electrode 212 structure together
At a metal-insulator-metal type (MIM) laminated 250a.
As shown in Figure 1, first electrode contact plunger 206 is set on above-mentioned semiconductor substrate 200, and it is electrically connected to and sets
The circuit 202 being placed on semiconductor substrate 200.First electrode contact plunger 206 is disposed through on above-mentioned semiconductor substrate 200
Interlayer dielectric layer 204.In some embodiment of the invention, circuit 202 is to apply operation voltage to RRAM device 500a.
Circuit 202 can be the circuit for including the combination of the electronic components such as transistor, diode, capacitor, resistance.First electrode contact plunger
206 material may include tungsten (W).
As shown in Figure 1, first electrode 208a is set on above-mentioned first electrode contact plunger 206, and contact above-mentioned first
Electrode contact plunger 206.Above-mentioned first electrode 208a can be considered a hearth electrode 208a.Therefore, above-mentioned first electrode contact plunger
206 can be considered a hearth electrode contact plunger 206.As shown in Figure 1, having admixture 220 in first electrode 208.In the present invention
In embodiment, the material of first electrode 208a may include titanium nitride.In some other embodiments of the present invention, first electrode 208a
Material may include tantalum, titanium or said combination.It is evaporated in vacuo using electron beam or sputtering method forms first electrode 208a.It can also
During forming first electrode 208a, in forming multiple conductive layers on interlayer dielectric layer 204.In some embodiment of the invention,
The material of admixture 220 may include carbon, boron or said combination.The metal material for forming first electrode and admixture 220 can be made jointly
At a sputtering target material, using total depositing process (co-sputtering process), in the phase of sputtering sedimentation first electrode material layer
Between by admixture 220 sputter incorporation first electrode 208a in.In some other embodiments of the present invention, first electrode 208a is being formed
Later, using ion implantation technology, admixture 220 is mixed in first electrode 208a.
As shown in Figure 1, second electrode 212 is set to above above-mentioned first electrode 208a.Above-mentioned second electrode 212 can be considered
One top electrode 212.The material and generation type of above-mentioned second electrode 212 can the same or similar material in first electrode 208a and
Generation type.In some embodiment of the invention, can not have admixture in second electrode 212.In some other implementations of the present invention
In example, can also have in second electrode 212 and the same or similar admixture of admixture 220.The shape of second electrode 212 with admixture
It can the same or similar generation type in the first electrode 208a with admixture 220 at mode.
As shown in Figure 1, first electrode 208a has a thickness A 2 with a thickness A 1, second electrode 212.In the present invention one
In a little embodiments, the thickness A 1 of first electrode 208a can design the thickness A 2 identical or less than second electrode 212.
As shown in Figure 1, resistance transition layer 210 is set on the above-mentioned first electrode 208a with admixture 220, and it is located at upper
It states between first electrode 208a and second electrode 212.Resistance transition layer 210 contacts the above-mentioned first electrode with admixture 220
208a and second electrode 212.The material of resistance transition layer 210 may include hafnium oxide, aluminium oxide, chromium doping strontium titanates, chromium
The combination of the strontium zirconate of doping, zirconium dioxide membrane or in which two or more material.Using atomic layer deposition method
(ALD) resistance transition layer 210 is formed.
As shown in Figure 1, second electrode contact plunger 216 is set to above-mentioned 212 top of second electrode, it is disposed through above-mentioned
Interlayer dielectric layer 218 and compliance in the barrier laying 214 formed on the laminated 250a of above-mentioned metal-insulator-metal type, and
Contact above-mentioned second electrode 212.First electrode contact plunger 206 is disposed through above-mentioned interlayer dielectric layer 204, and contacts above-mentioned
First electrode 208a.Above-mentioned second electrode contact plunger 216 can be considered a top electrode contact plunger 216.Above-mentioned first electrode connects
Touching plug 206 and second electrode contact plunger 216 can have the same or similar material and generation type.
Fig. 2 shows the diagrammatic cross-section of RRAM device 500b.RRAM device 500b and RRAM device 500a do not exist together for,
The first electrode 208b of RRAM device 500b is a layered structure, may include a metal nitride layer 208b1, metal oxidation
A nitride layer 208b2 and metal nitride layer 208b3.As shown in Fig. 2, metal oxide layer 208b2 is set to metal nitride layer
Between 208b1,208b3, so that the metal nitride layer 208b3 contact resistance transition layer 210 of first electrode 208b, and make metal
Nitride layer 208b1 contacts first electrode contact plunger 206.In some embodiment of the invention, metal nitride layer 208b1,
The material of 208b3 may include titanium nitride, and the material of metal oxide layer 208b2 may include titanium oxide.As shown in Fig. 2, metal
Nitride layer 208b1 has a thickness T2 with a thickness T1, metal oxide layer 208b2, and metal nitride layer 208b3 has
There is a thickness T3.In some embodiment of the invention, thickness T1~T3 can design the thickness A 2 of smaller than second electrode 212.Gold
The overall thickness A1 for belonging to nitride layer 208b1,208b3 and metal oxide layer 208b2 can be designed identical or less than second electrode 212
Thickness A 2.In some other embodiments of the present invention, the metal nitride layer of first electrode 208b and metal oxide layer
There is no restriction for the number of plies, only resistance transition layer 210 and first electrode contact plunger 206 need to be made all to contact with metal nitride layer, and
The thickness of each layer of metal nitride layer is set to be smaller than the thickness A 2 of second electrode 212.
Fig. 3 shows the diagrammatic cross-section of RRAM device 500c.RRAM device 500c and RRAM device 500b do not exist together for,
There is admixture in the metal nitride layer 208c3 that the first electrode 208b of RRAM device 500c is contacted with resistance transition layer 210
220.In some embodiment of the invention, the material of metal nitride layer 208c3 may include titanium nitride.It is some other in the present invention
Can also have in embodiment, in metal nitride layer 208b1 and the same or similar admixture of admixture 220.As shown in figure 3, with electricity
The thickness T3 of the contact of resistance transition layer 210 and the metal nitride layer 208c3 with admixture 220 can be designed less than second electrode 212
Thickness A 2.Metal nitride layer 208b1, metal nitride layer 208c3 and metal oxide layer 208b2 with admixture 220
Overall thickness A1 can design be identical to or less than second electrode 212 thickness A 2.
Then, the manufacturing method that RRAM device 500a will be further illustrated using Fig. 1, Fig. 4 A, Fig. 4 B, Fig. 5, wherein scheming
4A, Fig. 4 B, Fig. 5 show the diagrammatic cross-section of the intervening process steps of resistor type non-volatile memory device.Firstly, providing such as
Semiconductor substrate 200 shown in FIG. 1, and RCA (Radio Corporation of America) cleaning process is carried out to it.
Later, using being deposited and patterned technique, in forming a circuit 202 as shown in Figure 1 on semiconductor substrate 200.Then, may be used
Utilize chemical vapour deposition technique or plasma enhanced type chemical vapour deposition technique, a comprehensive deposition interlayer dielectric as shown in Figure 1
Layer 204.Then, using the Patternized technique for example including photoetching process and anisotropic etching method, in interlayer dielectric layer 204
It is middle to form an opening, define the forming position of first (bottom) electrode contact plunger 206.Also, partial circuit 202 is understood from above-mentioned
It is exposed in opening.Then, using sputtering method, the barrier layer of such as titanium and titanium nitride is deposited in opening sidewalls, then at opening
The conductive material of such as tungsten is inserted in mouthful, then carries out the flatening process of such as chemical mechanical milling method, to remove interlayer dielectric
The extra conductive material in 205 top of top surface of layer 204, is inserted with the first (bottom) electrode contact for forming as shown in Figure 1 in opening
Plug 206.
Followed by a kind of generation type of Fig. 4 A first electrode material layer 308a for illustrating that there is admixture 220.Such as Fig. 4 A
It is shown, it will include the above structure of semiconductor substrate 200, circuit 202, interlayer dielectric layer 204 and first electrode contact plunger 206
It is placed on the microscope carrier 228 in a sputtering machine table cavity 226.In some embodiment of the invention, sputtering machine table cavity 226 also wraps
A sputtering target material 224 and a gas source 232 are included.Sputtering target material 224 can be made of a metal material 224a and admixture 224b.
In some embodiment of the invention, metal material 224a may include titanium, and admixture 224b may include carbon, boron or said combination.Such as
Shown in Fig. 4 A, gas source 232 during technique to provide a gas 234.During forming first electrode material layer 308a,
Gas 234 may include nitrogen.Then, using a sputtering technology 222 is carried out, in one first electricity of formation on interlayer dielectric layer 204
Pole material layer 308a.Since sputtering target material 224 is made jointly of metal material 224a and admixture 224b, so being sputtered
During technique 222, metal material 224a and admixture 224b can be total to plated deposition on interlayer dielectric layer 204 together, thus will form
First electrode material layer 308a with admixture 220.Therefore, sputtering technology 222 as shown in Figure 4 A can be described as depositing process altogether
(co-sputtering process)222。
Fig. 4 B is another generation type for the first electrode material layer 308a that explanation has admixture 220.Forming such as Fig. 1
Shown in after first electrode contact plunger 206, as shown in Figure 4 B, be evaporated in vacuo using electron beam or the deposition works such as sputtering method
Skill, in formation first electrode material layer 308a on interlayer dielectric layer 204.Then an ion implantation technology 233 is carried out, by admixture
In 220 incorporation first electrode material layer 308a.In some embodiment of the invention, as shown in Fig. 4 A, 4B with admixture 220
First electrode material layer 308a can be non-crystalline (amorphous phase).
Later, as shown in figure 5, using atomic layer deposition method (ALD) depositional mode, in first electrode material layer 308a
One resistance transition material layer 210a of upper growth.Resistance transition material layer 210a contact has the first electrode material layer of admixture 220
308a。
Then, it refer again to Fig. 5, be evaporated in vacuo using electron beam or the depositional modes such as sputtering method, Yu Shangshu resistance turn
A second electrode material layer 212a is formed on state material layer 210a.In some other embodiments of the present invention, it is possible to use as schemed
Depositing operation shown in depositing process 222 or Fig. 4 B and subsequent ion implantation technology 233 are total to shown in 4A to be formed with admixture
Second electrode material layer 212a.In some embodiment of the invention, the second electrode material with admixture 220 as shown in Figure 5
Bed of material 212a can be non-crystalline (amorphous phase).
Please continue to refer to Fig. 5, then, a photoetching and etch process can be carried out, on Yu Shangshu second electrode material layer 212a
Form hard exposure mask (hard mask) pattern 230.
Later, an etch process is carried out as a mask using hard mask pattern 230, removed not by hard mask pattern 230
Above-mentioned second electrode material layer 212a, resistance transition material layer 210a and the first electrode material layer 308a of covering, to form Fig. 1
The shown metal-insulator-metal type collectively formed by second electrode 212, resistance transition layer 210 and first electrode 208a is laminated
250a。
Later, it refer again to Fig. 1, using the film depositional mode of atomic layer deposition method, chemical vapour deposition technique, Yu Shang
It states compliance on the laminated 250a of metal-insulator-metal type and forms a barrier laying 214.In some embodiment of the invention, it hinders
Barrier laying 214 extends to not by the top surface 205 of the laminated 250a of the metal-insulator-metal type above-mentioned interlayer dielectric layer 204 covered
On, the material of barrier laying 214 may include silicon nitride.
Later, Fig. 1, recycling chemical vapour deposition technique or plasma enhanced type chemical vapour deposition technique be refer again to, entirely
Face property deposits an interlayer dielectric layer 218, and interlayer dielectric layer 218 covers above-mentioned barrier laying 214.Then, available for example to wrap
The Patternized technique for including photoetching process and anisotropic etching method forms one in interlayer dielectric layer 218 and barrier laying 214
Opening, defines the forming position of second electrode contact plunger 216, and expose partial second electrode 212 from above-mentioned opening
Come.Then, using sputtering method, the barrier layer of such as titanium and titanium nitride is deposited in opening sidewalls, is inserted for example in opening
The conductive material of tungsten, then the flatening process of such as chemical mechanical milling method is carried out, to remove the top surface of interlayer dielectric layer 218
The extra conductive material in 217 tops, to form second electrode contact plunger 216 in opening.Then, it can carry out that there is heat treatment
The last part technology (backend on line (BEOL)) of (thermal treatment) is connected to second electrode contact to be formed
Plug 216 or the internal connection-wire structure for being connected to other circuits.After above-mentioned technique, RRAM device 500a is completed.Through later
After segment process, the first electrode 208a and second electrode 212 of non-crystalline can be because the temperature effect crystallization of heat treatment become
The first electrode 208a and second electrode 212 for crystalline state of signing an undertaking.Also, the first electrode 208a for crystalline state of signing an undertaking can be because of admixture
220 exist and have smaller and more uniform crystallite dimension, and can promote first electrode (hearth electrode) 208a and resistance transition layer
The flatness at the interface 209 between 210.
In addition, the manufacturing method that will further illustrate RRAM device 500b using Fig. 2, Fig. 6, Fig. 7, Fig. 8 A, Fig. 9 A.Figure
6, Fig. 7, Fig. 8 A, Fig. 9 A show the diagrammatic cross-section of the intervening process steps of RRAM device 500b shown in Fig. 2.In above-mentioned schema
Each element if any with the same or similar part shown in Fig. 1, Fig. 4 A, Fig. 4 B, Fig. 5, then can refer to the related narration of front,
This does not do repeated explanation.
As shown in fig. 6, will include semiconductor substrate 200, circuit 202, interlayer dielectric layer 204 and first electrode contact plunger
206 above structure is placed on the microscope carrier 228 in a sputtering machine table cavity 226.In some embodiment of the invention, sputter
Platform cavity 226 further includes having a sputtering target material 236 and a gas source 232.Sputtering target material 236 can be made of a metal material.
In some embodiment of the invention, metal material may include titanium.As shown in fig. 6, gas source 232 during technique to provide one
Gas 234.During forming metal nitride materials layer 308b1, gas 234 may include nitrogen.Then, using progress one
Sputtering technology 238, in forming a metal nitride materials layer 308b1 on interlayer dielectric layer 204.In some other implementations of the present invention
In example, using depositional modes such as electron beam vacuum vapor deposition methods, metal nitride materials layer 308b1 is formed.
Then, it refer again to Fig. 7, be passed through a gas 234 ' in sputtering machine table cavity 226 using gas source 232, and
With identical sputtering target material 236 carry out a sputtering technology 240, in formed on metal nitride materials layer 308b1 a metal oxidation
Object material layer 308b2.In some embodiment of the invention, gas 234 ' is different from gas 234 (Fig. 6), and gas 234 ' may include
Oxygen.
Then, Fig. 8 A is please referred to, is passed through gas 234 again in sputtering machine table cavity 226 using gas source 232, and with
Identical sputtering target material 236 carries out a sputtering technology 242, in forming a metal nitride on layers of metal oxide materials 308b2
Material layer 308b3.In some embodiment of the invention, metal nitride materials layer 308b1, layers of metal oxide materials 308b2
It can be formed continuously in same board cavity 226 with metal nitride materials layer 308b3, and all can be non-crystalline
(amorphous phase)。
Later, as shown in Figure 9 A, using the depositional mode of atomic layer deposition method (ALD), in metal nitride materials layer
One electricity of growth on the layered structure that 308b1, layers of metal oxide materials 308b2 and metal nitride materials layer 308b3 are constituted
Hinder transition material layer 210a.Resistance transition material layer 210a contacts the metal nitride materials layer 308b3 of above-mentioned layered structure.Such as
Shown in Fig. 9 A, metal nitride materials layer 308b1 has a thickness T2 with a thickness T1, layers of metal oxide materials 308b2,
And metal nitride materials layer 308b3 has a thickness T3.In some embodiment of the invention, thickness T1~T3 may be designed as small
In the thickness A 2 of second electrode 212, in other embodiments of the present invention, thickness T1~T3 can be mutually the same or differing from each other.
Then, it refer again to Fig. 9 A, be evaporated in vacuo using electron beam or the depositional modes such as sputtering method, Yu Shangshu resistance turn
A second electrode material layer 212a is formed on state material layer 210a.In some embodiment of the invention, metal nitride materials layer
The overall thickness A1 for the layered structure that 308b1, layers of metal oxide materials 308b2 and metal nitride materials layer 308b3 are constituted can
Identical or less than the thickness A 2 of second electrode material layer 212a.In some other embodiments of the present invention, it is possible to use such as Fig. 4 A
Shown in altogether depositing operation and subsequent ion implantation technology 233 shown in depositing process 222 or Fig. 4 B formed with admixture
Second electrode material layer 212a.Alternatively, can also be used the sputtering technology 238,240,242 as shown in Fig. 6, Fig. 7, Fig. 8 A formed with
Metal nitride materials layer 308b1, layers of metal oxide materials 308b2 and metal nitride materials layer 308b3 are same or similar
Layered structure.In some embodiment of the invention, second electrode material layer 212a as shown in Figure 9 A can be non-crystalline
(amorphous phase)。
Please continue to refer to Fig. 9 A, then, a photoetching and etch process can be carried out, on Yu Shangshu second electrode material layer 212a
Form a hard mask pattern 230.Later, using hard mask pattern 230 as a mask, carry out an etch process, remove not by
Above-mentioned second electrode material layer 212a, resistance transition material layer 210a and the metal nitride that above-mentioned hard mask pattern 230 covers
The layered structure that material layer 308b1, layers of metal oxide materials 308b2 and metal nitride materials layer 308b3 are constituted, to be formed
By second electrode 212, resistance transition layer 210, first electrode 208b (including metal nitride layer 208b1, metal oxygen shown in Fig. 2
Compound layer 208b2 and metal nitride layer 208b3) the laminated 250b of metal-insulator-metal type that collectively forms.
Later, it refer again to Fig. 2, compliance forms barrier liner on the laminated 250b of Yu Shangshu metal-insulator-metal type
Layer 214.In some embodiment of the invention, the material to generation type of barrier laying 214 can refer to the related narration of front,
Repeated explanation is not done herein.
Later, Fig. 2, comprehensive one interlayer dielectric layer 218 of deposition be refer again to, interlayer dielectric layer 218 covers above-mentioned barrier
Laying 214.Then, second electrode contact plunger 216 is formed in the opening of interlayer dielectric layer 218.Above-mentioned interlayer dielectric layer
218 can refer to the related narration of front to the material of second electrode contact plunger 216 to generation type, do not do repetition herein and say
It is bright.Then, the last part technology (backend on line (BEOL)) with heat treatment (thermal treatment) can be carried out,
Second electrode contact plunger 216 is connected to formation or is connected to the internal connection-wire structure of other circuits.After above-mentioned technique,
Complete RRAM device 500b.After last part technology, the first electrode 208b and second electrode 212 of non-crystalline can be because of warm
The temperature effect crystallization of processing becomes the first electrode 208b and second electrode 212 of crystalline state of signing an undertaking.Also, the of crystalline state of signing an undertaking
One electrode 208 can be because the thickness T3 design of the metal nitride layer 208b3 contacted with resistance transition layer 210 be less than second electrode
212 thickness A 2, thus can have smaller and more uniform crystallite dimension after high-temperature technology recrystallizes, and can be promoted
The flatness at the interface 209 between one electrode (hearth electrode) 208b and resistance transition layer 210.
In addition, the manufacturing method that will further illustrate RRAM device 500c using Fig. 3, Fig. 6, Fig. 7, Fig. 8 B, Fig. 9 B.Figure
6, Fig. 7, Fig. 8 B, Fig. 9 B show the diagrammatic cross-section of the intervening process steps of RRAM device 500c shown in Fig. 3.In above-mentioned schema
Each element if any with the same or similar part shown in Fig. 1, Fig. 4 A, Fig. 4 B, Fig. 5, Fig. 6, Fig. 7, Fig. 8 A, Fig. 9 A, then can join
The related narration in face before examination, does not do repeated explanation herein.
After forming metal nitride materials layer 308b1 and layers of metal oxide materials 308b2 as shown in Figure 6,7,
Fig. 8 B is please referred to, is passed through gas 234 again in sputtering machine table cavity 226 using gas source 232, and splash with as shown in Figure 4 A
Material 224 of shooting at the target carries out a sputtering technology 244, in forming a metal nitride materials layer on layers of metal oxide materials 308b2
308c3.Since sputtering target material 224 is made jointly of metal material 224a and admixture 224b, so carrying out sputtering technology 244
Period, metal material 224a and admixture 224b can be total to plated deposition on layers of metal oxide materials 308b2 together, thus will form
Metal nitride materials layer 308c3 with admixture 220.In some embodiment of the invention, metal nitride materials layer
308b1, layers of metal oxide materials 308b2 and metal nitride materials layer 308c3 with admixture 220 can be in same board chambers
It is formed continuously in body 226, and all can be non-crystalline (amorphous phase).
Fig. 8 C is another generation type for the metal nitride materials layer 308c3 that explanation has admixture 220.It is being formed such as
It is as shown in Figure 8 C, heavy using electron beam vacuum evaporation or sputtering method etc. after first electrode contact plunger 206 shown in FIG. 1
Product technique, in formation metal nitride materials layer 308b1, layers of metal oxide materials 308b2 and metal on interlayer dielectric layer 204
Layer of nitride material 308c3.Then an ion implantation technology 246 is carried out, admixture 220 is mixed into metal nitride materials layer
In 308c3.In some embodiment of the invention, with the metal nitride materials layer of admixture 220 as shown in Fig. 8 B, 8C
308c3 can be non-crystalline (amorphous phase).
Later, as shown in Figure 9 B, in metal nitride materials layer 308b1, layers of metal oxide materials 308b2 and can have
A sequentially resistance transition material layer 210a and one on the layered structure that the metal nitride materials layer 308c3 of admixture 220 is constituted
Second electrode material layer 212a.Above-mentioned resistance transition material layer 210a contacts the metal in above-mentioned layered structure with admixture 220
Layer of nitride material 308c3.In some embodiment of the invention, resistance transition material layer 210a and a second electrode material layer
The material of 212a can refer to the related narration of front to generation type, not do repeated explanation herein.
As shown in Figure 9 B, metal nitride materials layer 308b1, layers of metal oxide materials 308b2 and with admixture 220
The thickness A 1 for the layered structure that metal nitride materials layer 308c3 is constituted can be identical to or less than second electrode material layer 212a's
Thickness A 2.In some other embodiments of the present invention, it is possible to use sink shown in total depositing process 222 or Fig. 4 B as shown in Figure 4 A
Technique and subsequent ion implantation technology 233 are accumulated to form the second electrode material layer 212a with admixture.Alternatively, can also be used
The sputtering technology 238,240,242 as shown in Fig. 6,7,8A is formed and metal nitride materials layer 308b1, metal oxide materials
Layer 308b2 and the same or similar layered structure of metal nitride materials layer 308b3.Alternatively, can also be used such as Fig. 6,7,8B institute
The sputtering technology 238,240,244 shown is formed and metal nitride materials layer 308b1, layers of metal oxide materials 308b2 and tool
There is the same or similar layered structure of metal nitride materials layer 308c3 of admixture 220.In some embodiment of the invention, such as
Second electrode material layer 212a shown in Fig. 9 B can be non-crystalline (amorphous phase).
Then, the generation type for defining metal-insulator-metal type (MIM) laminated 250c is illustrated using Fig. 9 B and Fig. 3.Such as
Shown in Fig. 9 B, then, a photoetching and etch process can be carried out, forms a hard exposure mask figure on Yu Shangshu second electrode material layer 212a
Case 230, to define the second electrode 212, resistance transition layer 210 and 208 area of first electrode that are subsequently formed and forming position.
Later, it refer again to Fig. 3, using above-mentioned hard mask pattern 230 shown in Fig. 9 B as a mask, carry out an etching
Technique, remove the above-mentioned second electrode material layer 212a, the resistance transition material layer 210a that are not covered by above-mentioned photoresist pattern 230 and
Metal nitride materials layer 308b1, layers of metal oxide materials 308b2 and metal nitride materials layer with admixture 220
The layered structure that 308c3 is constituted, to be formed shown in Fig. 3 by second electrode 212, resistance transition layer 210, first electrode 208c (packet
Include metal nitride layer 208b1, metal oxide layer 208b2 and the metal nitride materials layer 308c3 with admixture 220) altogether
With the laminated 250c of metal-insulator-metal type constituted.
Later, it refer again to Fig. 3, compliance forms barrier liner on the laminated 250c of Yu Shangshu metal-insulator-metal type
Layer 214.In some embodiment of the invention, the material to generation type of barrier laying 214 can refer to the related narration of front,
Repeated explanation is not done herein.
Later, Fig. 3, comprehensive one interlayer dielectric layer 218 of deposition be refer again to, interlayer dielectric layer 218 covers above-mentioned barrier
Laying 214.Then, second electrode contact plunger 216 is formed in the opening of interlayer dielectric layer 218.Above-mentioned interlayer dielectric layer
218 can refer to the related narration of front to the material of second electrode contact plunger 216 to generation type, do not do repetition herein and say
It is bright.Then, the last part technology with heat treatment can be carried out, second electrode contact plunger 216 is connected to formation or is connected to it
The internal connection-wire structure of his circuit.After above-mentioned technique, RRAM device 500c is completed.It is noncrystalline after last part technology
The first electrode 208c and second electrode 212 of state can be because the temperature effect crystallization of such as heat treatment become and sign an undertaking the first of crystalline state
Electrode 208c and second electrode 212.Also, the first electrode 208 of crystalline state of signing an undertaking can be because contact with resistance transition layer 210
Metal nitride materials layer 308c3 can be because admixture 220 exists, and the thickness T3 design of metal nitride materials layer 308c3 is small
In the thickness A 2 of second electrode 212, thus it can have smaller and more uniform crystallite dimension after high-temperature technology recrystallizes,
And the flatness at the interface 209 between first electrode (hearth electrode) 208c and resistance transition layer 210 can be promoted.
The embodiment of the invention provides a kind of resistor type non-volatile memory device and its manufacturing methods.By in bottom electricity
The modes such as incorporation admixture or reduction hearth electrode thickness, control the crystal grain size of hearth electrode, to promote final resistance-type in extremely
The flatness at the interface between the hearth electrode in non-volatile memory device structure and resistance transition layer.Electricity can thus be promoted
The reliability of resistive non-volatile memory device.
Although the present invention is exposed in embodiment, however, it is not to limit the invention, those skilled in the art,
It does not depart from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection scope of the present invention is when view power
Subject to sharp claimed range institute defender.
Claims (12)
1. a kind of resistor type non-volatile memory device characterized by comprising
One first electrode, wherein having an admixture in the first electrode；
One second electrode is set in the first electrode；And
One resistance transition layer, is set between the first electrode and the second electrode, wherein the one of the first electrode is thick
Degree is less than a thickness of the second electrode.
2. resistor type non-volatile memory device as described in claim 1, which is characterized in that the first electrode changes for one
Layer structure, comprising:
One first metal nitride layer；And
One metal oxide layer is located in first metal nitride layer.
3. resistor type non-volatile memory device as claimed in claim 2, which is characterized in that further include:
One second metal nitride layer is located on the metal oxide layer.
4. resistor type non-volatile memory device as claimed in claim 3, which is characterized in that wherein second metal nitrogen
There is the admixture, and second metal nitride layer contacts the resistance transition layer in compound layer.
5. a kind of resistor type non-volatile memory device characterized by comprising
One first electrode, wherein the first electrode is a layered structure, comprising:
One first metal nitride layer has a first thickness；And
One metal oxide layer has a second thickness, and is located in first metal nitride layer；
One second electrode is set in the first electrode, wherein the first thickness and the second thickness are smaller than described
One thickness of second electrode；And
One resistance transition layer, is set between the first electrode and the second electrode.
6. resistor type non-volatile memory device as claimed in claim 5, which is characterized in that further include:
One second metal nitride layer is located on the metal oxide layer, wherein second metal nitride layer has one
Third thickness.
7. resistor type non-volatile memory device as claimed in claim 6, which is characterized in that wherein the third thickness is small
In the thickness of the second electrode.
8. resistor type non-volatile memory device as claimed in claim 6, which is characterized in that wherein second metal nitrogen
There is an admixture, and second metal nitride layer contacts the resistance transition layer in compound layer.
9. a kind of manufacturing method of resistor type non-volatile memory device, characterized in that it comprises the following steps:
Semiconductor substrate is provided；
In forming a first electrode on the semiconductor substrate；
An admixture is adulterated in the first electrode；
In forming a resistance transition layer in the first electrode；And
In forming a second electrode on the resistance transition layer, wherein a thickness of the first electrode is less than the second electrode
A thickness.
10. the manufacturing method of resistor type non-volatile memory device as claimed in claim 9, which is characterized in that formed
The admixture is adulterated during the first electrode in the first electrode, and forming the first electrode includes by one first electricity
Pole material and the admixture carry out depositing process altogether as a sputtering target material together.
11. the manufacturing method of resistor type non-volatile memory device as claimed in claim 9, which is characterized in that formed
The admixture is adulterated in the first electrode after the first electrode, and the admixture packet is adulterated in the first electrode
It includes and carries out an ion implantation technology, admixture is injected in the first electrode.
12. the manufacturing method of resistor type non-volatile memory device as claimed in claim 9, which is characterized in that form institute
Stating first electrode includes:
A sputtering target material is placed in a sputtering machine table cavity；
The substrate is placed in the sputtering machine table cavity；
It is passed through a first gas in the sputtering machine table cavity, one first sputtering technology is carried out to the substrate, in described
A metal nitride layer is formed on substrate；And
It is passed through a second gas in the sputtering machine table cavity, one second sputtering technology is carried out to the substrate, in described
A metal oxide layer is formed in metal nitride layer.
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