CN105590866A

CN105590866A - Method for deciding individual die identifiers and multi-chip module device

Info

Publication number: CN105590866A
Application number: CN201410558275.7A
Authority: CN
Inventors: 陈毓明
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2014-10-20
Filing date: 2014-10-20
Publication date: 2016-05-18
Anticipated expiration: 2034-10-20
Also published as: CN105590866B

Abstract

The present invention provides a method for deciding individual die identifiers and a multi-chip module device. As for co-encapsulated memory grains adopted as a memory device, the die identifiers (IDs) of individual dies are decided based on the unique identifiers (UID) of the dies. An external controller starts an internal die ID (DID) judgment process; after a plurality of clock rate signals are decided by the UIDs of the dies, each die triggers signals at signal pins between the dies finally; and before the response of the signals of each die, each die distributes the ID of the die its own based on the number of signals triggered by the other dies. According to the method, before the response of the signals of each die, each die records the number of the signals triggered by the other dies, and the total number of signals on the signal pins can selectively decide the number of encapsulated dies.

Description

Determine method and the multi-wafer modular device of indivedual crystal grain identifiers

Technical field

The invention relates to a kind of multi-memory crystal grain (memorydie) of common encapsulation, and relate to especially a kind of method and multi-wafer modular device that determines indivedual crystal grain identifiers for the common multi-memory crystal grain encapsulating.

Background technology

It is common thing for various uses that two or more memory crystal grain are packaged in to an encapsulation. Crystal grain can be identical or different. Be to be partially or even wholly connected to each other at the indivedual interface crystal grain of part situation crystal grain, therefore need to use in order to difference the technology of the pin of encapsulation at different intergranules. When crystal grain is identical type, this problem can become especially severe.

The wafer of stacked memory crystal grain is selected pin to be used in and in crystal grain, is differentiated crystal grain. Be exposed in tables of data " S70FL256P256-MbitCMOS3.0VoltFlashMemorywith104-MHzSPIMul tiI/OBus " amendment the 5th edition of Fei Suo semiconductor limited company (SpansionInc.) on January 30th, 2013. Two identical 128Mb crystal grain are stacked on their other wafers and select to input the indivedual pins that are engaged to encapsulation to form flash memory device. So storage arrangement can be operating as at identical Serial Peripheral Interface (SPI) (SerialPeripheralInterface, be called for short SPI) the SPI device of two separation of bus, user selects the stacking crystal grain of (Chipselect) primary access twin crystal grain by indivedual wafers. Adversely, controller is required to provide and manages multiple/CS control signal. In addition, two or more wafers select the demand of pins to get rid of quaternary SPI and quaternary peripheral interface (QuadPeripheralInterface is called for short QPI) encapsulates applicable option as eight pins.

Memory crystal grain typically has during fabrication the unique identifier (UniqueIdentifier is called for short UID) of setting up, and is used for production control. An example of applicable UID is the combination of the X-Y coordinate of device numbering, flow process lot number, wafer number and crystal grain, thereby has guaranteed the uniqueness of UID. If peripheral control unit is learnt UID, so UID can be by general interface in order to identify a crystal grain and other crystal grain in encapsulation. Unfortunately, crystal grain interface is for after being connected to each other during manufacture, and indivedual UID may be inaccessible, thereby indivedual UID may be unknown for outside controller.

Technology in the stacked position of the programmable memory crystal grain of multiple grain storage arrangement after encapsulation is exposed in U.S. Patent Application Publication No. US2009/0085608, and its invention people is Alzheimer, is disclosed on April 2nd, 2009. Each crystal grain is extremely shared output jointly corresponding to the crystal grain identification data bit drive output signal of crystal grain. Each crystal grain also comprises arbitration (arbitration) circuit, and it produces the corresponding identification bit that does not match other crystal grain corresponding to the control signal of the identification bit of crystal grain. Control signal is according to the stacking fuse (stackenablefuse) that enables of particular result programming of arbitration.

Summary of the invention

The invention provides a kind of method and multi-wafer modular device that determines indivedual crystal grain identifiers.

One embodiment of the invention provide a kind of indivedual crystal grain identifier (DieIdentifier of decision, be called for short DID) method, the multiple common sealed storage device crystal grain that is applicable to have indivedual unique identifiers (UID), comprising: enable the common connection (commonconnection) between memory crystal grain; Unique identifier based on memory crystal grain is set up indivedual crystal grain selection criterions of described memory crystal grain; Synchronously memory crystal grain is carried out to timing action; And during the timing action of each memory crystal grain: determine when crystal grain selection criterion be while meeting the operation that timing moves; Produce corresponding to the signal in the common connection of being positioned at of deciding step; Before this generation step, monitoring is common connects, to increase crystal grain position (DiePosition is called for short DP) parameter in the time that common connection exists signal; And set up DP parameter as DID.

Another embodiment of the present invention provides a kind of multi-wafer modular device, comprise: multiple memory crystal grain, comprise respectively unique identifier (UID), crystal grain identifier (DID) control circuit, multiple interface pins and intercrystalline signal pin (inter-diesignalingpin); And encapsulation, it holds the described multiple memory crystal grain in multi-wafer model block configuration, and encapsulation has multiple encapsulation pins, encapsulation pin at least one of them be coupled to each memory crystal grain interface pins at least one of them, wherein each described memory crystal grain has memory addressing ability; Wherein each described DID control circuit comprises: signal circuit, is coupled to this intercrystalline signal pin; Counter circuit, is coupled to this signal circuit and is configured to start this signal circuit in the time there is several clock signal based on UID; And event counter, be coupled to intercrystalline signal pin and be configured to before there are several clock signals based on UID, the signal that is positioned at intercrystalline signal pin at each increases crystal grain position (DP) parameter while appearance.

Brief description of the drawings

Fig. 1 is the illustrative view of functional configuration of the embodiment of SPI flash memory multi-wafer device;

Fig. 2 is the illustrative view of functional configuration that any type has the embodiment of any type multi-wafer device of common sealed storage device crystal grain;

Fig. 3 is the structural representation with the SPI-NOR flash memory crystal grain of DID decision circuitry;

Fig. 4 is the flow chart that a DID judges flow process;

Fig. 5 is the flow chart that another DID judges flow process;

Fig. 6 is circuit structure diagram and the oscillogram that the DID of Fig. 5 judges flow process;

Fig. 7 is the flow chart that another DID judges flow process;

Fig. 8 is the planar side view that has stacked memory crystal grain and have the multi-wafer module of spacer body (spacer) at intergranule;

Fig. 9 is the planar side view with the multi-wafer module of the stacked memory crystal grain that uses crystal grain to stagger (staggering);

Figure 10 is the planar side view with the multi-wafer module of the stacked memory crystal grain of different size;

Figure 11 is the structural representation of the DID control circuit of another embodiment.

Description of reference numerals:

100: Multi-chip encapsulating device;

110,120,130,140,820,840,920,940:SPI flash memory crystal grain;

150:SPI encapsulates pin;

200: Multi-chip encapsulating device;

210,220,230,240,1020,1040: crystal grain;

250: encapsulation pin;

260: inner connection;

300:NOR flash memory crystal grain;

310: instruction process and control circuit;

320:NOR flash memory array;

322: high-pressure generator;

323: page address latch/counter;

324: write protection logical AND column decoder;

326: byte address latch/counter;

328: row decoder and page buffer;

330: register;

340,370,610,620,630,640:DID control circuit;

342: counter;

344: comparator;

346,376: connector;

348,374: watch-dog;

350,612,622,632,642: drawing upwardly device;

360: transistor;

372: can be preloaded into counter;

378:NAND door;

400～420,500～520,700～740: flow process;

616,626,636,646: weld pad;

614,624,634,644: pull device;

800,900,1000:SPI flash memory device;

810,910,1010: packaging body;

830: spacer body;

861,862,863,864,980,990,1021,1022,1041: wire;

850,950,1050: adhesive;

860,960,1060: cooling pad;

870,880,970,1070,1080: lead-in wire;

930,1030: material;

/ CS ,/HOLD, IO3 ,/WP, IO2, DO, IO1, DI, IO0: pin;

BP: weld pad;

CLK: clock pulse;

CNT: counting;

ENABLE: enable;

UID: unique identifier;

DP: crystal grain position;

GND: ground connection;

INPUT: input;

OUTPUT: output;

PDC: encapsulation crystal grain counting;

PRELOAD: be preloaded into;

VCC, Vcc: power supply;

Vss: negative supply voltage.

Detailed description of the invention

Embodiment described herein concentrates on for Serial Peripheral Interface (SPI) flash memory device and determines unique crystal grain identifier, wherein any amount of SPI flash memory crystal grain can be used in for example multi-wafer module (MultipleChipModule of multi-die package technology of any requirement, be called for short MCM) be encapsulated as in the lump single device, maintaining under the advantage of SPI interface, to realize for example every bit low cost (lowper-bitcost) of different performances, high density storage, to random access memory (RandomAccessMemory, being called for short RAM) code covers (codeshadowing), with quick arbitrary access in one of them or the combinations thereof of carrying out (executeinplace) application. but, technology described herein can be used for arbitrary combination of memory crystal grain, no matter whether identical, it has completely or partially common connecting interface, and the multi-die package technology that can be used in any requirement is encapsulated as single device in the lump, comprise for example stacking, be arranged on same layer (mountedin-plane) miniature printed circuit board or ceramic substrate, be arranged on multilayer (multi-layer) laminated printed circuit boards or ceramic substrate, use thin film technique is deposited on substrate (basesubstrate) etc.

Fig. 1 is the illustrative view of functional configuration of the embodiment of SPI flash memory multi-wafer device; Concrete, Fig. 1 is the Multi-chip encapsulating device 100 that has a group four identical SPI flash memory crystal grain 110, SPI flash memory crystal grain 120, SPI flash memory crystal grain 130, SPI flash memory crystal grain 140 and be jointly connected to one group of SPI encapsulation pin 150, and wherein said SPI flash memory crystal grain 110, SPI flash memory crystal grain 120, SPI flash memory crystal grain 130, SPI flash memory crystal grain 140 have identical SPI interface. One of them of the pin of the SPI interface of indivedual SPI memory crystal grain 110, SPI flash memory crystal grain 120, SPI flash memory crystal grain 130, SPI flash memory crystal grain 140 used technology described herein can be used for delivering a letter (signaling). Fig. 2 is the illustrative view of functional configuration that any type has the embodiment of any type multi-wafer device of common sealed storage device crystal grain; Concrete, Figure 2 shows that Multi-chip encapsulating device 200 has the crystal grain 210 of four a groups, crystal grain 220, crystal grain 230, crystal grain 240, described crystal grain 210, crystal grain 220, crystal grain 230, crystal grain 240 can have maybe can not have arbitrary type or the identical interface of more than one type, but have part (illustrating) or all (not shown) be jointly connected to one group of encapsulation pin 250. Crystal grain can be completely different or identical, or part can be difference and part can be identical. For example, use technology described herein, a separation common but can be used for delivering a letter between crystal grain 210, crystal grain 220, crystal grain 230, crystal grain 240 in inner connection 260 completely. Or, be jointly connected to encapsulation pin one of them can use technology described herein to do delivering a letter of intergranule.

Technology described herein makes every crystal grain in two or more common encapsulation crystal grain, can determine unique crystal grain identifier (DieIdentifier with respect to the crystal grain in last crystal grain or encapsulation, be called for short DID), if there is requirement, also can be in order to the crystal grain sum of finding to participate in decision. no matter the interface section of the address pin of crystal grain or address configurable (address-configurable) pin ground or be fully jointly connected to encapsulation pin, this decision all can produce. each crystal grain has the unique identifier (UID) of any type, for example, the identifier of setting up in processing early, this identifier is specified for the production of control. peripheral control unit transmits specific instruction, and for example, for determining DID instruction, initial internal crystal grain ID judges that flow process requires unique crystal grain ID at common encapsulation crystal grain. each crystal grain has for judge the signal pin that flow process and other crystal grain are delivered a letter at crystal grain ID. signal pin can be one of them of interface pins, interface pins can jointly be connected to other similar interface pins one or more in other one or more crystal grain to corresponding encapsulation pin, or be not a part for external interface pin, therefore can not be connected with any encapsulation pin, but instead be uniquely or be provided as together with other functions crystal grain ID determine, when crystal grain receives clock pulse, and determined the number of clock signal by its UID after, each crystal grain finally triggers (assert) signal at its intercrystalline signal pin, and (if there is above-mentioned situation in the crystal grain ID of the signal number assignment based on triggering self, by other crystal grain trigger be have precedence over self signal respond). each crystal grain records the signal number being triggered by other crystal grain, and selectively, by the encapsulation number of die of the signal sum determination device on signal pin.

Fig. 3 is the structural representation with the SPI-NOR flash memory crystal grain of DID decision circuitry, for example NOR flash memory crystal grain 300, it comprises NOR (or non-) flash memory array 320 and interlock circuit for example high-pressure generator 322, page address latch/counter 323, write protection logical AND column decoder 324, byte address latch/counter 326 and row decoder and page buffer 328. shown in type of memory and interlock circuit be to illustrate, and can be used in required any type of memory and interlock circuit. instruction process and control circuit 310 are processed the different instruction receiving, and for example, SPI interface, comprises clock pulse CLK, pin/CS, pin/HOLD or pin IO3, pin/WP or pin IO2, pin DO or pin IO1 and pin DI or pin IO0. although crystal grain ID judgment technology can be described at the NOR flash memory crystal grain 300 that below uses SPI interface, technology is to be applicable to the encapsulation that all types of memory crystal grain are the whole of any type or local shared interface (commoninterface), comprise mixing of different types memory crystal grain for example NOR, NAND (with non-), resistance-type RAM (ResistiveRAM, be called for short ReRAM) and EEPROM (ElectronicallyErasableProgrammableReadOnlyMemory is called for short EEPROM). in single bit and many bits SPI, applicable NOR and nand memory and extraneous information can be referring to giving the 7th of the people such as Jigour on July 7th, 2009, 558, the open case of No. 900 United States Patent (USP)s and Huabang Electronics Co., Ltd, comprise the open case W25Q256FV of Huabang Electronics Co., Ltd's on October 16th, 2013: " spiflash3V256M-BitSerialFlashMemorywithDual/QuadSPI&QPI " version F, open case W25N01GV with Huabang Electronics Co., Ltd's on November 26th, 2013: " spiflash3V1G-BitSerialSLCNANDFlashMemorywithDual/QuadSPI " preliminary version B, above patent and open case in full way of reference are incorporated to herein.

Crystal grain ID (DID) control circuit 340 that is shown in Fig. 3 separates to know demonstration from instruction process with control circuit 310, but also can require DID control circuit to be integrated into instruction process and control circuit 310. DID control circuit 340 comprises and enables ENABLE input, clock pulse CLK input, unique identifier UID input, signal pin input INPUT, signal pin output OUTPUT, the output of crystal grain position DP parameter and encapsulation crystal grain counting (PackagedDieCount is called for short PDC) parameter output. Signal pin is connected to signal circuit, and it can be, for example, and any applicable drop-down or pull-up circuit. Pull-down circuit can be as shown in Figure 3, the weak pull-up device 350 of its use for example transistor, diode, resistance and like, VCC is provided to weak pull-up device 350, and pull device, for example can be metal-oxide half field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistor is called for short MOSFET) transistor 360, its source electrode is connected to input INPUT, drain electrode is connected to ground connection GND or negative supply voltage Vss, and grid is connected to output OUTPUT. Particular value depends on the design details of crystal grain, and weak pull-up device 350 for example can be resistance, and its resistance can be 3M Ω under 3VVCC, and mosfet transistor 360 for example can be N type. In order to prevent disturbing in the general operation of the interface pins jointly connecting, weak pull-up device 350 is preferably only judging that at inner DID flow process works. Drawing upwardly device (not shown) can comprise that strong pull-up device is series at weak pull-down device.

The UID input of DID control circuit 340 can receive UID bit from register, can be directly (not shown) or indirectly via instruction process and control circuit 310, and is generally to build on early time treatment. For example, UID bit can receive from the read-only register or the read/write register that are positioned at register 330. UID bit and the counting CNT comparison producing at counter, it can be by the timing of outside clock pulse CLK signal. Counter 342 can start counting in the time receiving enable signal, and increases counting at each clock pulse CLK signal. The output of comparator provides grid to transistor 360 with pulldown signal pin, in order to other crystal grain of delivering a letter corresponding to the particular kind of relationship between the counting CNT being detected by comparator 344 and UID.

348 monitoring input INPUT are drop-down with detection signal pin for watch-dog, for determining DP and PDC. At some embodiment, watch-dog 348 also can be by connector 346 (shown in dotted line) monitoring comparative result, for determining DP.

Figure 11 is the structural representation of the DID control circuit of another embodiment; As shown in figure 11, DID control circuit 370, comprises and is preloaded into PRELOAD input, clock pulse CLK input, unique identifier UID input, signal pin input INPUT, signal pin output OUTPUT, the output of crystal grain position DP parameter and the output of encapsulation crystal grain counting PDC parameter. Signal pin is connected to any applicable weak pull-up device 350 and any applicable pull device, and for example transistor 360 has source electrode and is connected to input INPUT, and drain electrode is connected to ground connection GND or negative supply voltage Vss, and grid is connected to output OUTPUT. UID bit is preloaded into being preloaded into counter 372, and it can be upwards counting or downwards counting. Can be preloaded into counter 372 can be by the timing of outside clock pulse CLK signal. Being stored in the count value that can be preloaded into counter 372 and being by applicable holding wire provides to any applicable combinational logic circuit for detection of the condition predetermining, for example to NAND door 378 to detect zero count. The grid that the output of NAND door 378 is supplied to transistor 360 is with when reaching the count value pulldown signal pin predetermining, in order to other crystal grain of delivering a letter.

374 monitoring input INPUT are drop-down with detection signal pin position for watch-dog, in order to determine DP and PDC. At some embodiment, watch-dog 374 also can be by connector 346 (shown in dotted line) monitoring comparative result, for determining DP.

DID control circuit 340 and DID control circuit 370 can, by any applicable hardware, software, firmware or any combinations thereof, comprise as the mode of state machine (statemachine) and realizing.

Fig. 4 is the flow chart that a DID judges flow process, for example: DID control circuit 340, DID control circuit 370. Receiving decision DID instruction (flow process 400), for example it can be the form of two byte operation codes (opcode), initializes any at the counter of DID control circuit and the element of other states (flow process 402). When being ready to provide crystal grain ID to the specific die determining based on specific die UID (flow process 404 is), between the wafer of the signal pin of crystal grain, the signal of (inter-chip) is triggered (flow process 406) to notify all common encapsulation crystal grain. In the time that signal is present in signal pin (flow process 408), signal pin is also monitored in order to detect. If so signal (flow process 408 is no) do not detected, DID control circuit is advanced (advanced) state (flow process 416) and repeats (flow process 418 is no) or stop (flow process 418 is) flow process. If so signal is detected (flow process 408 is) and not yet meets UID crystal grain selection criterion (flow process 410 is no), increase DP parameter and PDC parameter (flow process 412). If so signal is detected (flow process 408 is) and has met UID crystal grain selection criterion (flow process 410 is), only have PDC parameter to increase (flow process 414). Although in schematic flow, if the signal of triggering signal pin, DID control circuit does not increase DP, when UID crystal grain selection criterion meets, DP can increase (shortly past flow process 404 be after), rely on the crystal grain ID of the first crystal grain whether to want to become 0 or 1. DID control circuit is that advanced state (flow process 416) and flow process can be repetition (flow process 418 is no) or stop (flow process 418 is).

Fig. 5 is the flow chart that another DID judges flow process, and Fig. 6 is circuit structure diagram and oscillogram that the DID of Fig. 5 judges flow process. Inner DID judges flow process 500 usage count CNT parameters, crystal grain position DP parameter and encapsulation crystal grain counting PDC parameter, and above-mentioned counting CNT parameter, crystal grain position DP parameter and encapsulation crystal grain counting PDC parameter are set to 0 (flow process 502) at first. PDC is selectable, but in some flow process for example from the bending pitch of the laps of last crystal grain (wrap-around) to the first crystal grain the data of sequence read can be very useful. The relatively UID (flow process 504) of CNT crystal grain. If mate (match), drop-down its signal pin of crystal grain (flow process 506), therefore delivers a letter to other crystal grain of common encapsulation, represents the crystal grain ID of a crystal grain that has determined common encapsulation. In addition signal pin is without being interrupted. Flow process continues pilot signal pin pull-down state (flow process 508). If signal pin not by drop-down, represents do not have crystal grain ID to be determined, CNT increases (flow process 510) and repeats flow process (flow process 518 is not) until finish (flow process 518 be). If signal pin is by drop-down, UID compares CNT (flow process 512) again, or in the time that CNT=UID can read (not shown), there is the element of state (stateful) to be set, to determine whether specific die has determined its crystal grain ID. If UID is greater than CNT, specific die not yet determines its crystal grain ID, and therefore DP and PDC are the same with CNT increases (flow process 516). But if UID is not more than CNT, specific die has determined its crystal grain ID, therefore DP can not increase, although PDC and CNT still continue to increase (flow process 514).

Fig. 6 shows that four DID control circuits 610, DID control circuit 620, DID control circuit 630, DID control circuit 640 are coupled to four indivedual weld pads (pad) weld pad 616, weld pad 626, weld pad 636, the weld pad 646 at indivedual crystal grain. Weld pad 616, weld pad 626, weld pad 636, weld pad 646 for example engage (wirebonded) together with wire. Each weld pad 616, weld pad 626, weld pad 636, weld pad 646 have respectively above-mentioned drawing upwardly device 612, drawing upwardly device 622, drawing upwardly device 632, drawing upwardly device 642 and pull device 614, pull device 624, pull device 634, the pull device 644 of connection, for example, pull device can be transistor. Drawing upwardly device 612, drawing upwardly device 622, drawing upwardly device 632, drawing upwardly device 642 are coupled to power Vcc. Four DID control circuits 610, DID control circuit 620, DID control circuit 630, DID control circuits 640 are provided indivedual UID, for example, have respectively value 99,1,210 and 12. For all four DID control circuits 610, DID control circuit 620, DID control circuit 630, DID control circuit 640, counting CNT waveform can be identical, and similarly all crystal grain can be synchronized to common clock pulse. At counting, CNT is under the first count value, and DID control circuit 620 is that first mates its UID, and drop-down its weld pad 626, makes other DID control circuits 610, DID control circuit 630, DID control circuit 640 increase their indivedual DP parameters as response. The DP of DID control circuit 620 remains on when the initial value that coupling detected, specifically for " 0 ". When CNT is the 12 count value, DID control circuit 640 is next its UID of coupling, and drop-down its weld pad 646, makes DID control circuit 610, DID control circuit 630 increase their indivedual DP parameters as response. In the time coupling being detected, the DP of DID control circuit 640 remains on it increases numerical value once, specifically for " 1 ". When CNT is the 99 count value, DID control circuit 610 is next its UID of coupling, and drop-down its weld pad 616, and therefore DID control circuit 630 increases its DP parameter as response. In the time coupling being detected, the DP of DID control circuit 610 remains on it increases the numerical value of secondary, i.e. " 2 ". When CNT is the 210 count value, DID control circuit 630 is next its UID of coupling, and drop-down its weld pad 636. In the time coupling being detected, the DP of DID control circuit 630 remains on its numerical value that increases by three times, i.e. " 3 ". Fig. 6 also illustrate PDC corresponding to first, the 12, the 99, the increase of the 210 count value. In the time that flow process 500 finishes, each DID control circuit 610, DID control circuit 620, DID control circuit 630, DID control circuit 640 have determined DP parameter, it can be stored in read/write register (for example, register 330 (Fig. 3)) as crystal grain ID, and determined PDC parameter can be stored in read/write register. The BP of Fig. 6 is weld pad (BondingPad).

Determine that flow process 500 can be finished by several means. For example, in the time that clock pulse loop reaches predefined number or makes zero, the decision flow process in each crystal grain finishes. Lift again another example, each crystal grain can be by the crystal grain quantity programme in advance (pre-programmed) that participates in determining, or by the parameter that provides the crystal grain quantity that participates in determining to be used as determining to guide (DeterminationInstruction), and in the time that reaching this numeral, ends by event counter to determine flow process.

Fig. 7 is the flow chart that another DID judges flow process. When clock pulse CLK starts, enable signal is received by crystal grain ID control circuit, and as response, crystal grain ID control circuit is set count parameter " CNT ", crystal grain ID parameter " DID " and encapsulation crystal grain count parameter " PDC " to zero (flow process 702). At the relatively UID (flow process 704) of crystal grain of next clock pulse CNT. If coupling (flow process 704 no) do not detected, the state of detection signal pin (flow process 710). If signal pin is not by drop-down (flow process 710 no), represent that there is no jointly to encapsulate crystal grain has the UID meeting, increase (flow process 714) at next clock pulse CNT, and get back to comparison CNT and UID (flow process 704) in the flow process of next clock pulse. If signal pin is by drop-down (flow process 710 be), represent other crystal grain except having the specific die of mating UID, DP and PDC increase (flow process 712), and CNT increases (flow process 714) at next clock pulse, and flow process is got back at relatively CNT and UID (flow process 704) of next clock pulse. Get back to flow process 704, if matching detection (flow process 704 be) detected, the output OUTPUT of comparator be triggered therefore signal pin by drop-down (flow process 720) and in the end DP increase (flow process 722). If situation needs, the crystal grain of pulldown signal pin does not need oneself to count (that is to say, counting can be started from scratch if situation needs DP) in the time setting DP parameter, can omit flow process 722. Then, the state of detection signal pin (flow process 730). If signal pin is by drop-down (flow process 730 be), PDC increases (flow process 732). In two cases, CNT can increase (flow process 734) and make the judgement (flow process 736) whether CNT reaches its numerical value. Flow process 700 can finish (flow process 740) or return to pilot signal pin to monitor drop-down (flow process 730) of other crystal grain.

As following, the variation of these flow processs and other similar algorithms can be used for only using a signal to connect to determine crystal grain ID.

Judgement flow process described herein is particularly conducive to for stacking and be encapsulated in the SPI flash memory crystal grain of eight pins encapsulation. The whole SPI agreements that comprise quaternary SPI can be used so eight pin encapsulation to realize, and its signal pin can be one of them of SPI interface pins, or the special pin providing at crystal grain is provided, and it is not connected to any encapsulation pin.

By stacking the low-density crystal grain of same type be one of them example of the present invention to form highdensity serial flash memory device. the capacity of single crystal grain is 256Mb, for example, the serial flash memory crystal grain of two same types can be stacking to realize 512Mb (2x256Mb) device, and the serial flash memory crystal grain of four same types can be stacking to realize 1Gb (4x256Mb) device. the example of SPI-NOR flash memory crystal grain application type is the type that is used in the product type W25Q256FV of Huabang Electronics Co., Ltd, open case W25Q256FV referring to Huabang Electronics Co., Ltd's on October 16th, 2013: " spiflash3V256M-BitSerialFlashMemorywithDual/QuadSPI&QPI " version F, more than openly case in full way of reference be incorporated to herein, and the disclosure case can suitably be revised to comprise crystal grain ID decision circuitry, software/firmware, instruction and can process crystal grain and select the control logic of indicating. also can be used for the other types of SPI flash memory crystal grain, for example four stacking SPI-NAND flash memory crystal grain is for example for the type of the product type W25N01GV of Huabang Electronics Co., Ltd, open case W25N01GV referring to Huabang Electronics Co., Ltd's on November 26th, 2013: " spiflash3V1G-BitSerialSLCNANDFlashMemorywithDual/QuadSPI " preliminary amendment B, more than openly case in full way of reference be incorporated to herein, and the disclosure case can suitably be revised to comprise crystal grain ID decision circuitry, software/firmware, instruction and the control logic that can process crystal grain selection instruction. also can use SPI-NOR and the SPI-NAND flash memory crystal grain of other types, as desired. minimum two SPI flash memory crystal grain are stacking just its advantage, and more generally, the present invention can be used for any quantity. although the n power of use 2 is easily, the quantity of SPI flash memory crystal grain is not defined as 2 n power.

In addition, dissimilar flash memory crystal grain can stackingly have to realize single storage arrangement the unique combination that is applicable to application-specific performance. Amendment especially (specially-modify) the SPI-NAND type flash memory of SPI-NOR type flash memory and part type is applicable to code application examples and covers (codeshadowing) as carried out (execute-in-place) and code, but SPI-NAND type flash memory is generally applicable to high density data storage. The flash memory crystal grain of two types can be stacked in an encapsulation so that two kinds of performances to be provided. The size of the memory array of multiple crystal grain can be identical or different, or can be that part is identical and part is different. Stacking and the performance of NOR crystal grain and NAND crystal grain strengthens the further information of (performance-enhanced), be illustrated in U.S. Patent Application Publication No. US2012/0084491, the people such as its invention people is EungjoonPark, are disclosed on April 5th, 2012. More than openly case in full way of reference be incorporated to herein, and the disclosure case can suitably be revised to comprise crystal grain ID decision circuitry, software/firmware, instruction and can process crystal grain and select the control logic of indicating.

As used herein, term " memory crystal grain " comprises the memory array of any single type or multiple types and the integrated circuit crystal grain of a group interface pin, wherein any single type or polytype memory array can be the combination of NOR, NAND, ReRAM, EEPROM and any the above-mentioned type, and a group interface pin comprises that one or more pin is for memory addressing and data. Interface protocol comprises SPI, internal integrated circuit (I2C), three line serials (3-Wireserial), comprise single bit and many bit serials interface protocol and parallel etc. The major function of memory crystal grain is the crystal grain of data storage.

As used herein, term " SPI flash memory crystal grain " comprises any single type or polytype flash memory array and meets the integrated circuit crystal grain of a group interface pin of SPI agreement.

As used herein, term " pin " refers to be electrically connected in order to outside the interface element of the electric conductivity of serial flash memory crystal grain, no matter it is a contact on crystal grain, as weld pad, or one be embedded in the encapsulation contact of upper (comprising the contact that is placed in hidden my place), swash of wave contacts etched (flushcontacts) and outstanding contact (projectingcontacts) for example outstanding (prong) and BGA ball (BallGridArrayball is called for short BGAball) etc.

As used herein, term " SPI-elasticity (SPI-compliant) pin " refers to conform to a group interface pin of SPI agreement. According to SPI agreement, six pin configurations can be single SPI, two SPI, quaternary SPI and quaternary peripheral interface (QuadPeripheralInterface, be called for short QPI) (be also referred to as serial quaternary interface (SerialQuadInterface), or " SQI "), and comprise single bit or the instruction of many bits and/or address input and single bit or multi-bit data output, although configurability may be limited by the subclass of any demand of above-mentioned form. Six pins provide wafer selection/CS, clock pulse CLK, configurable pin (configurablepin) DI (IO0), configurable pin DO (IO1), configurable pin/WP (IO2) and configurable pin/HOLD (IO3). In single bit SPI operation, configurable pin can be used as data and inputs pin DI, data output connecting pin DO (or single pin (singlepin) DIO is configurable as input and output), reverse (bar) write protection pin/WP and oppositely keep pin/HOLD. For two SPI, configurable pin can be used as I/O pin IO0, I/O pin IO1, write protection pin/WP and keeps pin/HOLD. For quaternary SPI and QPI, configurable pin can be used as I/O pin IO0, I/O pin IO1, I/O pin IO2 and I/O pin IO3.

At an embodiment, 2 or 4 SPI flash memory crystal grain, there are respectively six pins in accordance with SPI agreement, except having two pins respectively as power supply (VCC) and ground connection (GND), described 2 or 4 SPI flash memory crystal grain encapsulate in the lump as the mode of Fig. 8 to Figure 10. So stacking and jointly encapsulate SPI flash memory crystal grain following benefit can be provided: (a) multiple pileup SPI flash memory crystal grain has single entities (physical) pin/CS; (b) eight pin encapsulation can be implemented quaternary SPI operation; (c) some SPI operations (concurrent) execution simultaneously; (d) existing SPI flash memory crystal grain only need to make less amendment; (e) be applicable to typical multi-die package technology; And (f) heterogeneous (heterogeneous) SPI flash memory crystal grain can be stacking to reach the object of many performances and multi-effect. Use the SPI flash memory device of so stacking SPI flash memory crystal grain can be compatible with traditional flash memory instructions group, and increased by any applicable " crystal grain selection " instruction. Schematically crystal grain selection instruction can be the two byte hexadecimal operation codes (opcode) that adopted by eight bit crystal grain ID. Although the amount of bits needing is to be determined by the stackable maximum of SPI flash memory device crystal grain of supporting, and when four stacked dies of as many as, two bits are enough, eight bits are to retain to crystal grain ID, and therefore crystal grain ID can end at byte boundary (byteboundary) and this crystal grain ID usually used as memory instructions.

Crystal grain selection instruction may operate at following manner, to select any other SPI flash memory crystal grain in multiple grain stacked package. Crystal grain selection instruction is distributed to unique crystal grain ID of SPI flash memory device and specific die to the access of demand by controller (not shown). All stacked dies are corresponding to crystal grain selection instruction. The crystal grain identifier match of crystal grain can be corresponding to whole SPI instruction set in the crystal grain ID of crystal grain selection instruction content (argument). The crystal grain identifier of other crystal grain does not match the crystal grain ID argument of crystal grain crystal grain selection instruction can be corresponding to the subclass of SPI instruction group, referring to closing as general (Universal) subset of instructions herein, otherwise do not correspond to SPI instruction set (set). If the support that the operation of (concurrent) occurs is had to demand, any current ongoing built-in function of the SPI order (command) of unselected crystal grain and the sustainable execution of control logic simultaneously. This performance can design into the control logic of SPI instruction and each stacking SPI flash memory crystal grain. Schematically crystal grain selection instruction is stacking and operate the Application No. 14/194 that is described in application on February 28th, 2014 of stacking flash memory crystal grain with another viewpoint, 248, denomination of invention is " StackedDieFlashMemoryDevicewithSerialPeripheralInterface ", invention people is HuiChen and TengSu (agent's label No.1770.035.US1N), and above application case in full way of reference is incorporated to herein.

Although stacking SPI flash memory crystal grain can be arranged at the encapsulation with extra pin, although and technology described in this patent document can utilize the technology of extra pin to be combined with other, make can carry out the stacking of multiple SPI flash memory crystal grain in simple and very small-sized pin position (footprint) eight pins encapsulation. Eight pin encapsulation are for example small outline integrated circuit (SmallOutlineIntegratedCircuit, be called for short SOIC) type, and very thin little profile is without lead-in wire (VeryVeryThinSmallOutlineNoLead, be called for short WSON) type, because eight pins are encapsulated in the small-sized pin position of system printed circuit board layout, therefore keep the popular selection of serial flash memory device.

Fig. 8 is the planar side view that has stacked memory crystal grain and have the multi-wafer module of spacer body (spacer) at intergranule; Concrete, Fig. 8 is the planar side view that eight pin WSON type SPI flash memory devices 800 comprise two stacking SPI flash memory crystal grain 820, SPI flash memory crystal grain 840 in packaging body 810. Can be used in any applicable Stack Technology, SPI flash memory device 800 uses spacer body (spacer) 830 to guarantee there are enough spaces in the bottom surface of SPI flash memory crystal grain 820 and between the wire of SPI flash memory crystal grain 840 end faces and bonding wire (for example, as wire 863, wire 864 and the bonding wire that is associated). Spacer body can be any applicable type, is schematically the material of end face and the bottom surface solid that is bonding plane, or viscous adhesive (viscouscement) or other engage material. SPI flash memory crystal grain 840 uses any applicable technology, and for example, adhesive 850 or other joint materials, be attached to cooling pad 860. SPI flash memory crystal grain 820 wires are engaged to the difference lead-in wire (for example, wire 861, wire 862, wire 863, wire 864 and the bonding wire that is associated to going between 870, wire 880) of lead frame (leadframe). The difference lead-in wire of lead frame, for example, for lead-in wire 870, lead-in wire 880, expose to provide through packaging body 810 weld pad that is connected to external circuit to the open air. Although illustrative bonding wire is to manufacture from crystal grain to lead-in wire, or bonding wire also can be from crystal grain to crystal grain, and then also can be from bottom die to lead-in wire. Engage although be illustrated as wire, any intergranule can use any other applicable joining technique, and for example, via replaces.

Fig. 9 is the planar side view with the multi-wafer module of the stacked memory crystal grain that uses crystal grain to stagger (staggering); Concrete, Fig. 9 is eight pin WSON type SPI flash memory devices 900 comprise two stacking SPI flash memory crystal grain 920, SPI flash memory crystal grain 940 planar side view at packaging body 910. SPI flash memory device 900 uses crystal grain migration technology to avoid SPI flash memory crystal grain 920 bottom surfaces and for example, in the interference between the wire of the end face of SPI flash memory crystal grain 940 and bonding wire (wire 990 and the bonding wire being associated). Using any applicable material 930, for example, is the material of adhesive or end face and the bottom surface solid that is bonding plane, to guarantee the stacking of SPI flash memory crystal grain 920, SPI flash memory crystal grain 940. SPI flash memory crystal grain 940 uses any applicable technology, and for example, adhesive 950 or other joint materials, be attached to cooling pad 960. SPI flash memory crystal grain 920, SPI flash memory crystal grain 940 wires are engaged to the difference lead-in wire (schematically, wire 980, wire 990 and the bonding wire being associated and lead-in wire 970) of lead frame. The difference lead-in wire (schematically, lead-in wire 970) of lead frame exposes to provide through packaging body 910 weld pad that is connected to external circuit to the open air. Although illustrative bonding wire is to manufacture from crystal grain to lead-in wire, or bonding wire also can be from crystal grain to crystal grain, and then also can be from bottom die to lead-in wire. Engage although be illustrated as wire, any intergranule can use any other applicable joining technique, and for example, via replaces.

Figure 10 is the planar side view with the multi-wafer module of the stacked memory crystal grain of different size; Concrete, Figure 10 is eight pin WSON type SPI flash memory devices 1000 comprise two stacking SPI flash memory crystal grain 1020, SPI flash memory crystal grain 1040 planar side view at packaging body 1010. The crystal grain that SPI flash memory device 1000 uses different size or shape is to avoid SPI flash memory crystal grain 1020 bottom surfaces and for example, in the interference between the wire of SPI flash memory crystal grain 1040 end faces and bonding wire (wire 1041 and the bonding wire being associated). Using any applicable material 1030, for example, is the material of adhesive or end face and the bottom surface solid that is bonding plane, to guarantee stacking SPI flash memory crystal grain 1020, SPI flash memory crystal grain 1040. SPI flash memory crystal grain 1040 uses any applicable technology, and for example adhesive 1050 or other joint materials are attached to cooling pad 1060. The part pin wire of SPI flash memory crystal grain 1020, SPI flash memory crystal grain 1040 is engaged to the difference lead-in wire (schematically, wire 1021, wire 1041 and the bonding wire being associated and lead-in wire 1070) of lead frame. Other pins only connect (for example wire 1022 and the bonding wire being associated) for inside. In crystal grain 1020,1040, judge that at crystal grain ID the pin jointly connecting of flow process can be connected to lead-in wire 1070 (or as shown in Figure 8 by wire 861, wire 863 to lead-in wire 870) by wire 1021, wire 1041 pins for signal, or can be connected to another crystal grain by wire 1022 pins. The difference lead-in wire (schematically, lead-in wire 1070, lead-in wire 1080) of lead frame exposes to provide through packaging body 1010 weld pad that is connected to external circuit to the open air. Engage although be illustrated as wire, any intergranule for example can use any other applicable joining technique, and for example, via replaces.

Stack Technology described herein and other Stack Technologies are also nonessential exclusive mutually, and plural this type of technology can be used for manufacturing any given stack. Different Stack Technologies are disclosed widely among affiliated technical field; For example, be disclosed in the Patent Application Publication case of No. 2011/0195529th, U.S. of Wu on the 11st August in 2011, above patent in full way of reference is incorporated to herein.

Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims

1. a method that determines indivedual crystal grain identifiers, is suitable for having the multiple common of indivedual unique identifiersWith encapsulation memory body crystal grain, it is characterized in that, comprising:

Enable the common connection between described memory crystal grain;

Described unique identifier based on described memory crystal grain is set up indivedual crystal grain of described memory crystal grainSelection criterion;

Synchronously described memory crystal grain is carried out to timing action; And

During the described timing action of each described memory crystal grain:

Determine when described crystal grain selection criterion be while meeting the operation that described timing moves;

Produce corresponding to the signal in the described common connection of being positioned at of described deciding step;

Before described generation step, monitor described common connection, to work as described common connectionWhile there is signal, increase crystal grain location parameter; And

Set up described crystal grain location parameter as described crystal grain identifier.

2. the method for the indivedual crystal grain identification codes of decision according to claim 1, is characterized in that, alsoComprise and set up the institute that strides across wire or via and be coupled to indivedual internal signal pins of described memory crystal grainState common connection.

3. the method for the indivedual crystal grain identification codes of decision according to claim 1, is characterized in that, instituteState memory crystal grain and be encapsulated in the multi-wafer model block configuration with multiple encapsulation pins, also comprise set up acrossCross wire or via and be coupled to indivedual interface pins of described memory crystal grain and described encapsulation pin whereinOne of described common connection.

4. the method for the indivedual crystal grain identification codes of decision according to claim 1, is characterized in that, eachThe described deciding step of described memory crystal grain comprises:

Read described unique identifier to the comparator of each described memory crystal grain;

Increase the counter of each described memory crystal grain as the fortune of the timing action of each described memory crystal grainRow is to provide count value;

The described count value of more described unique identifier is to determine that the described crystal grain selection criterion of instruction is for meetingCoupling.

5. the method for the indivedual crystal grain identification codes of decision according to claim 1, is characterized in that, eachThe described deciding step of described memory crystal grain comprises:

Be preloaded into described unique identifier to the counter of each described memory crystal grain to set up described counterNumerical value;

Operating described counter deposits to change as the operation of the described timing action of each described memory crystal grainBe stored in the described numerical value of described counter; And

Detect when the described numerical value that be stored in described counter be the numerical value predetermining, described in its instructionCrystal grain selection criterion is for meeting.

6. the method for the indivedual crystal grain identification codes of decision according to claim 1, is characterized in that, alsoComprise the described common connection of monitoring, to increase encapsulation crystal grain counting in the time that described common connection exists signalParameter.

7. the method for the indivedual crystal grain identification codes of decision according to claim 6, is characterized in that, alsoComprise and set up the institute that strides across wire or via and be coupled to indivedual internal signal pins of described memory crystal grainState common connection.

8. the method for the indivedual crystal grain identification codes of decision according to claim 6, is characterized in that, instituteState memory crystal grain and be encapsulated in the multi-wafer model block configuration with multiple encapsulation pins, also comprise set up acrossCross wire or via and be coupled to indivedual interface pins of described memory crystal grain and described encapsulation pin whereinOne of described common connection.

9. the method for the indivedual crystal grain identification codes of decision according to claim 6, is characterized in that, eachThe described deciding step of described memory crystal grain comprises:

10. the method for the indivedual crystal grain identification codes of decision according to claim 6, is characterized in that,The described deciding step of each described memory crystal grain comprises:

The method of the indivedual crystal grain identification codes of 11. decision according to claim 1, is characterized in that,During being also included in the described timing action of each described memory crystal grain, prison during described generation stepControl described common connection, to increase described crystal grain location parameter in the time the signal of described common connection being detected.

12. 1 kinds of multi-wafer modular devices, comprising:

Multiple memory crystal grain, comprise respectively unique identifier, crystal grain identifier control circuit, Duo GejieMouth pin and intercrystalline signal pin; And

Encapsulation, it holds the described multiple memory crystal grain in multi-wafer model block configuration, and described encapsulation toolHave multiple encapsulation pins, at least one of them is coupled to the institute of each described memory crystal grain to described encapsulation pinState interface pins at least one of them, wherein each described memory crystal grain has memory addressing ability;

Wherein each described crystal grain identifier control circuit comprises:

Signal circuit, is coupled to described intercrystalline signal pin;

Counter circuit, is coupled to described signal circuit and is configured to based on described uniqueWhen appearring in identifier, several clock signal starts described signal circuit; And

Event counter, is coupled to described intercrystalline signal pin and is configured to based on instituteState before several clock signals appear in unique identifier, be positioned at described intercrystalline signal pin at eachSignal increase crystal grain location parameter while occurring.

13. multi-wafer modular devices according to claim 12, is characterized in that:

Described signal circuit comprises drawing upwardly device and pull device, and described drawing upwardly device is coupled to described crystalline substanceIntergranular signal pin, described pull device is coupled to described intercrystalline signal pin, described pull device toolThere is control inputs;

Described counter circuit comprises counter and comparator, and described counter is configured to provide increaseCount value, described comparator has the first input, its be coupled to described counter, second input, itsBe coupled to described unique identifier and output, it is coupled to the described control inputs of described pull device,Described comparator is configured to producing predetermining between described count value and described unique identifierWhile relation, provide pulldown signal to described output; And

Described event counter comprises pull-down counter, and it is coupled to described intercrystalline signal pin and through joiningPut with before the relation the predetermining generation between described count value and described unique identifier, in instituteState each of intercrystalline signal pin and increase described crystal grain location parameter when drop-down.

14. multi-wafer modular devices according to claim 13, is characterized in that, described drop-down meterNumber device is also configured to each the drop-down increase encapsulation crystal grain count parameter at described intercrystalline signal pin.

15. multi-wafer modular devices according to claim 12, is characterized in that:

Described counter circuit comprises can be preloaded into counter and detector, describedly can read in advance countingDevice is configured to primitively be preloaded into described unique identifier as described counter circuit numerical value and foundationDescribed clock signal changes described counter circuit numerical value, and described detector is configured at described counterThe numerical value predetermining provides pulldown signal while occurring in described output; And

Described event counter comprises pull-down counter, is coupled to described intercrystalline signal pin and is configuredBefore occurring with the relation predetermining between described counting and described unique identifier, in describedWhen each of portion's crystal grain signal pin is drop-down, increase described crystal grain location parameter.

16. multi-wafer modular devices according to claim 15, is characterized in that, described drop-down meterNumber device is also configured to each the drop-down increase encapsulation crystal grain count parameter at described intercrystalline signal pin.

17. multi-wafer modular devices according to claim 12, is characterized in that, described in each, depositReservoir crystal grain, one of them of described intercrystalline signal pin and described interface pins is consistent.

18. multi-wafer modular devices according to claim 12, is characterized in that, described in each, depositReservoir crystal grain, described intercrystalline signal pin and described interface pins are to separate and distinguishing.

19. multi-wafer modular devices according to claim 12, is characterized in that, each described crystal grainThe described event counter of identifier control circuit is also configured to occurring number based on described unique identifierWhen individual clock signal, in the time that coming across described intercrystalline signal pin, signal increases described crystal grain location parameter.