CN105590853A - Manufacturing method for a VDMOS device - Google Patents
Manufacturing method for a VDMOS device Download PDFInfo
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- CN105590853A CN105590853A CN201410569316.2A CN201410569316A CN105590853A CN 105590853 A CN105590853 A CN 105590853A CN 201410569316 A CN201410569316 A CN 201410569316A CN 105590853 A CN105590853 A CN 105590853A
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Abstract
The invention discloses a manufacturing method for a vertical double diffused metal oxide semiconductor (VDMOS) device. The method comprises: a protection layer is formed on a first surface of a substrate; according to a preset graph, the protection layer is etched to form a window area and a protection layer graph corresponding to the preset graph is obtained; and epitaxial layers are formed at a top area and the window area of the protection graph by means of horizontal epitaxial growth. According to the method, the protection graph is formed on the substrate and the epitaxial layers are formed at the top area and the window area of the protection graph by means of horizontal epitaxial growth. The epitaxial growth direction is controlled by using the protection layer graph and the dislocation in the substrate can be stretched horizontally, so that the dislocation density of the grown epitaxial layer is 2 to 3 magnitude orders lower than that of the substrate. Therefore, the epitaxial layer quality is improved substantially and thus the electric performance of the VDMOS device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of making of VDMOS deviceMethod.
Background technology
VDMOS(VerticalDoubleDiffusedMetalOxideSemiconductor，Vertical DMOS) transistor has bipolar transistor and common MOS concurrentlyThe advantage of (MetalOxideSemiconductor, metal-oxide semiconductor (MOS)) device, nothingOpinion is switch application or linear application, and VDMOS is desirable power device, VDMOSBe mainly used in electric machine speed regulation, inverter, uninterrupted power source, electronic switch, high-fidelity music center,Car electrics and electric ballast etc. The manufacture process of VDMOS is: first, and in heavy dopingN+ Grown one deck N-type epitaxial layer; Secondly, by twice horizontal stroke in P type base and N+ source regionDifference to diffusion junction depth forms raceway groove, and these two regions are all to pass through grid in ion implantation processSelf-registered technology is injected impurity separately.
General VDMOS device is on the epitaxial wafer of silicon-based substrate, to manufacture and form, epitaxial waferQuality directly have influence on the electrical characteristics of VDMOS device, due to the manufacture in silicon-based substrateCheng Zhong, unavoidably can introduce a large amount of defects and lattice dislocation. For semi-conducting material andSpeech, dislocation is a kind of more common defect in semi-conducting material, refers to the local irregularities of atomArrange, to semi-conducting material and the performance of semiconductor devices of making thereon can produce seriouslyImpact. A large amount of dislocations can extend upwardly in epitaxial layer, and the dislocation in these epitaxial layers can becomeMainly former for what puncture in the follow-up VDMOS device surface electric leakage of making thereon and bodyCause.
Therefore, how to control defect and dislocation in epitaxial layer, become and promote VDMOS deviceA very important key of performance.
Summary of the invention
Exist dislocation defects to produce the electrical characteristics of VDMOS device in order to solve existing epitaxial layerThe technical problem of adverse effect, the invention provides a kind of preparation method of VDMOS device,Comprise:
On the first surface of substrate, form protective layer;
According to default figure, described protective layer is carried out to etching and form window area, obtain with describedThe default corresponding protective layer figure of figure;
Adopt upper area and the window region of transversal epitaxial growth mode at described protective layer figureTerritory forms epitaxial layer.
Optionally, described substrate is monocrystalline silicon, and described protective layer is silica or silicon nitride.
Optionally, described according to default figure to described protective layer carry out etching form window regionTerritory, obtains comprising with the corresponding protective layer figure of described default figure:
On described protective layer, form photoresist, and utilize the mask plate with described default figureDescribed photoresist is exposed, form and the corresponding photoetching offset plate figure of described default figure;
According to described photoetching offset plate figure, described protective layer is carried out to etching, obtain and described default figureThe corresponding protective layer figure of shape;
Peel off the photoetching offset plate figure of described protective layer figure top.
Optionally, described default figure is: any one in square, circle or rhombus.
Optionally, described transversal epitaxial growth mode comprises:
The outer layer growth direction of described window area is perpendicular to described substrate upwards;
The outer layer growth direction of described protective layer figure upper area is for being parallel to described substrate,And taking described window area as symmetrical centre to contrary two oppositely.
Optionally, after described formation epitaxial layer, also comprise:
Adopt epitaxial growth mode or transversal epitaxial growth mode to repeat shape on described epitaxial layerBecome epitaxial layer.
Optionally, the number of plies of described epitaxial layer is at least 1 layer, mostly is 5 layers most.
Optionally, above described epitaxial layer, form successively grid oxic horizon, polysilicon layer, JieMatter layer and the first metal layer, and grid using described polysilicon layer as VDMOS device,Source electrode using the first metal layer as VDMOS device.
Optionally, deposit the second metal level at the second surface of described substrate, described in etching formsThe drain electrode of VDMOS device.
Optionally, before the drain electrode of described formation VDMOS device, also comprise:
The second surface of described substrate is carried out to technique for thinning back side, remove described substrate and described inProtective layer figure.
Method provided by the invention first forms protective layer figure on substrate, adopts afterwards horizontalForm epitaxial layer, profit to epitaxial growth mode at upper area and the window area of protective layer figureWith protective layer figure, epitaxial growth direction is controlled, the dislocation in substrate laterally can be drawnStretch, the dislocation density of the epitaxial layer of growth can a low 2-3 order of magnitude compared with substrate thus, canSignificantly improve epitaxial layer quality, and then improve the electrical property of VDMOS device.
Brief description of the drawings
The steps flow chart of the preparation method of a kind of VDMOS device that Fig. 1 provides for the present embodimentFigure;
Fig. 2 is the flow chart of steps of step S20 in the present embodiment;
Fig. 3 is at the schematic diagram of making one deck silica 02 on silicon substrate 01 in the present embodiment;
Fig. 4 exposes and forms the schematic diagram of photoetching offset plate figure in the present embodiment on silica 02;
Fig. 5 is the schematic diagram that forms silica figure in the present embodiment on silicon substrate 01;
Fig. 6 is the direction schematic diagram of transversal epitaxial growth in the present embodiment;
Fig. 7 is the schematic diagram that forms epitaxial layer in the present embodiment;
Fig. 8 is the schematic diagram of the VDMOS device that finally obtains in the present embodiment.
Detailed description of the invention
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is done further in detailDescribe. Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
On the basis making in traditional VDMOS device epitaxial slice, the present embodiment adopts laterallyThe mode of extension is carried out grown epitaxial layer, and a kind of preparation method of VDMOS device is provided,Steps flow chart as shown in Figure 1, comprises the following steps:
Step S10, on the first surface of substrate, form protective layer.
Step S20, according to default figure to protective layer carry out etching form window area, obtainWith the corresponding protective layer figure of default figure.
Step S30, adopt transversal epitaxial growth mode upper area and the window at protective layer figurePort area forms epitaxial layer.
The wafer of making formation epitaxial layer on substrate is exactly epitaxial wafer, and different backing materials needsOtherwise same growth technology, chip manufacture technology and device packaging technique, backing material certainlyDetermined the development course of semiconductor lighting technology, the thickness of epitaxial layer is micron order, generally 2～Between 20 μ m, and the thickness of the relative epitaxial layer of thickness of substrate is larger, is generally hundreds ofμ m. Utilize the epitaxial layer dislocation density that the preparation method of above-mentioned VDMOS device obtains canBy 2-3 the order of magnitude, can reduce the adverse effect that dislocation defects brings, outside significantly improvingProlong a layer quality.
Optionally, wherein substrate can be monocrystalline silicon, corresponding protective layer can be silica orSilicon nitride.
Optionally, step S20 carries out etching according to default figure to protective layer and forms window area,Obtain and the corresponding protective layer figure of default figure, steps flow chart as shown in Figure 2, comprises followingStep:
Step S201, on protective layer, form photoresist, and utilize the mask with default figurePlate exposes to photoresist, forms and the corresponding photoetching offset plate figure of default figure.
Step S202, according to photoetching offset plate figure, protective layer is carried out to etching, obtain and default figureCorresponding protective layer figure.
Step S203, peel off the photoetching offset plate figure of protective layer figure top.
Optionally, transversal epitaxial growth (LateralEpitaxyOvergrowth is called for short LEO)Technology is to transfer the major part of growth to cross growth by longitudinal growth, makes in horizontal outgrowthDefect upwardly extending trend in district's is inhibited, thereby reduces defect concentration, transversal epitaxial growthMode comprises:
The outer layer growth direction of window area is perpendicular to substrate upwards;
The outer layer growth direction of protective layer figure upper area is for being parallel to substrate, and with windowRegion be symmetrical centre to contrary two oppositely.
Optionally, after utilizing transversal epitaxial growth formation epitaxial layer, also comprise:
Adopt epitaxial growth mode or transversal epitaxial growth mode on epitaxial layer, to repeat to form manyLayer epitaxial layer. Preferably, the number of plies of epitaxial layer is at least 1 layer, mostly is 5 layers most, if extensionLayer only has one deck, needs to adopt transversal epitaxial growth mode to grow; If epitaxial layer is notOnly one deck, at least ground floor epitaxial layer need to adopt transversal epitaxial growth mode to grow,Epitaxial layer afterwards can adopt transversal epitaxial growth mode to grow, and also can adopt commonGrowth pattern. Generally, in order to improve epitaxial layer quality, can, on the basis of epitaxial layer 1, continueThe continuous method grown epitaxial layer 2 that adopts horizontal extension, epitaxial layer 3 ... but, the layer of epitaxial layerNumber is not The more the better, and the result obtaining according to test of many times is, outside 3 layers of left and rightProlong the epitaxial layer quality that obtains of layer relatively good, if continued growth again, for epitaxial layer defect andThe minimizing of dislocation is just so obvious, and exceed after 5 layers, is subject to equipment or environmentImpact, continued growth also may make epitaxial layer quality variation, and therefore general epitaxial layer is1～5 layer, be preferably 3 layers.
Optionally, form epitaxial layer and start to make VDMOS device afterwards, above epitaxial layerForm successively grid oxic horizon, polysilicon layer, dielectric layer and the first metal layer, and by polycrystallineSilicon layer is as the grid of VDMOS device, the source using the first metal layer as VDMOS deviceThe utmost point.
Optionally, deposit the second metal level at the second surface of substrate, etching forms VDMOSThe drain electrode of device.
Optionally, before forming the drain electrode of VDMOS device, also comprise:
The second surface of substrate is carried out to technique for thinning back side, remove substrate and protective layer figureShape, the ability significantly puncturing in the anti-surface leakage of boost device and body. Outside commonProlong layer and in growth course, have a lot of defects and dislocation, this defect and dislocation can becomeIn follow-up VDMOS device body of making thereon, puncture or the center of surface leakage. And adoptMake the epitaxial layer obtaining by transversal epitaxial growth mode, dislocation density reduces, thus deviceElectrical characteristics also can promote.
Embodiment using monocrystalline silicon as substrate describes below, specifically comprises:
First, step S10 makes one deck silica 02 as protective layer on silicon substrate 01,As shown in Figure 3. The selection of backing material depends primarily on the following aspects: architectural characteristic,Interfacial characteristics, chemical stability, thermal property, electric conductivity, optical property and machineryPerformance, need to consider above-mentioned several aspect while selecting substrate and corresponding epitaxial layer. Due toSilicon is hot good conductor, the heat conductivility of device is better, extends device lifetime thereby reachObject, therefore describes as an example of silicon substrate example in the present embodiment, but need to illustrateBe, backing material be except being silicon (Si), can also be carborundum (SiC),Gallium nitride (GaN) or GaAs (GaAS) etc. In addition, for architectural characteristic,In the time that the crystal structure of epitaxial material and substrate is identical or close, lattice constant mismatch degree is little,Crystal property is good, defect concentration is little, therefore can pass through change and the device of growth technologyThe adjustment of processing technology adapts to research and development and the life of the light emitting semiconductor device on different substratesProduce.
Because the protective layer in the present embodiment is between substrate and epitaxial layer, if wherein protectedWhen sheath is silica, directly silicon substrate certain depth is oxidized and can be oxidizedSilicon, makes simple; And if protective layer is while being silicon nitride, forms the process bag of silicon nitrideDraw together: first form one deck thin liquid aluminium lamination in surface of silicon, this liquid state aluminium lamination mainEffect is the formation that stops unbodied silicon nitride layer; Then one deck high-temperature ammonolysis aluminium of growing is slowPunching layer, in this aluminum nitride buffer layer, the content of aluminium is greater than the content of nitrogen. Therefore, than nitrogenSiClx also needs the complex processes such as deposition growing while making, utilizes silica straight as protective layerThe operation that connects protective layer is very simple.
Optionally, step S20 carries out etching according to default figure to protective layer and forms window area,Obtain and the corresponding protective layer figure of default figure, comprise the following steps:
Step S201, at the upper photoresist that forms of protective layer (namely silica 02), and utilizeThe mask plate with default figure exposes to photoresist, forms and the corresponding light of default figureCarve glue pattern 03.
Optionally, in the present embodiment, default figure is: any one in square, circle or rhombusKind, specifically select which kind of shape to determine according to process equipment and condition. The shape of default figureShape is mainly and relevant, the different figure in crystal orientation (such as 100,110,010 etc.) of substrateShape need match from different substrate crystal orientation, and the epitaxial layer quality of growth could be better. Meanwhile,Graphics shape is also relevant with process equipment, such as there being some equipment to be bad at etching circular hole, and can onlySelect square hole, main purpose is in order to obtain better figure pattern. Presetting in the present embodimentImage is preferably square opening, and on silica 02, exposure forms photoetching offset plate figure as shown in Figure 403。
Step S202, according to photoetching offset plate figure 03, protective layer is carried out to etching, obtain and default figureThe corresponding protective layer figure of shape.
Step S203, peel off the photoetching offset plate figure of protective layer figure top, on silicon substrate 01 onlyRemaining have and default square identical silica figure 02 ', as shown in Figure 5, adjacentBetween two silica, there is window area W.
Afterwards according to carrying out epitaxial growth shown in Fig. 6, the window area W of silica laterally outsideEpitaxial growth obtains epitaxial layer, and the direction of arrow shown in Fig. 6 is outer layer growth direction. Concrete:The outer layer growth direction of window area W is perpendicular to silicon substrate 01 upwards; Silica figureThe outer layer growth direction of 02 ' upper area is for being parallel to substrate, and taking window area W as rightIn title mind-set contrary two oppositely, in Fig. 6 taking 3 window areas as example. Through epitaxial growthObtain epitaxial layer 04 as shown in Figure 7, the concrete thickness of epitaxial layer 04 can according to need not apply intoRow regulates. The withstand voltage size of the VDMOS device directly determining such as different epitaxial thicknesses,If high-voltage product, epitaxy layer thickness needs thickening; If low voltage product does not needThick epitaxial layer.
Preferably, in the present embodiment, the conduction type of silicon substrate 01 is N-type, corresponding formationEpitaxial layer 04 is N-type epitaxial layer. After epitaxial layer 04 forms, in high temperature furnace pipe, be oxidizedOperation, forms grid oxic horizon 05, and forms grid polycrystalline silicon on the surface of grid oxic horizon 05Region, drives in boron ion on epitaxial layer 04 surface, forms P-tagma 06. Further, formAfter P-tagma 06, apply photoresist in grid oxic horizon 05 surface element subregion, utilize photoresistAnd the stopping of grid polycrystalline silicon region, to N-type epitaxial layer 04 inject phosphonium ion or arsenic fromSon, and then form N+ source region 07. Further, after forming N+ source region 07, many at gridCrystal silicon region and grid oxic horizon 05 surface form one deck silicon nitride layer (not shown), andEtch away unnecessary silicon nitride, form side wall in grid polycrystalline silicon region side walls, utilize grid manyBlocking at the dark tagma of P+ 08 B Implanted ion of crystal silicon region and side wall. Further, at gridDeposit spathic silicon in utmost point oxide layer 05, forms polysilicon layer 09, sets it as VDMOS deviceGrid, afterwards through forming material layer and corresponding composition technique forms respectively dielectric layer 10With the first metal layer 11, and source electrode using the first metal layer as VDMOS device, finallyThe schematic diagram of the VDMOS device arriving as shown in Figure 8.
It should be noted that, deposit the second metal level at the second surface of silicon substrate 01 and formThe drain electrode (not shown in Fig. 8) of VDMOS device. Also it should be noted that, at silicon substrate 01Second surface deposit before the second metal level and can also first carry out technique for thinning back side, utilize thingReason mode is never polished the second surface excess stock of silicon substrate 01 or did not processSurface grind off, until wafer thickness reaches requirement, generally retain 100～300 μ m. This stepSuddenly silicon substrate 01 and silica figure 02 ' all can also be polished off, finally directly in extensionOn layer 04, depositing metal layers forms the drain electrode of VDMOS device.
Method provided by the invention first forms protective layer figure on substrate, adopts afterwards horizontalForm epitaxial layer, profit to epitaxial growth mode at upper area and the window area of protective layer figureWith protective layer figure, epitaxial growth direction is controlled, the dislocation in substrate laterally can be drawnStretch, the dislocation density of the epitaxial layer of growth can a low 2-3 order of magnitude compared with substrate thus, canSignificantly improve epitaxial layer quality, and then improve the electrical property of VDMOS device. At of substrateTwo surfaces are carried out technique for thinning back side substrate are polished, the significantly anti-surface of boost deviceThe ability puncturing in electric leakage and body.
Above embodiment is only for the present invention is described, and limitation of the present invention is not relevantThe those of ordinary skill of technical field, without departing from the spirit and scope of the present invention,Can also make a variety of changes and modification, therefore all technical schemes that are equal to also belong to the present inventionCategory, scope of patent protection of the present invention should be defined by the claims.
Claims (10)
1. a preparation method for VDMOS device, is characterized in that, comprising:
On the first surface of substrate, form protective layer;
According to default figure, described protective layer is carried out to etching and form window area, obtain with describedThe default corresponding protective layer figure of figure;
Adopt upper area and the window region of transversal epitaxial growth mode at described protective layer figureTerritory forms epitaxial layer.
2. method according to claim 1, is characterized in that, described substrate is monocrystallineSilicon, described protective layer is silica or silicon nitride.
3. method according to claim 1, is characterized in that, described according to default figureDescribed protective layer is carried out to etching and form window area, obtain protecting accordingly with described default figureSheath figure comprises:
On described protective layer, form photoresist, and utilize the mask plate with described default figureDescribed photoresist is exposed, form and the corresponding photoetching offset plate figure of described default figure;
According to described photoetching offset plate figure, described protective layer is carried out to etching, obtain and described default figureThe corresponding protective layer figure of shape;
Peel off the photoetching offset plate figure of described protective layer figure top.
4. method according to claim 1, is characterized in that, described default figure is:Any one in square, circle or rhombus.
5. method according to claim 1, is characterized in that, described transversal epitaxial growthMode comprises:
The outer layer growth direction of described window area is perpendicular to described substrate upwards;
The outer layer growth direction of described protective layer figure upper area is for being parallel to described substrate,And taking described window area as symmetrical centre to contrary two oppositely.
6. method according to claim 1, is characterized in that, described formation epitaxial layer itAfter, also comprise:
Adopt epitaxial growth mode or transversal epitaxial growth mode to repeat shape on described epitaxial layerBecome epitaxial layer.
7. method according to claim 6, is characterized in that, the number of plies of described epitaxial layerBe at least 1 layer, mostly be 5 layers most.
8. according to the method described in any one in claim 1-7, it is characterized in that, describedEpitaxial layer top forms grid oxic horizon, polysilicon layer, dielectric layer and the first metal layer successively,And grid using described polysilicon layer as VDMOS device, using the first metal layer asThe source electrode of VDMOS device.
9. method according to claim 1, is characterized in that, at second of described substrateSurface deposition the second metal level, etching forms the drain electrode of described VDMOS device.
10. method according to claim 9, is characterized in that, described formation VDMOSBefore the drain electrode of device, also comprise:
The second surface of described substrate is carried out to technique for thinning back side, remove described substrate and described inProtective layer figure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410569316.2A CN105590853A (en) | 2014-10-22 | 2014-10-22 | Manufacturing method for a VDMOS device |
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| CN201410569316.2A CN105590853A (en) | 2014-10-22 | 2014-10-22 | Manufacturing method for a VDMOS device |
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| CN201410569316.2A Pending CN105590853A (en) | 2014-10-22 | 2014-10-22 | Manufacturing method for a VDMOS device |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4879254A (en) * | 1987-06-10 | 1989-11-07 | Nippondenso Co., Ltd. | Method of manufacturing a DMOS |
| CN101764055A (en) * | 2009-10-19 | 2010-06-30 | 金柯 | Epitaxy-based method for improving the quality of GaN films |
-
2014
- 2014-10-22 CN CN201410569316.2A patent/CN105590853A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4879254A (en) * | 1987-06-10 | 1989-11-07 | Nippondenso Co., Ltd. | Method of manufacturing a DMOS |
| CN101764055A (en) * | 2009-10-19 | 2010-06-30 | 金柯 | Epitaxy-based method for improving the quality of GaN films |
Non-Patent Citations (1)
| Title |
|---|
| 考林基: "《SOI技术 21世纪的硅集成电路技术》", 31 December 1993, 北京：科学出版社 * |
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